Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 262906240 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 186275056 1 T1 932 T2 1054 T3 220



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 233136993 1 T1 1171 T2 839 T3 92
values[0x0] 103797231 1 T1 500 T2 505 T3 69
values[0x1] 112247072 1 T1 448 T2 511 T3 74



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 204341298 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 244839998 1 T1 1303 T2 1221 T3 221



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 1392231 1 T2 5 T17 421 T36 1
valid_sources[0x01] 1398424 1 T2 5 T17 353 T36 4
valid_sources[0x02] 1392495 1 T2 9 T17 397 T36 4
valid_sources[0x03] 1394357 1 T2 7 T17 431 T36 1
valid_sources[0x04] 1573049 1 T2 10 T17 427 T36 5
valid_sources[0x05] 1394061 1 T2 4 T17 400 T36 10
valid_sources[0x06] 1396500 1 T2 3 T17 360 T36 7
valid_sources[0x07] 1386863 1 T2 9 T17 395 T36 9
valid_sources[0x08] 1523689 1 T2 8 T17 397 T36 11
valid_sources[0x09] 2061749 1 T2 9 T17 371 T36 9
valid_sources[0x0a] 1447984 1 T2 20 T17 398 T36 4
valid_sources[0x0b] 1387079 1 T2 5 T17 365 T36 8
valid_sources[0x0c] 1386265 1 T2 9 T17 431 T36 9
valid_sources[0x0d] 2041341 1 T2 4 T17 391 T36 5
valid_sources[0x0e] 2323378 1 T2 4 T17 446 T36 12
valid_sources[0x0f] 1388099 1 T2 8 T17 442 T36 7
valid_sources[0x10] 1556134 1 T2 12 T17 362 T36 2
valid_sources[0x11] 1387712 1 T2 11 T17 355 T36 3
valid_sources[0x12] 1422909 1 T2 3 T17 451 T36 9
valid_sources[0x13] 1388396 1 T2 10 T17 451 T36 4
valid_sources[0x14] 1424279 1 T2 8 T17 423 T36 3
valid_sources[0x15] 1406699 1 T2 4 T17 445 T36 5
valid_sources[0x16] 1384467 1 T2 7 T17 409 T36 5
valid_sources[0x17] 2001618 1 T2 9 T17 449 T36 2
valid_sources[0x18] 1387195 1 T2 7 T17 445 T36 2
valid_sources[0x19] 1504092 1 T2 5 T17 419 T36 3
valid_sources[0x1a] 2554025 1 T2 9 T17 427 T36 5
valid_sources[0x1b] 1390068 1 T2 6 T17 437 T36 7
valid_sources[0x1c] 1389860 1 T2 5 T17 415 T36 5
valid_sources[0x1d] 1399683 1 T2 7 T17 428 T36 3
valid_sources[0x1e] 1512194 1 T2 7 T17 411 T36 4
valid_sources[0x1f] 1418916 1 T2 12 T17 366 T36 8
valid_sources[0x20] 2703960 1 T2 2 T17 406 T36 7
valid_sources[0x21] 1394011 1 T2 8 T17 391 T36 5
valid_sources[0x22] 1387437 1 T17 429 T36 10 T6 147
valid_sources[0x23] 1396725 1 T2 7 T17 441 T36 10
valid_sources[0x24] 1389512 1 T2 12 T17 437 T36 11
valid_sources[0x25] 4228964 1 T2 7 T17 392 T36 8
valid_sources[0x26] 1420926 1 T2 8 T17 407 T36 4
valid_sources[0x27] 1393533 1 T2 3 T17 378 T36 6
valid_sources[0x28] 1390022 1 T2 9 T17 460 T36 13
valid_sources[0x29] 3421253 1 T2 9 T17 420 T36 7
valid_sources[0x2a] 1395234 1 T2 12 T17 342 T36 7
valid_sources[0x2b] 1419224 1 T2 12 T17 401 T36 10
valid_sources[0x2c] 1390363 1 T2 5 T17 418 T36 8
valid_sources[0x2d] 1507173 1 T2 8 T17 413 T36 8
valid_sources[0x2e] 1394753 1 T2 8 T17 440 T36 6
valid_sources[0x2f] 1405937 1 T2 8 T17 493 T36 7
valid_sources[0x30] 2044221 1 T2 9 T17 411 T36 3
valid_sources[0x31] 1388895 1 T2 8 T17 463 T36 4
valid_sources[0x32] 3840410 1 T2 4 T17 424 T36 8
valid_sources[0x33] 1838911 1 T2 8 T17 460 T36 9
valid_sources[0x34] 1467013 1 T2 1 T17 425 T36 10
valid_sources[0x35] 1509935 1 T2 4 T17 428 T36 7
valid_sources[0x36] 1795630 1 T2 6 T17 414 T36 4
valid_sources[0x37] 1389049 1 T2 3 T17 431 T36 10
valid_sources[0x38] 1386989 1 T2 9 T17 440 T36 10
valid_sources[0x39] 1388245 1 T2 7 T17 385 T36 4
valid_sources[0x3a] 1576698 1 T2 3 T17 455 T36 3
valid_sources[0x3b] 1392107 1 T2 3 T17 457 T36 4
valid_sources[0x3c] 1401173 1 T2 7 T17 396 T36 7
valid_sources[0x3d] 1390211 1 T2 4 T17 428 T36 2
valid_sources[0x3e] 1397582 1 T2 4 T17 439 T36 10
valid_sources[0x3f] 5001140 1 T2 8 T17 427 T6 129
valid_sources[0x40] 1413055 1 T2 7 T17 419 T36 6
valid_sources[0x41] 1421228 1 T2 1 T17 378 T36 10
valid_sources[0x42] 1392736 1 T2 5 T17 400 T36 6
valid_sources[0x43] 1653557 1 T2 5 T17 337 T36 2
valid_sources[0x44] 2587642 1 T2 10 T17 405 T36 9
valid_sources[0x45] 2103980 1 T2 5 T17 461 T36 5
valid_sources[0x46] 3548348 1 T2 3 T17 429 T36 7
valid_sources[0x47] 4500729 1 T2 9 T17 435 T36 8
valid_sources[0x48] 1426916 1 T2 8 T17 430 T36 4
valid_sources[0x49] 1391427 1 T2 9 T17 437 T36 4
valid_sources[0x4a] 4001750 1 T2 5 T17 434 T36 1
valid_sources[0x4b] 1573628 1 T2 7 T17 416 T36 4
valid_sources[0x4c] 1488286 1 T2 6 T17 455 T36 8
valid_sources[0x4d] 2640651 1 T2 5 T17 434 T36 9
valid_sources[0x4e] 1516430 1 T2 10 T17 421 T36 3
valid_sources[0x4f] 1392752 1 T2 5 T17 431 T36 2
valid_sources[0x50] 1389977 1 T2 3 T17 359 T36 10
valid_sources[0x51] 1384981 1 T2 5 T17 430 T36 18
valid_sources[0x52] 1396273 1 T2 6 T17 402 T36 3
valid_sources[0x53] 2244239 1 T2 11 T17 425 T36 6
valid_sources[0x54] 1390951 1 T2 16 T17 391 T36 11
valid_sources[0x55] 1395714 1 T2 7 T17 461 T36 10
valid_sources[0x56] 1392397 1 T2 5 T17 447 T36 7
valid_sources[0x57] 2240421 1 T2 4 T17 386 T36 4
valid_sources[0x58] 2073309 1 T2 5 T17 389 T36 10
valid_sources[0x59] 3381390 1 T2 9 T17 388 T36 7
valid_sources[0x5a] 1430648 1 T2 2 T17 446 T36 10
valid_sources[0x5b] 1836755 1 T2 11 T17 397 T36 4
valid_sources[0x5c] 1393671 1 T2 9 T17 417 T36 2
valid_sources[0x5d] 1387231 1 T2 9 T17 457 T36 4
valid_sources[0x5e] 1389419 1 T2 7 T17 406 T36 7
valid_sources[0x5f] 1838145 1 T2 5 T17 352 T36 14
valid_sources[0x60] 2264010 1 T2 11 T17 395 T36 11
valid_sources[0x61] 3338837 1 T2 5 T17 487 T36 6
valid_sources[0x62] 1844461 1 T2 17 T17 528 T36 5
valid_sources[0x63] 1390371 1 T2 10 T17 328 T36 9
valid_sources[0x64] 3732821 1 T2 13 T17 371 T36 11
valid_sources[0x65] 1389627 1 T2 6 T17 392 T36 7
valid_sources[0x66] 1395852 1 T2 8 T17 392 T36 3
valid_sources[0x67] 1871238 1 T2 5 T17 436 T36 11
valid_sources[0x68] 1388997 1 T2 10 T17 385 T36 9
valid_sources[0x69] 1393518 1 T2 2 T17 432 T36 3
valid_sources[0x6a] 1393986 1 T2 14 T17 362 T36 13
valid_sources[0x6b] 1388779 1 T2 7 T17 442 T36 9
valid_sources[0x6c] 2369418 1 T2 13 T17 427 T36 6
valid_sources[0x6d] 1538600 1 T2 8 T17 413 T6 118
valid_sources[0x6e] 1391281 1 T2 8 T17 451 T36 4
valid_sources[0x6f] 1387697 1 T2 7 T17 436 T36 1
valid_sources[0x70] 1393401 1 T2 5 T17 369 T36 7
valid_sources[0x71] 1554616 1 T2 2 T17 414 T36 7
valid_sources[0x72] 1386329 1 T2 11 T17 444 T36 3
valid_sources[0x73] 1395297 1 T2 8 T17 450 T36 17
valid_sources[0x74] 1383862 1 T2 7 T17 423 T36 14
valid_sources[0x75] 1399671 1 T2 8 T17 353 T36 5
valid_sources[0x76] 2255654 1 T2 6 T17 440 T36 1
valid_sources[0x77] 1390920 1 T2 8 T17 420 T36 2
valid_sources[0x78] 1394225 1 T2 10 T17 441 T36 4
valid_sources[0x79] 1732443 1 T2 5 T17 378 T36 6
valid_sources[0x7a] 1390059 1 T2 1 T17 427 T36 7
valid_sources[0x7b] 1398180 1 T2 10 T17 371 T36 5
valid_sources[0x7c] 1390938 1 T2 9 T17 392 T36 5
valid_sources[0x7d] 1566458 1 T2 6 T17 449 T36 3
valid_sources[0x7e] 1398724 1 T2 8 T17 452 T36 10
valid_sources[0x7f] 1394061 1 T2 5 T17 428 T36 2
valid_sources[0x80] 1389606 1 T2 6 T17 390 T36 5



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 72392738 1 T1 45 T2 344 T3 87
values[0x0] all_enables biggest_size 61219722 1 T1 474 T2 380 T3 65
values[0x1] all_enables biggest_size 52662596 1 T1 413 T2 330 T3 68

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%