Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

264518594

1

T1

1187

T2

801

T3

15

full_word

186376691

1

T1

932

T2

1054

T3

220

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	450894965	1			T1	2119		T2	1855		T3	235
auto[TlIntgErrCmd]	100	1			T142	8		T143	7		T144	1
auto[TlIntgErrData]	107	1			T142	8		T143	6		T144	2
auto[TlIntgErrBoth]	113	1			T142	4		T143	7		T144	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

233450467

1

T1

1171

T2

839

T3

92

auto[1]

217444818

1

T1

948

T2

1016

T3

143

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	161031762	1			T1	1126		T2	495		T3	5
auto[TlIntgErrNone]	partial	auto[1]	103486530	1			T1	61		T2	306		T3	10
auto[TlIntgErrNone]	full_word	auto[0]	72418578	1			T1	45		T2	344		T3	87
auto[TlIntgErrNone]	full_word	auto[1]	113958095	1			T1	887		T2	710		T3	133
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T142	1		T143	2		T144	1
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T142	5		T143	5		T185	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T186	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T142	2		T204	1		-	-
auto[TlIntgErrData]	partial	auto[0]	41	1			T142	5		T143	1		T185	7
auto[TlIntgErrData]	partial	auto[1]	61	1			T142	3		T143	5		T144	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T144	1		T205	1		T206	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T207	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T142	1		T143	3		T144	3
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T142	3		T143	4		T144	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T144	1		T208	1		T209	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T186	1		T206	1		T210	1