Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	375042	0	0
entropy_period_rd_A	2147483647	2346	0	0
intr_enable_rd_A	2147483647	3096	0	0
prefix_0_rd_A	2147483647	2381	0	0
prefix_10_rd_A	2147483647	2256	0	0
prefix_1_rd_A	2147483647	2221	0	0
prefix_2_rd_A	2147483647	2407	0	0
prefix_3_rd_A	2147483647	2328	0	0
prefix_4_rd_A	2147483647	2347	0	0
prefix_5_rd_A	2147483647	2283	0	0
prefix_6_rd_A	2147483647	2334	0	0
prefix_7_rd_A	2147483647	2245	0	0
prefix_8_rd_A	2147483647	2202	0	0
prefix_9_rd_A	2147483647	2208	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	375042	0	0
T72	738560	102466	0	0
T73	0	20387	0	0
T74	0	98538	0	0
T92	0	112929	0	0
T142	0	3	0	0
T148	0	38237	0	0
T149	0	1	0	0
T150	0	184	0	0
T151	0	23	0	0
T152	0	279	0	0
T154	661493	0	0	0
T155	496023	0	0	0
T156	702543	0	0	0
T157	982959	0	0	0
T158	621058	0	0	0
T159	10285	0	0	0
T160	342426	0	0	0
T161	350213	0	0	0
T162	408208	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2346	0	0
T144	10760	33	0	0
T149	4600	3	0	0
T176	2146	4	0	0
T177	2906	14	0	0
T178	11568	64	0	0
T179	7629	26	0	0
T180	10939	17	0	0
T181	72277	112	0	0
T182	1809	7	0	0
T183	11160	32	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3096	0	0
T144	10760	69	0	0
T149	4600	12	0	0
T177	2906	5	0	0
T178	11568	73	0	0
T179	7629	24	0	0
T180	10939	35	0	0
T181	72277	168	0	0
T182	1809	11	0	0
T183	11160	23	0	0
T184	26502	190	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2381	0	0
T144	10760	10	0	0
T149	4600	5	0	0
T176	2146	6	0	0
T178	11568	36	0	0
T179	7629	19	0	0
T180	10939	22	0	0
T181	72277	208	0	0
T182	1809	3	0	0
T183	11160	53	0	0
T184	26502	253	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2256	0	0
T144	10760	27	0	0
T177	2906	10	0	0
T178	11568	44	0	0
T179	7629	16	0	0
T180	10939	65	0	0
T181	72277	193	0	0
T182	1809	6	0	0
T183	11160	14	0	0
T184	26502	175	0	0
T185	23279	91	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2221	0	0
T144	10760	23	0	0
T149	4600	9	0	0
T176	2146	1	0	0
T177	2906	12	0	0
T178	11568	28	0	0
T179	7629	14	0	0
T180	10939	24	0	0
T181	72277	221	0	0
T182	1809	1	0	0
T183	11160	20	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2407	0	0
T144	10760	39	0	0
T149	4600	12	0	0
T176	2146	2	0	0
T177	2906	7	0	0
T178	11568	40	0	0
T179	7629	14	0	0
T180	10939	36	0	0
T181	72277	244	0	0
T182	1809	9	0	0
T183	11160	40	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2328	0	0
T144	10760	33	0	0
T149	4600	8	0	0
T176	2146	1	0	0
T177	2906	10	0	0
T178	11568	13	0	0
T179	7629	18	0	0
T180	10939	32	0	0
T181	72277	275	0	0
T182	1809	4	0	0
T183	11160	33	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2347	0	0
T144	10760	17	0	0
T149	4600	3	0	0
T176	2146	9	0	0
T177	2906	8	0	0
T178	11568	52	0	0
T179	7629	14	0	0
T180	10939	68	0	0
T181	72277	220	0	0
T182	1809	3	0	0
T183	11160	16	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2283	0	0
T144	10760	22	0	0
T149	4600	8	0	0
T176	2146	4	0	0
T177	2906	10	0	0
T178	11568	45	0	0
T179	7629	15	0	0
T180	10939	20	0	0
T181	72277	187	0	0
T182	1809	7	0	0
T183	11160	48	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2334	0	0
T144	10760	25	0	0
T149	4600	1	0	0
T176	2146	8	0	0
T177	2906	11	0	0
T178	11568	26	0	0
T179	7629	27	0	0
T180	10939	63	0	0
T181	72277	254	0	0
T182	1809	1	0	0
T183	11160	43	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2245	0	0
T144	10760	54	0	0
T149	4600	5	0	0
T176	2146	3	0	0
T177	2906	10	0	0
T178	11568	18	0	0
T179	7629	23	0	0
T180	10939	31	0	0
T181	72277	195	0	0
T182	1809	3	0	0
T183	11160	78	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2202	0	0
T144	10760	17	0	0
T176	2146	6	0	0
T178	11568	57	0	0
T179	7629	14	0	0
T180	10939	48	0	0
T181	72277	213	0	0
T183	11160	24	0	0
T184	26502	246	0	0
T185	23279	73	0	0
T186	24507	69	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2208	0	0
T144	10760	26	0	0
T149	4600	5	0	0
T176	2146	5	0	0
T177	2906	3	0	0
T178	11568	47	0	0
T179	7629	2	0	0
T180	10939	87	0	0
T181	72277	278	0	0
T182	1809	5	0	0
T183	11160	74	0	0