Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	258638640	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

183805977

1

T1

927622

T2

927810

T3

910888

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	229525062	1			T1	118130		T2	118826		T3	119756
values[0x0]	102355765	1			T1	556837		T2	559115		T3	555946
values[0x1]	110563790	1			T1	604251		T2	608918		T3	607371

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	201041638	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

241402979

1

T1

123925

T2

124327

T3

123256

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1384154	1			T2	9441		T3	9223		T7	343
valid_sources[0x01]	1372807	1			T2	9345		T3	9270		T7	413
valid_sources[0x02]	1397532	1			T2	9513		T3	9270		T7	333
valid_sources[0x03]	1556823	1			T2	8948		T3	9363		T7	380
valid_sources[0x04]	2052583	1			T2	9116		T3	9335		T7	394
valid_sources[0x05]	1380659	1			T2	9460		T3	9171		T7	282
valid_sources[0x06]	1379209	1			T2	9181		T3	9097		T7	295
valid_sources[0x07]	1380960	1			T2	9880		T3	9025		T7	318
valid_sources[0x08]	1382366	1			T2	9898		T3	9298		T7	269
valid_sources[0x09]	1382809	1			T2	8996		T3	9333		T7	279
valid_sources[0x0a]	1373954	1			T2	9288		T3	9365		T7	323
valid_sources[0x0b]	1381770	1			T2	9648		T3	9313		T7	299
valid_sources[0x0c]	1378176	1			T2	9337		T3	9422		T7	307
valid_sources[0x0d]	2878918	1			T2	8205		T3	9540		T7	773
valid_sources[0x0e]	1383962	1			T2	9308		T3	9275		T7	309
valid_sources[0x0f]	1381909	1			T2	9037		T3	9362		T7	382
valid_sources[0x10]	1589313	1			T2	9505		T3	9173		T7	296
valid_sources[0x11]	1382551	1			T2	9274		T3	9266		T7	1291
valid_sources[0x12]	1377810	1			T2	9394		T3	9064		T7	437
valid_sources[0x13]	3343927	1			T2	9211		T3	9223		T7	303
valid_sources[0x14]	1381912	1			T2	9757		T3	9098		T7	784
valid_sources[0x15]	1775654	1			T2	9141		T3	9212		T7	394656
valid_sources[0x16]	1381762	1			T2	9436		T3	9342		T7	349
valid_sources[0x17]	1383516	1			T2	9311		T3	9251		T7	316
valid_sources[0x18]	1377312	1			T2	8766		T3	9035		T7	257
valid_sources[0x19]	1484639	1			T2	9423		T3	9336		T7	1002
valid_sources[0x1a]	1853490	1			T2	10427		T3	9169		T7	323
valid_sources[0x1b]	1391684	1			T2	9328		T3	9261		T7	253
valid_sources[0x1c]	1381097	1			T2	8904		T3	9247		T7	252
valid_sources[0x1d]	3772282	1			T2	9836		T3	9285		T7	911
valid_sources[0x1e]	1606932	1			T2	9487		T3	9126		T7	270
valid_sources[0x1f]	1386201	1			T2	9206		T3	9160		T7	282
valid_sources[0x20]	1370851	1			T2	9159		T3	9241		T7	460
valid_sources[0x21]	3146531	1			T2	9328		T3	9312		T7	278
valid_sources[0x22]	3387281	1			T2	9413		T3	9191		T7	385
valid_sources[0x23]	2015688	1			T2	9517		T3	9196		T7	348
valid_sources[0x24]	1956850	1			T2	9324		T3	9122		T7	367
valid_sources[0x25]	2042068	1			T2	9343		T3	9316		T7	355
valid_sources[0x26]	1373552	1			T2	8758		T3	9337		T7	278
valid_sources[0x27]	1380608	1			T2	9683		T3	9202		T7	289
valid_sources[0x28]	2411307	1			T2	9198		T3	9352		T7	251
valid_sources[0x29]	1439698	1			T2	9272		T3	9183		T7	359
valid_sources[0x2a]	1833790	1			T2	8939		T3	9143		T7	323
valid_sources[0x2b]	1381074	1			T2	9315		T3	9460		T7	360
valid_sources[0x2c]	1378478	1			T2	8857		T3	9198		T7	282
valid_sources[0x2d]	2275335	1			T2	9013		T3	9192		T7	310
valid_sources[0x2e]	1380160	1			T2	8649		T3	9358		T7	320
valid_sources[0x2f]	1389372	1			T2	8663		T3	9237		T7	252
valid_sources[0x30]	1381394	1			T2	9462		T3	9185		T7	375
valid_sources[0x31]	1383024	1			T2	8704		T3	9193		T7	322
valid_sources[0x32]	1401585	1			T2	9358		T3	9449		T7	297
valid_sources[0x33]	1552538	1			T2	9088		T3	9213		T7	697
valid_sources[0x34]	1384637	1			T2	9368		T3	9283		T7	250
valid_sources[0x35]	1383207	1			T2	9632		T3	9279		T7	313
valid_sources[0x36]	1378272	1			T2	9063		T3	9244		T7	826
valid_sources[0x37]	1844063	1			T2	9154		T3	9333		T7	244
valid_sources[0x38]	2059126	1			T2	9542		T3	9370		T7	299
valid_sources[0x39]	1374814	1			T2	9242		T3	9206		T7	278
valid_sources[0x3a]	3755239	1			T2	8845		T3	9239		T7	273
valid_sources[0x3b]	2047309	1			T2	8970		T3	9513		T7	928
valid_sources[0x3c]	1374335	1			T2	9768		T3	9182		T7	289
valid_sources[0x3d]	1438067	1			T2	9069		T3	9249		T7	287
valid_sources[0x3e]	1446982	1			T2	9204		T3	9013		T7	320
valid_sources[0x3f]	1379001	1			T2	9851		T3	9342		T7	290
valid_sources[0x40]	1543614	1			T2	9417		T3	9224		T7	314
valid_sources[0x41]	1973859	1			T2	10542		T3	9269		T7	341
valid_sources[0x42]	1380224	1			T2	9875		T3	9295		T7	336
valid_sources[0x43]	1433509	1			T2	9762		T3	9203		T7	281
valid_sources[0x44]	1630764	1			T2	8706		T3	9394		T7	281
valid_sources[0x45]	2983614	1			T2	9084		T3	9305		T7	275
valid_sources[0x46]	1383008	1			T2	8919		T3	9308		T7	311
valid_sources[0x47]	1369555	1			T2	9410		T3	9065		T7	263
valid_sources[0x48]	1383674	1			T2	8975		T3	9407		T7	338
valid_sources[0x49]	1386973	1			T2	8887		T3	9296		T7	333
valid_sources[0x4a]	3364909	1			T2	9413		T3	9129		T7	261
valid_sources[0x4b]	1388481	1			T2	9748		T3	9230		T7	290
valid_sources[0x4c]	1386961	1			T2	9163		T3	9098		T7	340
valid_sources[0x4d]	1376971	1			T2	9020		T3	9319		T7	356
valid_sources[0x4e]	3326378	1			T2	9130		T3	9020		T7	251
valid_sources[0x4f]	1385215	1			T2	9092		T3	9120		T7	279
valid_sources[0x50]	3826039	1			T2	9909		T3	9172		T7	347
valid_sources[0x51]	1374177	1			T2	9228		T3	9201		T7	301
valid_sources[0x52]	1842490	1			T2	8711		T3	9255		T7	299
valid_sources[0x53]	1378382	1			T2	8803		T3	9064		T7	336
valid_sources[0x54]	1389470	1			T2	9092		T3	9276		T7	1239
valid_sources[0x55]	1430252	1			T2	8708		T3	9254		T7	260
valid_sources[0x56]	1379057	1			T2	9731		T3	9281		T7	393
valid_sources[0x57]	2526088	1			T2	9056		T3	9127		T7	311
valid_sources[0x58]	1564727	1			T2	9114		T3	9111		T7	287
valid_sources[0x59]	1381514	1			T2	9275		T3	9176		T7	293
valid_sources[0x5a]	1386002	1			T2	9567		T3	9224		T7	355
valid_sources[0x5b]	1454272	1			T2	9596		T3	9330		T7	801
valid_sources[0x5c]	2700913	1			T2	9674		T3	9145		T7	918
valid_sources[0x5d]	2283274	1			T2	9035		T3	9097		T7	378
valid_sources[0x5e]	1388449	1			T2	8626		T3	9105		T7	381
valid_sources[0x5f]	2291469	1			T2	9472		T3	9217		T7	370
valid_sources[0x60]	1827180	1			T2	8154		T3	9193		T7	315
valid_sources[0x61]	1384148	1			T2	8404		T3	9334		T7	305
valid_sources[0x62]	1376980	1			T2	9200		T3	9135		T7	339
valid_sources[0x63]	1375198	1			T2	8821		T3	9197		T7	365
valid_sources[0x64]	1373976	1			T2	8855		T3	9217		T7	345
valid_sources[0x65]	2266817	1			T2	8638		T3	9175		T7	368
valid_sources[0x66]	1616660	1			T2	8649		T3	9104		T7	954
valid_sources[0x67]	1521847	1			T2	9117		T3	9143		T7	305
valid_sources[0x68]	3327039	1			T2	9078		T3	9190		T7	921
valid_sources[0x69]	1387343	1			T2	9426		T3	9327		T7	315
valid_sources[0x6a]	1378042	1			T2	9310		T3	9114		T7	343
valid_sources[0x6b]	3027506	1			T2	9474		T3	9155		T7	320
valid_sources[0x6c]	1384580	1			T2	8736		T3	9050		T7	332
valid_sources[0x6d]	3646612	1			T2	10020		T3	9186		T7	365
valid_sources[0x6e]	1493066	1			T2	8409		T3	9182		T7	301
valid_sources[0x6f]	1382941	1			T2	8340		T3	9312		T7	363
valid_sources[0x70]	2028601	1			T2	9368		T3	9190		T7	298
valid_sources[0x71]	1378785	1			T2	9079		T3	9100		T7	277
valid_sources[0x72]	1373746	1			T2	9184		T3	9141		T7	325
valid_sources[0x73]	1482551	1			T2	10203		T3	9080		T7	290
valid_sources[0x74]	2248638	1			T2	9877		T3	9204		T7	234
valid_sources[0x75]	1379708	1			T2	9629		T3	9133		T7	265
valid_sources[0x76]	1511471	1			T2	9103		T3	9173		T7	325
valid_sources[0x77]	1375362	1			T2	8944		T3	9193		T7	295
valid_sources[0x78]	1383043	1			T2	9765		T3	9127		T7	317
valid_sources[0x79]	1444172	1			T2	10109		T3	9307		T7	297
valid_sources[0x7a]	2303683	1			T2	10070		T3	9071		T7	297
valid_sources[0x7b]	1451026	1			T2	8759		T3	9318		T7	302
valid_sources[0x7c]	1418875	1			T2	9638		T3	9369		T7	271
valid_sources[0x7d]	1859157	1			T2	9529		T3	9361		T7	293
valid_sources[0x7e]	1538483	1			T2	9225		T3	9162		T7	378
valid_sources[0x7f]	2299803	1			T2	9267		T3	9157		T7	1032
valid_sources[0x80]	1375390	1			T2	9227		T3	9172		T7	356

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

71261537

1

T1

336362

T2

338199

T3

339962

values[0x0]

all_enables

biggest_size

60485567

1

T1

319075

T2

318956

T3

309682

values[0x1]

all_enables

biggest_size

52058873

1

T1

272185

T2

270655

T3

261244