Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

259167390

1

T1

141477

T2

142849

T3

144999

full_word

183839022

1

T1

927622

T2

927810

T3

910888

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	443006142	1			T1	234239		T2	235630		T3	236088
auto[TlIntgErrCmd]	100	1			T111	7		T126	5		T127	5
auto[TlIntgErrData]	81	1			T111	9		T126	3		T127	3
auto[TlIntgErrBoth]	89	1			T111	4		T126	2		T127	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

229627577

1

T1

118130

T2

118826

T3

119756

auto[1]

213378835

1

T1

116108

T2

116803

T3

116331

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	158357643	1			T1	844947		T2	850070		T3	857601
auto[TlIntgErrNone]	partial	auto[1]	100809500	1			T1	569828		T2	578422		T3	592391
auto[TlIntgErrNone]	full_word	auto[0]	71269820	1			T1	336362		T2	338199		T3	339962
auto[TlIntgErrNone]	full_word	auto[1]	112569179	1			T1	591260		T2	589611		T3	570926
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T111	6		T127	2		T139	1
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T126	5		T127	2		T139	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T111	1		T147	1		T148	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T127	1		T182	1		-	-
auto[TlIntgErrData]	partial	auto[0]	31	1			T111	6		T126	1		T127	2
auto[TlIntgErrData]	partial	auto[1]	42	1			T111	3		T126	2		T127	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T183	1		T180	1		T182	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T183	1		T184	1		T181	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1			T111	1		T147	2		T148	3
auto[TlIntgErrBoth]	partial	auto[1]	48	1			T111	2		T126	2		T127	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T111	1		T147	1		T182	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T180	2		T182	1		T185	1