Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	119918	0	0
entropy_period_rd_A	2147483647	1196	0	0
intr_enable_rd_A	2147483647	1791	0	0
prefix_0_rd_A	2147483647	1430	0	0
prefix_10_rd_A	2147483647	1238	0	0
prefix_1_rd_A	2147483647	1372	0	0
prefix_2_rd_A	2147483647	1419	0	0
prefix_3_rd_A	2147483647	1303	0	0
prefix_4_rd_A	2147483647	1435	0	0
prefix_5_rd_A	2147483647	1387	0	0
prefix_6_rd_A	2147483647	1415	0	0
prefix_7_rd_A	2147483647	1304	0	0
prefix_8_rd_A	2147483647	1265	0	0
prefix_9_rd_A	2147483647	1486	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	119918	0	0
T17	582405	80138	0	0
T59	795265	0	0	0
T70	0	37214	0	0
T91	475431	0	0	0
T111	0	1	0	0
T125	0	144	0	0
T127	0	3	0	0
T133	0	120	0	0
T134	0	15	0	0
T135	0	10	0	0
T138	0	4	0	0
T139	0	2	0	0
T140	15580	0	0	0
T141	146126	0	0	0
T142	190550	0	0	0
T143	216388	0	0	0
T144	917858	0	0	0
T145	364517	0	0	0
T146	646920	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1196	0	0
T81	4744	22	0	0
T87	3890	6	0	0
T89	11888	68	0	0
T126	12555	48	0	0
T127	12135	45	0	0
T157	3009	2	0	0
T158	11019	68	0	0
T159	2130	13	0	0
T160	1704	8	0	0
T161	3617	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1791	0	0
T81	4744	32	0	0
T87	3890	9	0	0
T89	11888	72	0	0
T126	12555	95	0	0
T127	12135	64	0	0
T158	11019	25	0	0
T159	2130	5	0	0
T160	1704	11	0	0
T162	1263	14	0	0
T163	1495	18	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1430	0	0
T81	4744	22	0	0
T87	3890	5	0	0
T89	11888	57	0	0
T126	12555	27	0	0
T127	12135	51	0	0
T157	3009	5	0	0
T158	11019	67	0	0
T160	1704	1	0	0
T161	3617	3	0	0
T164	26746	214	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1238	0	0
T81	4744	21	0	0
T87	3890	8	0	0
T89	11888	42	0	0
T126	12555	40	0	0
T127	12135	47	0	0
T158	11019	33	0	0
T159	2130	2	0	0
T160	1704	2	0	0
T161	3617	3	0	0
T164	26746	199	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1372	0	0
T81	4744	36	0	0
T87	3890	14	0	0
T89	11888	51	0	0
T126	12555	40	0	0
T127	12135	45	0	0
T157	3009	10	0	0
T158	11019	49	0	0
T159	2130	3	0	0
T160	1704	4	0	0
T161	3617	1	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1419	0	0
T81	4744	16	0	0
T87	3890	2	0	0
T89	11888	49	0	0
T126	12555	46	0	0
T127	12135	40	0	0
T157	3009	12	0	0
T158	11019	48	0	0
T160	1704	5	0	0
T161	3617	9	0	0
T164	26746	225	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1303	0	0
T81	4744	15	0	0
T87	3890	7	0	0
T89	11888	50	0	0
T126	12555	50	0	0
T127	12135	52	0	0
T158	11019	51	0	0
T160	1704	9	0	0
T161	3617	4	0	0
T164	26746	153	0	0
T165	12627	35	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1435	0	0
T81	4744	12	0	0
T87	3890	15	0	0
T89	11888	69	0	0
T126	12555	39	0	0
T127	12135	40	0	0
T157	3009	9	0	0
T158	11019	61	0	0
T159	2130	9	0	0
T160	1704	4	0	0
T164	26746	201	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1387	0	0
T81	4744	24	0	0
T87	3890	7	0	0
T89	11888	60	0	0
T126	12555	35	0	0
T127	12135	53	0	0
T157	3009	1	0	0
T158	11019	23	0	0
T159	2130	9	0	0
T160	1704	10	0	0
T161	3617	8	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1415	0	0
T81	4744	17	0	0
T87	3890	9	0	0
T89	11888	76	0	0
T126	12555	37	0	0
T127	12135	35	0	0
T158	11019	52	0	0
T159	2130	4	0	0
T160	1704	3	0	0
T161	3617	12	0	0
T164	26746	203	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1304	0	0
T81	4744	27	0	0
T87	3890	16	0	0
T89	11888	76	0	0
T126	12555	42	0	0
T127	12135	29	0	0
T157	3009	11	0	0
T158	11019	38	0	0
T159	2130	4	0	0
T160	1704	1	0	0
T161	3617	1	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1265	0	0
T81	4744	21	0	0
T87	3890	9	0	0
T89	11888	52	0	0
T126	12555	34	0	0
T127	12135	25	0	0
T157	3009	4	0	0
T158	11019	36	0	0
T159	2130	3	0	0
T160	1704	7	0	0
T161	3617	3	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1486	0	0
T81	4744	26	0	0
T87	3890	9	0	0
T89	11888	65	0	0
T126	12555	32	0	0
T127	12135	60	0	0
T157	3009	1	0	0
T158	11019	20	0	0
T159	2130	9	0	0
T160	1704	3	0	0
T161	3617	3	0	0