Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
171581 |
1 |
|
|
T3 |
836 |
|
T7 |
168 |
|
T8 |
342 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
87161 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
63669 |
1 |
|
|
T3 |
29 |
|
T7 |
164 |
|
T8 |
336 |
seven_bytes |
3059 |
1 |
|
|
T3 |
23 |
|
T15 |
12 |
|
T18 |
23 |
six_bytes |
2877 |
1 |
|
|
T3 |
30 |
|
T15 |
22 |
|
T18 |
20 |
five_bytes |
3052 |
1 |
|
|
T3 |
17 |
|
T15 |
12 |
|
T18 |
26 |
four_bytes |
2934 |
1 |
|
|
T3 |
23 |
|
T15 |
9 |
|
T18 |
15 |
three_bytes |
2965 |
1 |
|
|
T3 |
27 |
|
T15 |
13 |
|
T18 |
23 |
two_bytes |
2930 |
1 |
|
|
T3 |
18 |
|
T15 |
8 |
|
T18 |
20 |
one_byte |
2934 |
1 |
|
|
T3 |
18 |
|
T15 |
10 |
|
T18 |
16 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
168183 |
1 |
|
|
T3 |
824 |
|
T7 |
160 |
|
T8 |
330 |
auto[1] |
3398 |
1 |
|
|
T3 |
12 |
|
T7 |
8 |
|
T8 |
12 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
171581 |
1 |
|
|
T3 |
836 |
|
T7 |
168 |
|
T8 |
342 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
171568 |
1 |
|
|
T3 |
836 |
|
T7 |
168 |
|
T8 |
342 |
auto[1] |
13 |
1 |
|
|
T38 |
1 |
|
T9 |
2 |
|
T61 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1177 |
1 |
|
|
T3 |
2 |
|
T7 |
4 |
|
T8 |
6 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3398 |
1 |
|
|
T3 |
12 |
|
T7 |
8 |
|
T8 |
12 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
174251 |
1 |
|
|
T3 |
1389 |
|
T7 |
396 |
|
T8 |
350 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
91306 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
60923 |
1 |
|
|
T3 |
35 |
|
T7 |
387 |
|
T8 |
344 |
seven_bytes |
3233 |
1 |
|
|
T3 |
35 |
|
T15 |
24 |
|
T18 |
25 |
six_bytes |
3120 |
1 |
|
|
T3 |
44 |
|
T15 |
18 |
|
T18 |
23 |
five_bytes |
3207 |
1 |
|
|
T3 |
41 |
|
T15 |
10 |
|
T18 |
36 |
four_bytes |
3127 |
1 |
|
|
T3 |
40 |
|
T15 |
16 |
|
T18 |
21 |
three_bytes |
3205 |
1 |
|
|
T3 |
37 |
|
T15 |
25 |
|
T18 |
15 |
two_bytes |
3063 |
1 |
|
|
T3 |
38 |
|
T15 |
19 |
|
T18 |
21 |
one_byte |
3067 |
1 |
|
|
T3 |
49 |
|
T15 |
13 |
|
T18 |
26 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170899 |
1 |
|
|
T3 |
1373 |
|
T7 |
378 |
|
T8 |
338 |
auto[1] |
3352 |
1 |
|
|
T3 |
16 |
|
T7 |
18 |
|
T8 |
12 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
174251 |
1 |
|
|
T3 |
1389 |
|
T7 |
396 |
|
T8 |
350 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
174241 |
1 |
|
|
T3 |
1389 |
|
T7 |
396 |
|
T8 |
350 |
auto[1] |
10 |
1 |
|
|
T57 |
1 |
|
T60 |
1 |
|
T188 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1179 |
1 |
|
|
T3 |
1 |
|
T7 |
9 |
|
T8 |
6 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3352 |
1 |
|
|
T3 |
16 |
|
T7 |
18 |
|
T8 |
12 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
344919 |
1 |
|
|
T3 |
1055 |
|
T7 |
1456 |
|
T8 |
767 |
auto[1] |
481 |
1 |
|
|
T4 |
30 |
|
T9 |
92 |
|
T10 |
47 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
177302 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
126295 |
1 |
|
|
T3 |
28 |
|
T7 |
1435 |
|
T8 |
757 |
seven_bytes |
5954 |
1 |
|
|
T3 |
24 |
|
T15 |
39 |
|
T18 |
26 |
six_bytes |
5852 |
1 |
|
|
T3 |
24 |
|
T15 |
29 |
|
T18 |
32 |
five_bytes |
5983 |
1 |
|
|
T3 |
25 |
|
T15 |
42 |
|
T18 |
21 |
four_bytes |
6029 |
1 |
|
|
T3 |
22 |
|
T15 |
39 |
|
T18 |
22 |
three_bytes |
6048 |
1 |
|
|
T3 |
30 |
|
T15 |
29 |
|
T18 |
27 |
two_bytes |
5933 |
1 |
|
|
T3 |
32 |
|
T15 |
42 |
|
T18 |
23 |
one_byte |
6004 |
1 |
|
|
T3 |
32 |
|
T15 |
32 |
|
T18 |
16 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
338745 |
1 |
|
|
T3 |
1043 |
|
T7 |
1414 |
|
T8 |
747 |
auto[1] |
6655 |
1 |
|
|
T3 |
12 |
|
T7 |
42 |
|
T8 |
20 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
345400 |
1 |
|
|
T3 |
1055 |
|
T7 |
1456 |
|
T8 |
767 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
345370 |
1 |
|
|
T3 |
1055 |
|
T7 |
1456 |
|
T8 |
767 |
auto[1] |
30 |
1 |
|
|
T4 |
1 |
|
T189 |
1 |
|
T72 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2340 |
1 |
|
|
T3 |
3 |
|
T7 |
21 |
|
T8 |
10 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6655 |
1 |
|
|
T3 |
12 |
|
T7 |
42 |
|
T8 |
20 |