Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

259565411

1

T1

4473

T2

30220

T3

11074

full_word

184470620

1

T1

21503

T2

160715

T3

21856

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	444035751	1			T1	25976		T2	190935		T3	32930
auto[TlIntgErrCmd]	92	1			T139	4		T140	6		T141	4
auto[TlIntgErrData]	100	1			T139	1		T140	8		T141	3
auto[TlIntgErrBoth]	88	1			T139	5		T140	6		T141	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

229803863

1

T1

14993

T2

60989

T3

21839

auto[1]

214232168

1

T1

10983

T2

129946

T3

11091

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	158305436	1			T1	2580		T2	28380		T3	7089
auto[TlIntgErrNone]	partial	auto[1]	101259720	1			T1	1893		T2	1840		T3	3985
auto[TlIntgErrNone]	full_word	auto[0]	71498299	1			T1	12413		T2	32609		T3	14750
auto[TlIntgErrNone]	full_word	auto[1]	112972296	1			T1	9090		T2	128106		T3	7106
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T139	3		T140	3		T141	2
auto[TlIntgErrCmd]	partial	auto[1]	42	1			T139	1		T140	3		T141	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T178	1		T193	1		T194	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T141	1		T195	1		-	-
auto[TlIntgErrData]	partial	auto[0]	41	1			T140	3		T141	2		T190	2
auto[TlIntgErrData]	partial	auto[1]	47	1			T139	1		T140	2		T190	8
auto[TlIntgErrData]	full_word	auto[0]	5	1			T140	2		T141	1		T196	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T140	1		T190	1		T191	1
auto[TlIntgErrBoth]	partial	auto[0]	32	1			T139	3		T140	3		T141	2
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T139	2		T140	3		T141	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T197	1		T196	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T190	1		T178	1		T195	1