Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	130512	0	0
entropy_period_rd_A	2147483647	938	0	0
intr_enable_rd_A	2147483647	959	0	0
prefix_0_rd_A	2147483647	664	0	0
prefix_10_rd_A	2147483647	649	0	0
prefix_1_rd_A	2147483647	556	0	0
prefix_2_rd_A	2147483647	554	0	0
prefix_3_rd_A	2147483647	646	0	0
prefix_4_rd_A	2147483647	763	0	0
prefix_5_rd_A	2147483647	632	0	0
prefix_6_rd_A	2147483647	756	0	0
prefix_7_rd_A	2147483647	655	0	0
prefix_8_rd_A	2147483647	677	0	0
prefix_9_rd_A	2147483647	602	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	130512	0	0
T50	941285	10514	0	0
T56	0	117170	0	0
T121	0	80	0	0
T139	0	1	0	0
T140	0	3	0	0
T141	0	1	0	0
T142	0	30	0	0
T143	0	325	0	0
T147	0	189	0	0
T148	0	213	0	0
T150	608810	0	0	0
T151	63892	0	0	0
T152	182394	0	0	0
T153	197414	0	0	0
T154	23048	0	0	0
T155	65079	0	0	0
T156	346759	0	0	0
T157	23559	0	0	0
T158	147644	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	938	0	0
T102	7619	52	0	0
T140	22346	132	0	0
T159	4267	10	0	0
T167	6046	45	0	0
T168	9622	17	0	0
T169	3000	26	0	0
T170	5231	12	0	0
T171	5333	6	0	0
T172	1589	17	0	0
T173	2989	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	959	0	0
T140	22346	145	0	0
T159	4267	2	0	0
T167	6046	21	0	0
T168	9622	8	0	0
T169	3000	30	0	0
T170	5231	11	0	0
T171	5333	1	0	0
T174	1564	16	0	0
T175	2008	1	0	0
T176	1744	14	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	664	0	0
T102	7619	25	0	0
T140	22346	89	0	0
T167	6046	33	0	0
T168	9622	33	0	0
T169	3000	3	0	0
T171	5333	17	0	0
T172	1589	4	0	0
T173	2989	10	0	0
T175	2008	7	0	0
T177	5822	20	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	649	0	0
T102	7619	18	0	0
T140	22346	66	0	0
T147	11893	7	0	0
T159	4267	8	0	0
T167	6046	27	0	0
T168	9622	23	0	0
T169	3000	4	0	0
T170	5231	22	0	0
T171	5333	14	0	0
T172	1589	1	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	556	0	0
T102	7619	38	0	0
T140	22346	75	0	0
T159	4267	7	0	0
T167	6046	18	0	0
T168	9622	19	0	0
T169	3000	15	0	0
T170	5231	13	0	0
T171	5333	2	0	0
T172	1589	2	0	0
T175	2008	5	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	554	0	0
T102	7619	34	0	0
T140	22346	72	0	0
T167	6046	1	0	0
T168	9622	14	0	0
T169	3000	8	0	0
T170	5231	2	0	0
T171	5333	13	0	0
T173	2989	13	0	0
T177	5822	4	0	0
T178	35356	56	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	646	0	0
T102	7619	15	0	0
T140	22346	59	0	0
T167	6046	14	0	0
T168	9622	37	0	0
T169	3000	18	0	0
T170	5231	9	0	0
T171	5333	8	0	0
T172	1589	3	0	0
T173	2989	8	0	0
T175	2008	8	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	763	0	0
T102	7619	41	0	0
T140	22346	87	0	0
T159	4267	11	0	0
T167	6046	35	0	0
T168	9622	45	0	0
T169	3000	17	0	0
T170	5231	9	0	0
T171	5333	29	0	0
T172	1589	3	0	0
T173	2989	4	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	632	0	0
T102	7619	38	0	0
T140	22346	66	0	0
T159	4267	8	0	0
T167	6046	48	0	0
T168	9622	14	0	0
T169	3000	9	0	0
T171	5333	4	0	0
T173	2989	7	0	0
T175	2008	1	0	0
T177	5822	11	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	756	0	0
T102	7619	24	0	0
T140	22346	95	0	0
T159	4267	12	0	0
T167	6046	34	0	0
T168	9622	38	0	0
T169	3000	12	0	0
T170	5231	3	0	0
T171	5333	24	0	0
T172	1589	7	0	0
T175	2008	1	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	655	0	0
T102	7619	35	0	0
T140	22346	60	0	0
T159	4267	6	0	0
T167	6046	34	0	0
T168	9622	14	0	0
T169	3000	4	0	0
T170	5231	7	0	0
T171	5333	7	0	0
T172	1589	1	0	0
T175	2008	1	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	677	0	0
T102	7619	28	0	0
T140	22346	81	0	0
T159	4267	1	0	0
T167	6046	27	0	0
T168	9622	15	0	0
T169	3000	3	0	0
T170	5231	17	0	0
T171	5333	16	0	0
T172	1589	8	0	0
T175	2008	4	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	602	0	0
T102	7619	27	0	0
T140	22346	68	0	0
T167	6046	12	0	0
T168	9622	25	0	0
T169	3000	11	0	0
T170	5231	9	0	0
T171	5333	21	0	0
T173	2989	16	0	0
T177	5822	16	0	0
T178	35356	83	0	0