SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
push_pull_agent_pkg.uvm_test_top.env.m_kmac_app_agent[0].m_data_push_agent.cov::m_valid_ready_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
push_pull_agent_pkg.uvm_test_top.env.m_kmac_app_agent[1].m_data_push_agent.cov::m_valid_ready_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
push_pull_agent_pkg.uvm_test_top.env.m_kmac_app_agent[2].m_data_push_agent.cov::m_valid_ready_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 4 | 0 | 4 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_valid_ready | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 4 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 4 | 0 | 4 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_valid_ready | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 4 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 4 | 0 | 4 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_valid_ready | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 49484 | 1 | T1 | 27 | T3 | 1 | T7 | 13 | ||||
auto[1] | 16833 | 1 | T1 | 27 | T3 | 1 | T7 | 13 | ||||
auto[2] | 289141 | 1 | T1 | 1762 | T3 | 46 | T7 | 693 | ||||
auto[3] | 305318 | 1 | T1 | 1789 | T3 | 47 | T7 | 706 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 27909 | 1 | T1 | 11 | T3 | 2 | T7 | 4 | ||||
auto[1] | 8182 | 1 | T1 | 11 | T3 | 2 | T7 | 4 | ||||
auto[2] | 143147 | 1 | T1 | 710 | T3 | 101 | T7 | 277 | ||||
auto[3] | 150495 | 1 | T1 | 721 | T3 | 103 | T7 | 281 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 23987 | 1 | T1 | 17 | T7 | 2 | T20 | 446 | ||||
auto[1] | 7789 | 1 | T1 | 17 | T7 | 9 | T20 | 10 | ||||
auto[2] | 127983 | 1 | T1 | 855 | T20 | 1434 | T21 | 1142 | ||||
auto[3] | 134891 | 1 | T1 | 872 | T7 | 9 | T20 | 1450 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |