Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

257183710

1

T1

61989

T2

44717

T3

6976

full_word

182397314

1

T1

70687

T2

45065

T3

7104

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	439580714	1			T1	132676		T2	89782		T3	14080
auto[TlIntgErrCmd]	91	1			T133	9		T134	5		T135	7
auto[TlIntgErrData]	111	1			T133	6		T134	8		T135	5
auto[TlIntgErrBoth]	108	1			T133	5		T134	7		T135	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

227939791

1

T1

94379

T2

53663

T3

9702

auto[1]

211641233

1

T1

38297

T2

36119

T3

4378

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	157412495	1			T1	45126		T2	44100		T3	5018
auto[TlIntgErrNone]	partial	auto[1]	99770939	1			T1	16863		T2	617		T3	1958
auto[TlIntgErrNone]	full_word	auto[0]	70527163	1			T1	49253		T2	9563		T3	4684
auto[TlIntgErrNone]	full_word	auto[1]	111870117	1			T1	21434		T2	35502		T3	2420
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T133	4		T134	1		T162	2
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T133	5		T134	3		T135	7
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T186	1		T187	1		T188	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T134	1		T185	1		T189	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T133	5		T134	4		T135	2
auto[TlIntgErrData]	partial	auto[1]	54	1			T133	1		T134	4		T135	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T135	1		T190	1		T191	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T165	3		T186	1		T190	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T133	3		T134	3		T135	4
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T133	2		T134	3		T135	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T186	1		T190	1		T192	1
auto[TlIntgErrBoth]	full_word	auto[1]	12	1			T134	1		T162	1		T185	1