Unified Coverage Report :: Module :: prim_mubi4_sender

Module : prim_mubi4_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3_done_sender	100.00	100.00				100.00	100.00
tb.dut.gen_entropy.u_entropy.u_entropy_configured	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_sha3_done_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_entropy.u_entropy.u_entropy_configured

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.57	100.00	87.83		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

Line Coverage for Module : prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Module : prim_mubi4_sender

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1031086	1030940	0	0
T2	414300	414140	0	0
T3	86766	86606	0	0
T7	322098	321964	0	0
T11	4616	4318	0	0
T20	919306	919126	0	0
T36	723512	723380	0	0
T37	1964268	1964252	0	0
T38	1243852	1243832	0	0
T39	24622	24502	0	0

Line Coverage for Instance : tb.dut.u_sha3_done_sender

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.u_sha3_done_sender

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sha3_done_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	515543	515470	0	0
T2	207150	207070	0	0
T3	43383	43303	0	0
T7	161049	160982	0	0
T11	2308	2159	0	0
T20	459653	459563	0	0
T36	361756	361690	0	0
T37	982134	982126	0	0
T38	621926	621916	0	0
T39	12311	12251	0	0

Line Coverage for Instance : tb.dut.gen_entropy.u_entropy.u_entropy_configured

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_entropy.u_entropy.u_entropy_configured

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_entropy.u_entropy.u_entropy_configured

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	515543	515470	0	0
T2	207150	207070	0	0
T3	43383	43303	0	0
T7	161049	160982	0	0
T11	2308	2159	0	0
T20	459653	459563	0	0
T36	361756	361690	0	0
T37	982134	982126	0	0
T38	621926	621916	0	0
T39	12311	12251	0	0