Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	114439	0	0
entropy_period_rd_A	2147483647	1466	0	0
intr_enable_rd_A	2147483647	2326	0	0
prefix_0_rd_A	2147483647	1742	0	0
prefix_10_rd_A	2147483647	1719	0	0
prefix_1_rd_A	2147483647	1792	0	0
prefix_2_rd_A	2147483647	1803	0	0
prefix_3_rd_A	2147483647	1860	0	0
prefix_4_rd_A	2147483647	1756	0	0
prefix_5_rd_A	2147483647	1797	0	0
prefix_6_rd_A	2147483647	1830	0	0
prefix_7_rd_A	2147483647	1870	0	0
prefix_8_rd_A	2147483647	1819	0	0
prefix_9_rd_A	2147483647	1743	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	114439	0	0
T6	3506	0	0	0
T15	726827	11407	0	0
T19	715491	0	0	0
T57	0	33420	0	0
T74	0	40318	0	0
T75	593404	0	0	0
T108	443317	0	0	0
T133	0	3	0	0
T139	0	25982	0	0
T140	0	171	0	0
T141	0	2	0	0
T142	0	2	0	0
T143	0	4	0	0
T144	0	3	0	0
T146	12167	0	0	0
T147	176939	0	0	0
T148	10932	0	0	0
T149	141844	0	0	0
T150	481104	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1466	0	0
T98	11975	57	0	0
T141	8548	28	0	0
T143	4628	9	0	0
T161	10557	26	0	0
T162	47837	95	0	0
T163	10401	43	0	0
T164	1839	4	0	0
T165	23661	119	0	0
T166	3577	9	0	0
T167	6982	44	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2326	0	0
T98	11975	88	0	0
T136	1577	8	0	0
T141	8548	17	0	0
T143	4628	10	0	0
T161	10557	56	0	0
T162	47837	127	0	0
T163	10401	50	0	0
T168	984	11	0	0
T169	1187	12	0	0
T170	1038	30	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1742	0	0
T98	11975	56	0	0
T141	8548	12	0	0
T143	4628	4	0	0
T161	10557	41	0	0
T162	47837	60	0	0
T163	10401	25	0	0
T165	23661	79	0	0
T166	3577	16	0	0
T167	6982	7	0	0
T171	1635	5	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1719	0	0
T98	11975	44	0	0
T141	8548	10	0	0
T143	4628	6	0	0
T161	10557	73	0	0
T162	47837	68	0	0
T163	10401	15	0	0
T165	23661	80	0	0
T166	3577	14	0	0
T167	6982	7	0	0
T171	1635	6	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1792	0	0
T98	11975	52	0	0
T141	8548	25	0	0
T143	4628	15	0	0
T161	10557	17	0	0
T162	47837	59	0	0
T163	10401	46	0	0
T164	1839	4	0	0
T165	23661	76	0	0
T166	3577	10	0	0
T167	6982	16	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1803	0	0
T98	11975	64	0	0
T141	8548	31	0	0
T143	4628	6	0	0
T161	10557	30	0	0
T162	47837	76	0	0
T163	10401	29	0	0
T164	1839	7	0	0
T165	23661	79	0	0
T166	3577	12	0	0
T167	6982	31	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1860	0	0
T98	11975	54	0	0
T141	8548	9	0	0
T143	4628	5	0	0
T161	10557	40	0	0
T162	47837	76	0	0
T163	10401	46	0	0
T164	1839	3	0	0
T165	23661	69	0	0
T166	3577	17	0	0
T167	6982	1	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1756	0	0
T98	11975	56	0	0
T141	8548	20	0	0
T143	4628	7	0	0
T161	10557	43	0	0
T162	47837	83	0	0
T163	10401	39	0	0
T164	1839	3	0	0
T165	23661	60	0	0
T166	3577	5	0	0
T167	6982	19	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1797	0	0
T98	11975	50	0	0
T141	8548	12	0	0
T143	4628	6	0	0
T161	10557	33	0	0
T162	47837	96	0	0
T163	10401	62	0	0
T165	23661	90	0	0
T166	3577	9	0	0
T167	6982	35	0	0
T172	5334	7	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1830	0	0
T98	11975	58	0	0
T141	8548	21	0	0
T143	4628	8	0	0
T161	10557	43	0	0
T162	47837	76	0	0
T163	10401	24	0	0
T164	1839	9	0	0
T165	23661	55	0	0
T166	3577	6	0	0
T167	6982	19	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1870	0	0
T98	11975	58	0	0
T141	8548	17	0	0
T143	4628	1	0	0
T161	10557	71	0	0
T162	47837	101	0	0
T163	10401	78	0	0
T165	23661	93	0	0
T166	3577	7	0	0
T167	6982	24	0	0
T171	1635	9	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1819	0	0
T98	11975	45	0	0
T141	8548	21	0	0
T143	4628	8	0	0
T161	10557	37	0	0
T162	47837	62	0	0
T163	10401	31	0	0
T165	23661	72	0	0
T166	3577	1	0	0
T167	6982	32	0	0
T171	1635	5	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1743	0	0
T98	11975	51	0	0
T141	8548	9	0	0
T143	4628	9	0	0
T161	10557	45	0	0
T162	47837	55	0	0
T163	10401	43	0	0
T164	1839	7	0	0
T165	23661	80	0	0
T166	3577	13	0	0
T167	6982	17	0	0