Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 260510481 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 184959201 1 T1 79627 T2 1088 T3 326363



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 230748948 1 T1 89619 T2 1236 T3 426047
values[0x0] 103208206 1 T1 21111 T2 567 T3 204503
values[0x1] 111512528 1 T1 22843 T2 543 T3 221036



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 202515225 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 242954457 1 T1 92074 T2 1504 T3 441722



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 1380878 1 T1 41 T2 13 T17 7448
valid_sources[0x01] 1808040 1 T1 26 T2 7 T17 7567
valid_sources[0x02] 1317428 1 T1 45 T2 22 T17 7885
valid_sources[0x03] 3292910 1 T1 31 T2 4 T17 7619
valid_sources[0x04] 1317519 1 T1 30 T2 4 T17 7463
valid_sources[0x05] 1317496 1 T1 36 T2 3 T17 7540
valid_sources[0x06] 3310973 1 T1 32 T2 19 T17 7532
valid_sources[0x07] 1318805 1 T1 38 T2 7 T17 7768
valid_sources[0x08] 1324929 1 T1 40 T2 5 T17 7820
valid_sources[0x09] 4256275 1 T1 38 T2 13 T17 7667
valid_sources[0x0a] 1316760 1 T1 25 T2 11 T17 7710
valid_sources[0x0b] 3961660 1 T1 34 T2 4 T17 7849
valid_sources[0x0c] 3326283 1 T1 37 T2 9 T17 7566
valid_sources[0x0d] 1319291 1 T1 28 T2 21 T17 7350
valid_sources[0x0e] 3641561 1 T1 36 T2 19 T17 7832
valid_sources[0x0f] 1312339 1 T1 42 T2 17 T17 7601
valid_sources[0x10] 1809211 1 T1 34 T2 4 T17 7816
valid_sources[0x11] 1316550 1 T1 30 T2 7 T17 7419
valid_sources[0x12] 1322299 1 T1 32 T2 19 T17 7818
valid_sources[0x13] 2256088 1 T1 45 T2 10 T3 851586
valid_sources[0x14] 1318233 1 T1 45 T2 10 T17 7333
valid_sources[0x15] 1352495 1 T1 34 T2 25 T17 7588
valid_sources[0x16] 1320874 1 T1 39 T2 10 T17 7761
valid_sources[0x17] 3282415 1 T1 31 T2 8 T17 7623
valid_sources[0x18] 1314705 1 T1 33 T2 4 T17 7563
valid_sources[0x19] 1482669 1 T1 28 T2 4 T17 8159
valid_sources[0x1a] 1315932 1 T1 35 T2 1 T17 7795
valid_sources[0x1b] 1428141 1 T1 29 T2 9 T17 7887
valid_sources[0x1c] 1995572 1 T1 39 T2 3 T17 7906
valid_sources[0x1d] 1821408 1 T1 28 T2 13 T17 7590
valid_sources[0x1e] 1316907 1 T1 30 T2 7 T17 7410
valid_sources[0x1f] 1315435 1 T1 32 T2 12 T17 7497
valid_sources[0x20] 1316047 1 T1 33 T2 15 T17 7231
valid_sources[0x21] 1359221 1 T1 47 T2 4 T17 7586
valid_sources[0x22] 1345462 1 T1 43 T2 7 T17 7618
valid_sources[0x23] 1318156 1 T1 31 T2 7 T17 7530
valid_sources[0x24] 1317811 1 T1 50 T2 5 T17 7813
valid_sources[0x25] 1325165 1 T1 32 T2 18 T17 7553
valid_sources[0x26] 1323500 1 T1 39 T2 7 T17 7477
valid_sources[0x27] 1316271 1 T1 30 T2 12 T17 7630
valid_sources[0x28] 1317143 1 T1 27 T2 5 T17 7742
valid_sources[0x29] 2006310 1 T1 37 T2 19 T38 25
valid_sources[0x2a] 1312353 1 T1 50 T17 7689 T39 1698
valid_sources[0x2b] 1314442 1 T1 41 T2 13 T17 7774
valid_sources[0x2c] 1319444 1 T1 32 T2 5 T17 7416
valid_sources[0x2d] 1323205 1 T1 30 T2 14 T17 7648
valid_sources[0x2e] 1314235 1 T1 44 T2 2 T17 7742
valid_sources[0x2f] 1323641 1 T1 36 T2 4 T17 7768
valid_sources[0x30] 1322325 1 T1 34 T2 14 T17 7214
valid_sources[0x31] 1977416 1 T1 36 T2 5 T17 7597
valid_sources[0x32] 1324503 1 T1 28 T2 11 T17 7937
valid_sources[0x33] 1324605 1 T1 39 T2 11 T17 7805
valid_sources[0x34] 1320962 1 T1 42 T2 2 T17 7672
valid_sources[0x35] 1319122 1 T1 37 T2 11 T17 7597
valid_sources[0x36] 1329976 1 T1 30 T2 15 T17 7804
valid_sources[0x37] 1321449 1 T1 33 T2 7 T17 7466
valid_sources[0x38] 1771917 1 T1 30 T2 8 T17 7748
valid_sources[0x39] 3669395 1 T1 24 T2 9 T17 7704
valid_sources[0x3a] 2980064 1 T1 39 T2 7 T17 7744
valid_sources[0x3b] 1769409 1 T1 29 T2 8 T17 7412
valid_sources[0x3c] 1525499 1 T1 42 T2 15 T17 7614
valid_sources[0x3d] 1325144 1 T1 35 T2 9 T17 7696
valid_sources[0x3e] 1316758 1 T1 21 T2 9 T17 7556
valid_sources[0x3f] 1321070 1 T1 50 T2 12 T17 7322
valid_sources[0x40] 1314146 1 T1 29 T2 15 T17 7451
valid_sources[0x41] 2323471 1 T1 40 T2 4 T17 7684
valid_sources[0x42] 1314183 1 T1 33 T2 4 T17 7626
valid_sources[0x43] 1317345 1 T1 35 T2 9 T17 7590
valid_sources[0x44] 1761645 1 T1 36 T2 17 T17 7512
valid_sources[0x45] 1328934 1 T1 46 T2 3 T17 7458
valid_sources[0x46] 2196205 1 T1 30 T2 7 T17 7687
valid_sources[0x47] 1318558 1 T1 29 T2 11 T17 7686
valid_sources[0x48] 1318248 1 T1 43 T2 16 T17 7818
valid_sources[0x49] 1319208 1 T1 42 T2 14 T17 7645
valid_sources[0x4a] 1314915 1 T1 37 T2 8 T17 8125
valid_sources[0x4b] 1401607 1 T1 28 T2 17 T17 7562
valid_sources[0x4c] 1465497 1 T1 42 T2 8 T17 7758
valid_sources[0x4d] 1319502 1 T1 36 T2 8 T17 7861
valid_sources[0x4e] 1323243 1 T1 40 T2 8 T17 7584
valid_sources[0x4f] 1317152 1 T1 42 T2 4 T17 7725
valid_sources[0x50] 1315636 1 T1 42 T2 5 T17 7694
valid_sources[0x51] 1317545 1 T1 36 T2 7 T17 7673
valid_sources[0x52] 1318952 1 T1 40 T2 9 T17 7720
valid_sources[0x53] 1335310 1 T1 36 T2 3 T17 7374
valid_sources[0x54] 1445586 1 T1 29 T2 12 T17 7743
valid_sources[0x55] 1324917 1 T1 44 T2 10 T17 7679
valid_sources[0x56] 2186515 1 T1 39 T2 5 T17 7646
valid_sources[0x57] 1324410 1 T1 40 T2 2 T17 7675
valid_sources[0x58] 2222364 1 T1 34 T2 10 T17 7578
valid_sources[0x59] 1318086 1 T1 33 T2 11 T17 7501
valid_sources[0x5a] 1317311 1 T1 45 T2 14 T17 7464
valid_sources[0x5b] 1319384 1 T1 32 T2 15 T17 7617
valid_sources[0x5c] 1457742 1 T1 31 T2 3 T17 7552
valid_sources[0x5d] 4488345 1 T1 30 T2 18 T17 7589
valid_sources[0x5e] 1325160 1 T1 33 T2 3 T17 7747
valid_sources[0x5f] 1314785 1 T1 27 T2 12 T17 7709
valid_sources[0x60] 1323251 1 T1 33 T2 2 T17 7658
valid_sources[0x61] 1971163 1 T1 32 T2 8 T17 7525
valid_sources[0x62] 3860369 1 T1 30 T2 26 T17 7582
valid_sources[0x63] 1971050 1 T1 38 T2 5 T17 7593
valid_sources[0x64] 1909723 1 T1 28 T2 13 T17 7862
valid_sources[0x65] 1315223 1 T1 31 T2 5 T17 7417
valid_sources[0x66] 3630586 1 T1 33 T2 7 T17 7876
valid_sources[0x67] 4229379 1 T1 31 T2 12 T17 7564
valid_sources[0x68] 1308642 1 T1 28 T2 5 T17 7938
valid_sources[0x69] 1314096 1 T1 40 T2 13 T17 7708
valid_sources[0x6a] 1771620 1 T1 35 T2 17 T17 7677
valid_sources[0x6b] 2730888 1 T1 45 T2 7 T17 7490
valid_sources[0x6c] 1318082 1 T1 39 T2 18 T17 7963
valid_sources[0x6d] 1316436 1 T1 38 T2 8 T17 7567
valid_sources[0x6e] 3690252 1 T1 42 T2 14 T17 7663
valid_sources[0x6f] 1321511 1 T1 46 T2 7 T17 7668
valid_sources[0x70] 1331573 1 T1 31 T2 12 T17 7341
valid_sources[0x71] 2158668 1 T1 24 T2 7 T17 7532
valid_sources[0x72] 1322301 1 T1 26 T2 12 T17 7833
valid_sources[0x73] 3651254 1 T1 41 T2 5 T17 7476
valid_sources[0x74] 1317300 1 T1 33 T2 5 T17 7640
valid_sources[0x75] 2201176 1 T1 30 T2 2 T17 7535
valid_sources[0x76] 1318102 1 T1 31 T2 12 T17 7535
valid_sources[0x77] 1317864 1 T1 33 T2 6 T17 7551
valid_sources[0x78] 3326523 1 T1 38 T2 7 T17 7254
valid_sources[0x79] 1313257 1 T1 28 T2 8 T17 7480
valid_sources[0x7a] 3278590 1 T1 37 T2 13 T17 7646
valid_sources[0x7b] 1318680 1 T1 38 T2 10 T17 7612
valid_sources[0x7c] 1316837 1 T1 38 T2 6 T17 7489
valid_sources[0x7d] 3683086 1 T1 28 T2 12 T17 7625
valid_sources[0x7e] 1313267 1 T1 30 T2 13 T17 7593
valid_sources[0x7f] 1325376 1 T1 22 T2 9 T17 7553
valid_sources[0x80] 1366780 1 T1 31 T2 4 T17 7529



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 71513792 1 T1 56256 T2 37 T3 110952
values[0x0] all_enables biggest_size 60966482 1 T1 12511 T2 537 T3 116574
values[0x1] all_enables biggest_size 52478927 1 T1 10860 T2 514 T3 98837

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%