Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

261170765

1

T1

53946

T2

1258

T3

525223

full_word

185000908

1

T1

79627

T2

1088

T3

326363

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	446171333	1			T1	133573		T2	2346		T3	851586
auto[TlIntgErrCmd]	112	1			T122	8		T123	4		T124	6
auto[TlIntgErrData]	118	1			T122	8		T123	4		T124	6
auto[TlIntgErrBoth]	110	1			T122	4		T123	2		T124	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

230876204

1

T1

89619

T2

1236

T3

426047

auto[1]

215295469

1

T1

43954

T2

1110

T3

425539

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	159351886	1			T1	33363		T2	1199		T3	315095
auto[TlIntgErrNone]	partial	auto[1]	101818571	1			T1	20583		T2	59		T3	210128
auto[TlIntgErrNone]	full_word	auto[0]	71524176	1			T1	56256		T2	37		T3	110952
auto[TlIntgErrNone]	full_word	auto[1]	113476700	1			T1	23371		T2	1051		T3	215411
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T122	1		T123	2		T124	2
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T122	7		T123	1		T124	4
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T123	1		T179	1		T182	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T166	3		T179	1		T180	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T122	5		T123	1		T124	3
auto[TlIntgErrData]	partial	auto[1]	62	1			T122	3		T123	3		T124	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T124	1		T183	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T177	1		T181	1		T184	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T122	1		T123	1		T124	2
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T122	3		T123	1		T124	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T124	2		T180	1		T181	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T166	1		T176	1		T179	1