Unified Coverage Report :: Module :: sha3pad

Module : sha3pad

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.89	99.41	88.37		80.95	95.70	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3.u_pad	95.59	99.41	88.37		94.44	95.70	100.00

---

Module Instance : tb.dut.u_sha3.u_pad

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.59	99.41	88.37		94.44	95.70	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.34	99.45	88.37	100.00	94.44	95.79	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	97.56	88.89		100.00	93.33	100.00	u_sha3

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prefix_slicer	100.00	100.00					100.00
u_sentmsg_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : sha3pad

	Line No.	Total	Covered	Percent
TOTAL		170	169	99.41
ALWAYS	157	6	6	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	257	1	1	100.00
ALWAYS	267	6	6	100.00
ALWAYS	279	3	3	100.00
CONT_ASSIGN	286	1	1	100.00
ALWAYS	293	3	3	100.00
ALWAYS	298	76	75	98.68
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	538	1	1	100.00
ALWAYS	558	4	4	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	588	1	1	100.00
ALWAYS	591	5	5	100.00
ALWAYS	603	5	5	100.00
ALWAYS	615	5	5	100.00
ALWAYS	664	10	10	100.00
ALWAYS	680	17	17	100.00
ALWAYS	779	6	6	100.00
ALWAYS	788	6	6	100.00
ALWAYS	798	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
209	1	1
213	1	1
236	1	1
242	1	1
247	1	1
257	1	1
267	1	1
268	1	1
269	1	1
270	1	1
271	1	1
272	1	1
			MISSING_ELSE
279	3	3
286	1	1
293	2	2
294	1	1
298	1	1
301	1	1
302	1	1
304	1	1
306	1	1
307	1	1
309	1	1
310	1	1
312	1	1
314	1	1
316	1	1
325	1	1
327	1	1
328	1	1
330	1	1
333	1	1
345	1	1
347	1	1
348	1	1
350	1	1
351	1	1
352	1	1
354	1	1
356	1	1
361	1	1
363	1	1
364	1	1
366	1	1
375	1	1
377	1	1
378	1	1
380	1	1
381	1	1
383	1	1
385	1	1
386	1	1
387	1	1
388	1	1
389	1	1
392	1	1
394	1	1
400	1	1
402	1	1
403	1	1
405	1	1
414	1	1
416	1	1
418	1	1
421	1	1
424	1	1
425	1	1
426	1	1
427	1	1
428	1	1
430	0	1
435	1	1
437	1	1
438	1	1
447	1	1
451	1	1
452	1	1
454	1	1
455	1	1
456	1	1
458	1	1
460	1	1
466	1	1
467	1	1
469	1	1
470	1	1
472	1	1
474	1	1
480	1	1
481	1	1
494	1	1
495	1	1
			MISSING_ELSE
509	1	1
520	1	1
538	1	1
558	1	1
559	1	1
560	1	1
561	1	1
578	1	1
588	1	1
591	1	1
592	1	1
593	1	1
594	1	1
595	1	1
603	1	1
604	1	1
605	1	1
606	1	1
607	1	1
615	1	1
616	1	1
617	1	1
618	1	1
619	1	1
664	1	1
665	1	1
666	1	1
667	1	1
668	1	1
669	1	1
671	1	1
672	1	1
673	1	1
674	1	1
			MISSING_ELSE
680	1	1
682	1	1
683	1	1
686	1	1
687	1	1
690	1	1
691	1	1
694	1	1
695	1	1
698	1	1
699	1	1
702	1	1
703	1	1
706	1	1
707	1	1
710	1	1
711	1	1
779	1	1
780	1	1
781	1	1
782	1	1
783	1	1
784	1	1
			MISSING_ELSE
788	1	1
789	1	1
790	1	1
791	1	1
792	1	1
793	1	1
			MISSING_ELSE
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE

---

Cond Coverage for Module : sha3pad

	Total	Covered	Percent
Conditions	43	38	88.37
Logical	43	38	88.37
Non-Logical	0	0
Event	0	0

 LINE       209
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       213
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION ((mode_i == CShake) ? 1'b1 : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T35

 LINE       236
 SUB-EXPRESSION (mode_i == CShake)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T35

 LINE       242
 EXPRESSION ((sent_message == block_addr_limit) ? 1'b1 : 1'b0)
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       242
 SUB-EXPRESSION (sent_message == block_addr_limit)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       247
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       257
 EXPRESSION ((&msg_strb_i) != 1'b1)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION (((sent_message + 1'b1) == block_addr_limit) ? 1'b1 : 1'b0)
             ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 SUB-EXPRESSION ((sent_message + 1'b1) == block_addr_limit)
                ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       377
 EXPRESSION (msg_valid_i && msg_partial)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T17

 LINE       388
 EXPRESSION (process_latched || process_i)
             -------1-------    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T17

 LINE       418
 EXPRESSION (keccak_ack && end_of_block)
             -----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T17

 LINE       588
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       604
 EXPRESSION (msg_valid_i & ((~hold_msg)) & ((~en_msgbuf)))
             -----1-----   ------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T19,T44
1	1	0	Covered	T1,T3,T17
1	1	1	Covered	T1,T2,T3

 LINE       616
 EXPRESSION (en_msgbuf | (keccak_ready_i & ((~hold_msg))))
             ----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       616
 SUB-EXPRESSION (keccak_ready_i & ((~hold_msg)))
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : sha3pad

Summary for FSM :: st

	Total	Covered	Percent
States	10	10	100.00	(Not included in score)
Transitions	21	17	80.95
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StMessage	330	Covered	T1,T2,T3
StMessageWait	383	Covered	T1,T2,T3
StPad	389	Covered	T1,T2,T3
StPad01	427	Covered	T1,T2,T3
StPadFlush	435	Covered	T1,T2,T3
StPadIdle	333	Covered	T1,T2,T3
StPadRun	421	Covered	T1,T3,T17
StPrefix	328	Covered	T1,T2,T35
StPrefixWait	348	Covered	T1,T2,T35
StTerminalError	495	Covered	T11,T12,T13

transitions	Line No.	Covered	Tests
StMessage->StMessageWait	383	Covered	T1,T2,T3
StMessage->StPad	389	Covered	T1,T2,T3
StMessage->StTerminalError	495	Covered	T48,T49,T64
StMessageWait->StMessage	403	Covered	T1,T2,T3
StMessageWait->StTerminalError	495	Covered	T53,T50,T55
StPad->StPad01	427	Covered	T1,T2,T3
StPad->StPadRun	421	Covered	T1,T3,T17
StPad->StTerminalError	495	Not Covered
StPad01->StPadFlush	452	Covered	T1,T2,T3
StPad01->StTerminalError	495	Not Covered
StPadFlush->StPadIdle	470	Covered	T1,T2,T3
StPadFlush->StTerminalError	495	Not Covered
StPadIdle->StMessage	330	Covered	T1,T3,T17
StPadIdle->StPrefix	328	Covered	T1,T2,T35
StPadIdle->StTerminalError	495	Covered	T31,T34,T32
StPadRun->StPadFlush	435	Covered	T1,T3,T17
StPadRun->StTerminalError	495	Not Covered
StPrefix->StPrefixWait	348	Covered	T1,T2,T35
StPrefix->StTerminalError	495	Covered	T65,T30
StPrefixWait->StMessage	364	Covered	T1,T2,T35
StPrefixWait->StTerminalError	495	Covered	T11,T12,T13

---

Branch Coverage for Module : sha3pad

	Line No.	Total	Covered	Percent
Branches		93	89	95.70
TERNARY	213	2	2	100.00
TERNARY	236	2	2	100.00
TERNARY	242	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	588	2	2	100.00
CASE	157	6	5	83.33
IF	267	4	4	100.00
IF	279	2	2	100.00
IF	293	2	2	100.00
CASE	316	23	22	95.65
IF	494	2	2	100.00
CASE	558	4	3	75.00
CASE	591	5	5	100.00
CASE	603	5	5	100.00
CASE	615	5	5	100.00
IF	664	4	4	100.00
IF	779	4	4	100.00
IF	788	4	4	100.00
IF	798	4	4	100.00
CASE	680	9	8	88.89

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	213	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	236	((mode_i == CShake)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T35
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	242	((sent_message == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(((sent_message + 1'b1) == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	588	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	157	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T1,T2,T3
L224	Covered	T1,T22,T7
L256	Covered	T1,T2,T3
L384	Covered	T1,T2,T6
L512	Covered	T39,T6,T66
default	Not Covered

	LineNo.	Expression
-1-:	267	if ((!rst_ni))
-2-:	269	if (process_i)
-3-:	271	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	279	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	293	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	316	case (st)
-2-:	325	if (start_i)
-3-:	327	if (mode_eq_cshake)
-4-:	347	if (sent_blocksize)
-5-:	363	if (keccak_complete_i)
-6-:	377	if ((msg_valid_i && msg_partial))
-7-:	381	if (sent_blocksize)
-8-:	388	if ((process_latched || process_i))
-9-:	402	if (keccak_complete_i)
-10-:	418	if ((keccak_ack && end_of_block))
-11-:	426	if (keccak_ack)
-12-:	451	if (sent_blocksize)
-13-:	469	if (keccak_complete_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StPadIdle	1	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T35
StPadIdle	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T17
StPadIdle	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrefix	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T35
StPrefix	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T35
StPrefixWait	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T35
StPrefixWait	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T35
StMessage	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T3,T17
StMessage	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T1,T2,T3
StMessage	-	-	-	-	0	0	1	-	-	-	-	-	Covered	T1,T2,T3
StMessage	-	-	-	-	0	0	0	-	-	-	-	-	Covered	T1,T2,T3
StMessageWait	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T3
StMessageWait	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
StPad	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T1,T3,T17
StPad	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T1,T2,T3
StPad	-	-	-	-	-	-	-	-	0	0	-	-	Not Covered
StPadRun	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T17
StPad01	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T3
StPad01	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T2,T3
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	494	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	558	case (mode_i)

Branches:

-1-	Status	Tests
Sha3	Covered	T1,T2,T3
Shake	Covered	T1,T2,T17
CShake	Covered	T1,T2,T35
default	Not Covered

	LineNo.	Expression
-1-:	591	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T1,T2,T3
MuxPrefix	Covered	T1,T2,T35
MuxFuncPad	Covered	T1,T2,T3
MuxZeroEnd	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	603	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T1,T2,T3
MuxPrefix	Covered	T1,T2,T35
MuxFuncPad	Covered	T1,T2,T3
MuxZeroEnd	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	615	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T1,T2,T3
MuxPrefix	Covered	T1,T2,T35
MuxFuncPad	Covered	T1,T2,T3
MuxZeroEnd	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	664	if ((!rst_ni))
-2-:	667	if (en_msgbuf)
-3-:	672	if (clr_msgbuf)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T17
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	779	if ((!rst_ni))
-2-:	781	if (start_i)
-3-:	783	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	788	if ((!rst_ni))
-2-:	790	if (start_i)
-3-:	792	if (process_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	798	if ((!rst_ni))
-2-:	800	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_o))
-3-:	802	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	680	case (msg_strb)

Branches:

-1-	Status	Tests
7'b0000000	Covered	T1,T2,T3
7'b0000001	Covered	T1,T3,T17
7'b0000011	Covered	T1,T3,T17
7'b0000111	Covered	T1,T3,T17
7'b0001111	Covered	T1,T3,T17
7'b0011111	Covered	T1,T3,T17
7'b0111111	Covered	T1,T3,T17
7'b1111111	Covered	T1,T3,T17
default	Not Covered

---

Assert Coverage for Module : sha3pad

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	4	4	100.00	4	100.00
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AbsorbedPulse_A	2147483647	345305	0	0
AlwaysPartialMsgBuf_M	2147483647	196020	0	0
CompleteBlockWhenProcess_A	2147483647	333255	0	0
DoneCondition_M	2147483647	345300	0	0
DonePulse_A	2147483647	345300	0	0
KeccakAddrInRange_A	2147483647	52876543	0	0
KeccakRunPulse_A	2147483647	3064838	0	0
MessageCondition_M	2147483647	48194520	0	0
ModeStableDuringOp_M	2147483647	32619	0	0
MsgReadyCondition_A	2147483647	2144396470	0	0
MsgWidthidth_A	1022	1022	0	0
NoPartialMsgFifo_M	2147483647	47998500	0	0
Pad01NotAttheEndOfBlock_A	2147483647	334655	0	0
PartialEndOfMsg_M	2147483647	196020	0	0
PrefixLessThanBlock_A	1022	1022	0	0
ProcessCondition_M	2147483647	345310	0	0
ProcessPulse_A	2147483647	345310	0	0
StartCondition_M	2147483647	345355	0	0
StartProcessDoneMutex_a	2147483647	2147483647	0	0
StartPulse_A	2147483647	345355	0	0
StrengthStableDuringOp_M	2147483647	39578	0	0
u_state_regs_A	2147483647	2147483647	0	0

AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345305	0	0
T1	161611	174	0	0
T2	167210	19	0	0
T3	191537	374	0	0
T6	0	84	0	0
T17	149490	2265	0	0
T35	25641	9	0	0
T36	19708	9	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	246	0	0
T40	2138	0	0	0
T42	0	9	0	0
T56	0	9	0	0

AlwaysPartialMsgBuf_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	196020	0	0
T1	161611	133	0	0
T2	167210	0	0	0
T3	191537	326	0	0
T6	0	76	0	0
T17	149490	890	0	0
T22	0	96	0	0
T35	25641	9	0	0
T36	19708	9	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	214	0	0
T40	2138	0	0	0
T42	0	9	0	0
T56	0	9	0	0

CompleteBlockWhenProcess_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	333255	0	0
T1	161611	159	0	0
T2	167210	19	0	0
T3	191537	356	0	0
T6	0	78	0	0
T17	149490	2211	0	0
T35	25641	9	0	0
T36	19708	9	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	219	0	0
T40	2138	0	0	0
T42	0	9	0	0
T56	0	9	0	0

DoneCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345300	0	0
T1	161611	174	0	0
T2	167210	19	0	0
T3	191537	374	0	0
T6	0	84	0	0
T17	149490	2265	0	0
T35	25641	9	0	0
T36	19708	9	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	246	0	0
T40	2138	0	0	0
T42	0	9	0	0
T56	0	9	0	0

DonePulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345300	0	0
T1	161611	174	0	0
T2	167210	19	0	0
T3	191537	374	0	0
T6	0	84	0	0
T17	149490	2265	0	0
T35	25641	9	0	0
T36	19708	9	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	246	0	0
T40	2138	0	0	0
T42	0	9	0	0
T56	0	9	0	0

KeccakAddrInRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	52876543	0	0
T1	161611	16677	0	0
T2	167210	969	0	0
T3	191537	93942	0	0
T6	0	7118	0	0
T17	149490	220643	0	0
T35	25641	607	0	0
T36	19708	607	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	48843	0	0
T40	2138	0	0	0
T42	0	607	0	0
T56	0	607	0	0

KeccakRunPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3064838	0	0
T1	161611	911	0	0
T2	167210	57	0	0
T3	191537	5526	0	0
T6	0	390	0	0
T17	149490	12979	0	0
T35	25641	31	0	0
T36	19708	31	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	5427	0	0
T40	2138	0	0	0
T42	0	31	0	0
T56	0	31	0	0

MessageCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48194520	0	0
T1	161611	12901	0	0
T2	167210	323	0	0
T3	191537	90674	0	0
T6	0	5367	0	0
T17	149490	195716	0	0
T35	25641	286	0	0
T36	19708	286	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	47746	0	0
T40	2138	0	0	0
T42	0	286	0	0
T56	0	286	0	0

ModeStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	32619	0	0
T1	161611	180	0	0
T2	167210	35	0	0
T3	191537	0	0	0
T6	0	98	0	0
T17	149490	1	0	0
T22	0	45	0	0
T35	25641	1	0	0
T36	19708	1	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	0	0	0
T40	2138	6	0	0
T42	0	1	0	0
T56	0	1	0	0

MsgReadyCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2144396470	0	0
T1	161611	837212	0	0
T2	167210	156902	0	0
T3	191537	117494	0	0
T6	0	471125	0	0
T17	149490	117006	0	0
T35	25641	1006	0	0
T36	19708	5769	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	414372	0	0
T40	2138	0	0	0
T42	0	7248	0	0
T56	0	6932	0	0

MsgWidthidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T17	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0

NoPartialMsgFifo_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	47998500	0	0
T1	161611	12768	0	0
T2	167210	323	0	0
T3	191537	90348	0	0
T6	0	5291	0	0
T17	149490	194826	0	0
T35	25641	277	0	0
T36	19708	277	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	47532	0	0
T40	2138	0	0	0
T42	0	277	0	0
T56	0	277	0	0

Pad01NotAttheEndOfBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	334655	0	0
T1	161611	162	0	0
T2	167210	19	0	0
T3	191537	358	0	0
T6	0	78	0	0
T17	149490	2217	0	0
T35	25641	9	0	0
T36	19708	9	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	222	0	0
T40	2138	0	0	0
T42	0	9	0	0
T56	0	9	0	0

PartialEndOfMsg_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	196020	0	0
T1	161611	133	0	0
T2	167210	0	0	0
T3	191537	326	0	0
T6	0	76	0	0
T17	149490	890	0	0
T22	0	96	0	0
T35	25641	9	0	0
T36	19708	9	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	214	0	0
T40	2138	0	0	0
T42	0	9	0	0
T56	0	9	0	0

PrefixLessThanBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T17	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0

ProcessCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345310	0	0
T1	161611	174	0	0
T2	167210	19	0	0
T3	191537	374	0	0
T6	0	84	0	0
T17	149490	2265	0	0
T35	25641	9	0	0
T36	19708	9	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	246	0	0
T40	2138	0	0	0
T42	0	9	0	0
T56	0	9	0	0

ProcessPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345310	0	0
T1	161611	174	0	0
T2	167210	19	0	0
T3	191537	374	0	0
T6	0	84	0	0
T17	149490	2265	0	0
T35	25641	9	0	0
T36	19708	9	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	246	0	0
T40	2138	0	0	0
T42	0	9	0	0
T56	0	9	0	0

StartCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345355	0	0
T1	161611	174	0	0
T2	167210	19	0	0
T3	191537	374	0	0
T6	0	84	0	0
T17	149490	2265	0	0
T35	25641	9	0	0
T36	19708	9	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	246	0	0
T40	2138	0	0	0
T42	0	9	0	0
T56	0	9	0	0

StartProcessDoneMutex_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	161611	161603	0	0
T2	167210	167127	0	0
T3	191537	191530	0	0
T17	149490	149489	0	0
T35	25641	25589	0	0
T36	19708	19633	0	0
T37	1172	1104	0	0
T38	1957	1865	0	0
T39	490351	490344	0	0
T40	2138	2039	0	0

StartPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345355	0	0
T1	161611	174	0	0
T2	167210	19	0	0
T3	191537	374	0	0
T6	0	84	0	0
T17	149490	2265	0	0
T35	25641	9	0	0
T36	19708	9	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	246	0	0
T40	2138	0	0	0
T42	0	9	0	0
T56	0	9	0	0

StrengthStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39578	0	0
T1	161611	172	0	0
T2	167210	40	0	0
T3	191537	2	0	0
T17	149490	2	0	0
T35	25641	2	0	0
T36	19708	2	0	0
T37	1172	1	0	0
T38	1957	1	0	0
T39	490351	2	0	0
T40	2138	8	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	161611	161603	0	0
T2	167210	167127	0	0
T3	191537	191530	0	0
T17	149490	149489	0	0
T35	25641	25589	0	0
T36	19708	19633	0	0
T37	1172	1104	0	0
T38	1957	1865	0	0
T39	490351	490344	0	0
T40	2138	2039	0	0

---

Cover Directives for Properties: Details

Name	Attempts	Matches	Incomplete
StComplete_C	2147483647	33520287	0
StMessageFeed_C	2147483647	2147424573	0
StPadSendMsg_C	2147483647	3842053	0
StPad_C	2147483647	334655	0

StComplete_C

Name	Attempts	Matches	Incomplete
Total	2147483647	33520287	0
T1	161611	16878	0
T2	167210	1843	0
T3	191537	36278	0
T6	0	8148	0
T17	149490	219755	0
T35	25641	873	0
T36	19708	873	0
T37	1172	0	0
T38	1957	0	0
T39	490351	23862	0
T40	2138	0	0
T42	0	873	0
T56	0	873	0

StMessageFeed_C

Name	Attempts	Matches	Incomplete
Total	2147483647	2147424573	0
T1	161611	838005	0
T2	167210	156940	0
T3	191537	118046	0
T6	0	471462	0
T17	149490	117136	0
T35	25641	1028	0
T36	19708	5791	0
T37	1172	0	0
T38	1957	0	0
T39	490351	414915	0
T40	2138	0	0
T42	0	7270	0
T56	0	6954	0

StPadSendMsg_C

Name	Attempts	Matches	Incomplete
Total	2147483647	3842053	0
T1	161611	1557	0
T2	167210	304	0
T3	191537	3220	0
T6	0	758	0
T17	149490	23552	0
T35	25641	144	0
T36	19708	144	0
T37	1172	0	0
T38	1957	0	0
T39	490351	1065	0
T40	2138	0	0
T42	0	144	0
T56	0	144	0

StPad_C

Name	Attempts	Matches	Incomplete
Total	2147483647	334655	0
T1	161611	162	0
T2	167210	19	0
T3	191537	358	0
T6	0	78	0
T17	149490	2217	0
T35	25641	9	0
T36	19708	9	0
T37	1172	0	0
T38	1957	0	0
T39	490351	222	0
T40	2138	0	0
T42	0	9	0
T56	0	9	0

Line Coverage for Instance : tb.dut.u_sha3.u_pad

	Line No.	Total	Covered	Percent
TOTAL		170	169	99.41
ALWAYS	157	6	6	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	257	1	1	100.00
ALWAYS	267	6	6	100.00
ALWAYS	279	3	3	100.00
CONT_ASSIGN	286	1	1	100.00
ALWAYS	293	3	3	100.00
ALWAYS	298	76	75	98.68
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	538	1	1	100.00
ALWAYS	558	4	4	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	588	1	1	100.00
ALWAYS	591	5	5	100.00
ALWAYS	603	5	5	100.00
ALWAYS	615	5	5	100.00
ALWAYS	664	10	10	100.00
ALWAYS	680	17	17	100.00
ALWAYS	779	6	6	100.00
ALWAYS	788	6	6	100.00
ALWAYS	798	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
209	1	1
213	1	1
236	1	1
242	1	1
247	1	1
257	1	1
267	1	1
268	1	1
269	1	1
270	1	1
271	1	1
272	1	1
			MISSING_ELSE
279	3	3
286	1	1
293	2	2
294	1	1
298	1	1
301	1	1
302	1	1
304	1	1
306	1	1
307	1	1
309	1	1
310	1	1
312	1	1
314	1	1
316	1	1
325	1	1
327	1	1
328	1	1
330	1	1
333	1	1
345	1	1
347	1	1
348	1	1
350	1	1
351	1	1
352	1	1
354	1	1
356	1	1
361	1	1
363	1	1
364	1	1
366	1	1
375	1	1
377	1	1
378	1	1
380	1	1
381	1	1
383	1	1
385	1	1
386	1	1
387	1	1
388	1	1
389	1	1
392	1	1
394	1	1
400	1	1
402	1	1
403	1	1
405	1	1
414	1	1
416	1	1
418	1	1
421	1	1
424	1	1
425	1	1
426	1	1
427	1	1
428	1	1
430	0	1
435	1	1
437	1	1
438	1	1
447	1	1
451	1	1
452	1	1
454	1	1
455	1	1
456	1	1
458	1	1
460	1	1
466	1	1
467	1	1
469	1	1
470	1	1
472	1	1
474	1	1
480	1	1
481	1	1
494	1	1
495	1	1
			MISSING_ELSE
509	1	1
520	1	1
538	1	1
558	1	1
559	1	1
560	1	1
561	1	1
578	1	1
588	1	1
591	1	1
592	1	1
593	1	1
594	1	1
595	1	1
603	1	1
604	1	1
605	1	1
606	1	1
607	1	1
615	1	1
616	1	1
617	1	1
618	1	1
619	1	1
664	1	1
665	1	1
666	1	1
667	1	1
668	1	1
669	1	1
671	1	1
672	1	1
673	1	1
674	1	1
			MISSING_ELSE
680	1	1
682	1	1
683	1	1
686	1	1
687	1	1
690	1	1
691	1	1
694	1	1
695	1	1
698	1	1
699	1	1
702	1	1
703	1	1
706	1	1
707	1	1
710	1	1
711	1	1
779	1	1
780	1	1
781	1	1
782	1	1
783	1	1
784	1	1
			MISSING_ELSE
788	1	1
789	1	1
790	1	1
791	1	1
792	1	1
793	1	1
			MISSING_ELSE
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sha3.u_pad

	Total	Covered	Percent
Conditions	43	38	88.37
Logical	43	38	88.37
Non-Logical	0	0
Event	0	0

 LINE       209
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       213
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION ((mode_i == CShake) ? 1'b1 : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T35

 LINE       236
 SUB-EXPRESSION (mode_i == CShake)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T35

 LINE       242
 EXPRESSION ((sent_message == block_addr_limit) ? 1'b1 : 1'b0)
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       242
 SUB-EXPRESSION (sent_message == block_addr_limit)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       247
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       257
 EXPRESSION ((&msg_strb_i) != 1'b1)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION (((sent_message + 1'b1) == block_addr_limit) ? 1'b1 : 1'b0)
             ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 SUB-EXPRESSION ((sent_message + 1'b1) == block_addr_limit)
                ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       377
 EXPRESSION (msg_valid_i && msg_partial)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T17

 LINE       388
 EXPRESSION (process_latched || process_i)
             -------1-------    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T17

 LINE       418
 EXPRESSION (keccak_ack && end_of_block)
             -----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T17

 LINE       588
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       604
 EXPRESSION (msg_valid_i & ((~hold_msg)) & ((~en_msgbuf)))
             -----1-----   ------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T19,T44
1	1	0	Covered	T1,T3,T17
1	1	1	Covered	T1,T2,T3

 LINE       616
 EXPRESSION (en_msgbuf | (keccak_ready_i & ((~hold_msg))))
             ----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       616
 SUB-EXPRESSION (keccak_ready_i & ((~hold_msg)))
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_sha3.u_pad

Summary for FSM :: st

	Total	Covered	Percent
States	10	10	100.00	(Not included in score)
Transitions	18	17	94.44
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StMessage	330	Covered	T1,T2,T3
StMessageWait	383	Covered	T1,T2,T3
StPad	389	Covered	T1,T2,T3
StPad01	427	Covered	T1,T2,T3
StPadFlush	435	Covered	T1,T2,T3
StPadIdle	333	Covered	T1,T2,T3
StPadRun	421	Covered	T1,T3,T17
StPrefix	328	Covered	T1,T2,T35
StPrefixWait	348	Covered	T1,T2,T35
StTerminalError	495	Covered	T11,T12,T13

transitions	Line No.	Covered	Tests	Exclude Annotation
StMessage->StMessageWait	383	Covered	T1,T2,T3
StMessage->StPad	389	Covered	T1,T2,T3
StMessage->StTerminalError	495	Covered	T48,T49,T64
StMessageWait->StMessage	403	Covered	T1,T2,T3
StMessageWait->StTerminalError	495	Covered	T53,T50,T55
StPad->StPad01	427	Covered	T1,T2,T3
StPad->StPadRun	421	Covered	T1,T3,T17
StPad->StTerminalError	495	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPad01->StPadFlush	452	Covered	T1,T2,T3
StPad01->StTerminalError	495	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPadFlush->StPadIdle	470	Covered	T1,T2,T3
StPadFlush->StTerminalError	495	Not Covered
StPadIdle->StMessage	330	Covered	T1,T3,T17
StPadIdle->StPrefix	328	Covered	T1,T2,T35
StPadIdle->StTerminalError	495	Covered	T31,T34,T32
StPadRun->StPadFlush	435	Covered	T1,T3,T17
StPadRun->StTerminalError	495	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPrefix->StPrefixWait	348	Covered	T1,T2,T35
StPrefix->StTerminalError	495	Covered	T65,T30
StPrefixWait->StMessage	364	Covered	T1,T2,T35
StPrefixWait->StTerminalError	495	Covered	T11,T12,T13

---

Branch Coverage for Instance : tb.dut.u_sha3.u_pad

	Line No.	Total	Covered	Percent
Branches		93	89	95.70
TERNARY	213	2	2	100.00
TERNARY	236	2	2	100.00
TERNARY	242	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	588	2	2	100.00
CASE	157	6	5	83.33
IF	267	4	4	100.00
IF	279	2	2	100.00
IF	293	2	2	100.00
CASE	316	23	22	95.65
IF	494	2	2	100.00
CASE	558	4	3	75.00
CASE	591	5	5	100.00
CASE	603	5	5	100.00
CASE	615	5	5	100.00
IF	664	4	4	100.00
IF	779	4	4	100.00
IF	788	4	4	100.00
IF	798	4	4	100.00
CASE	680	9	8	88.89

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	213	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	236	((mode_i == CShake)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T35
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	242	((sent_message == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(((sent_message + 1'b1) == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	588	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	157	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T1,T2,T3
L224	Covered	T1,T22,T7
L256	Covered	T1,T2,T3
L384	Covered	T1,T2,T6
L512	Covered	T39,T6,T66
default	Not Covered

	LineNo.	Expression
-1-:	267	if ((!rst_ni))
-2-:	269	if (process_i)
-3-:	271	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	279	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	293	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	316	case (st)
-2-:	325	if (start_i)
-3-:	327	if (mode_eq_cshake)
-4-:	347	if (sent_blocksize)
-5-:	363	if (keccak_complete_i)
-6-:	377	if ((msg_valid_i && msg_partial))
-7-:	381	if (sent_blocksize)
-8-:	388	if ((process_latched || process_i))
-9-:	402	if (keccak_complete_i)
-10-:	418	if ((keccak_ack && end_of_block))
-11-:	426	if (keccak_ack)
-12-:	451	if (sent_blocksize)
-13-:	469	if (keccak_complete_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StPadIdle	1	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T35
StPadIdle	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T17
StPadIdle	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrefix	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T35
StPrefix	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T35
StPrefixWait	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T35
StPrefixWait	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T35
StMessage	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T3,T17
StMessage	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T1,T2,T3
StMessage	-	-	-	-	0	0	1	-	-	-	-	-	Covered	T1,T2,T3
StMessage	-	-	-	-	0	0	0	-	-	-	-	-	Covered	T1,T2,T3
StMessageWait	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T3
StMessageWait	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
StPad	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T1,T3,T17
StPad	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T1,T2,T3
StPad	-	-	-	-	-	-	-	-	0	0	-	-	Not Covered
StPadRun	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T17
StPad01	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T3
StPad01	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T2,T3
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T31,T32,T33

	LineNo.	Expression
-1-:	494	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	558	case (mode_i)

Branches:

-1-	Status	Tests
Sha3	Covered	T1,T2,T3
Shake	Covered	T1,T2,T17
CShake	Covered	T1,T2,T35
default	Not Covered

	LineNo.	Expression
-1-:	591	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T1,T2,T3
MuxPrefix	Covered	T1,T2,T35
MuxFuncPad	Covered	T1,T2,T3
MuxZeroEnd	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	603	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T1,T2,T3
MuxPrefix	Covered	T1,T2,T35
MuxFuncPad	Covered	T1,T2,T3
MuxZeroEnd	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	615	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T1,T2,T3
MuxPrefix	Covered	T1,T2,T35
MuxFuncPad	Covered	T1,T2,T3
MuxZeroEnd	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	664	if ((!rst_ni))
-2-:	667	if (en_msgbuf)
-3-:	672	if (clr_msgbuf)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T17
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	779	if ((!rst_ni))
-2-:	781	if (start_i)
-3-:	783	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	788	if ((!rst_ni))
-2-:	790	if (start_i)
-3-:	792	if (process_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	798	if ((!rst_ni))
-2-:	800	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_o))
-3-:	802	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	680	case (msg_strb)

Branches:

-1-	Status	Tests
7'b0000000	Covered	T1,T2,T3
7'b0000001	Covered	T1,T3,T17
7'b0000011	Covered	T1,T3,T17
7'b0000111	Covered	T1,T3,T17
7'b0001111	Covered	T1,T3,T17
7'b0011111	Covered	T1,T3,T17
7'b0111111	Covered	T1,T3,T17
7'b1111111	Covered	T1,T3,T17
default	Not Covered

---

Assert Coverage for Instance : tb.dut.u_sha3.u_pad

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	4	4	100.00	4	100.00
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AbsorbedPulse_A	2147483647	345305	0	0
AlwaysPartialMsgBuf_M	2147483647	196020	0	0
CompleteBlockWhenProcess_A	2147483647	333255	0	0
DoneCondition_M	2147483647	345300	0	0
DonePulse_A	2147483647	345300	0	0
KeccakAddrInRange_A	2147483647	52876543	0	0
KeccakRunPulse_A	2147483647	3064838	0	0
MessageCondition_M	2147483647	48194520	0	0
ModeStableDuringOp_M	2147483647	32619	0	0
MsgReadyCondition_A	2147483647	2144396470	0	0
MsgWidthidth_A	1022	1022	0	0
NoPartialMsgFifo_M	2147483647	47998500	0	0
Pad01NotAttheEndOfBlock_A	2147483647	334655	0	0
PartialEndOfMsg_M	2147483647	196020	0	0
PrefixLessThanBlock_A	1022	1022	0	0
ProcessCondition_M	2147483647	345310	0	0
ProcessPulse_A	2147483647	345310	0	0
StartCondition_M	2147483647	345355	0	0
StartProcessDoneMutex_a	2147483647	2147483647	0	0
StartPulse_A	2147483647	345355	0	0
StrengthStableDuringOp_M	2147483647	39578	0	0
u_state_regs_A	2147483647	2147483647	0	0

AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345305	0	0
T1	161611	174	0	0
T2	167210	19	0	0
T3	191537	374	0	0
T6	0	84	0	0
T17	149490	2265	0	0
T35	25641	9	0	0
T36	19708	9	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	246	0	0
T40	2138	0	0	0
T42	0	9	0	0
T56	0	9	0	0

AlwaysPartialMsgBuf_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	196020	0	0
T1	161611	133	0	0
T2	167210	0	0	0
T3	191537	326	0	0
T6	0	76	0	0
T17	149490	890	0	0
T22	0	96	0	0
T35	25641	9	0	0
T36	19708	9	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	214	0	0
T40	2138	0	0	0
T42	0	9	0	0
T56	0	9	0	0

CompleteBlockWhenProcess_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	333255	0	0
T1	161611	159	0	0
T2	167210	19	0	0
T3	191537	356	0	0
T6	0	78	0	0
T17	149490	2211	0	0
T35	25641	9	0	0
T36	19708	9	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	219	0	0
T40	2138	0	0	0
T42	0	9	0	0
T56	0	9	0	0

DoneCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345300	0	0
T1	161611	174	0	0
T2	167210	19	0	0
T3	191537	374	0	0
T6	0	84	0	0
T17	149490	2265	0	0
T35	25641	9	0	0
T36	19708	9	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	246	0	0
T40	2138	0	0	0
T42	0	9	0	0
T56	0	9	0	0

DonePulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345300	0	0
T1	161611	174	0	0
T2	167210	19	0	0
T3	191537	374	0	0
T6	0	84	0	0
T17	149490	2265	0	0
T35	25641	9	0	0
T36	19708	9	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	246	0	0
T40	2138	0	0	0
T42	0	9	0	0
T56	0	9	0	0

KeccakAddrInRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	52876543	0	0
T1	161611	16677	0	0
T2	167210	969	0	0
T3	191537	93942	0	0
T6	0	7118	0	0
T17	149490	220643	0	0
T35	25641	607	0	0
T36	19708	607	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	48843	0	0
T40	2138	0	0	0
T42	0	607	0	0
T56	0	607	0	0

KeccakRunPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3064838	0	0
T1	161611	911	0	0
T2	167210	57	0	0
T3	191537	5526	0	0
T6	0	390	0	0
T17	149490	12979	0	0
T35	25641	31	0	0
T36	19708	31	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	5427	0	0
T40	2138	0	0	0
T42	0	31	0	0
T56	0	31	0	0

MessageCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48194520	0	0
T1	161611	12901	0	0
T2	167210	323	0	0
T3	191537	90674	0	0
T6	0	5367	0	0
T17	149490	195716	0	0
T35	25641	286	0	0
T36	19708	286	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	47746	0	0
T40	2138	0	0	0
T42	0	286	0	0
T56	0	286	0	0

ModeStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	32619	0	0
T1	161611	180	0	0
T2	167210	35	0	0
T3	191537	0	0	0
T6	0	98	0	0
T17	149490	1	0	0
T22	0	45	0	0
T35	25641	1	0	0
T36	19708	1	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	0	0	0
T40	2138	6	0	0
T42	0	1	0	0
T56	0	1	0	0

MsgReadyCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2144396470	0	0
T1	161611	837212	0	0
T2	167210	156902	0	0
T3	191537	117494	0	0
T6	0	471125	0	0
T17	149490	117006	0	0
T35	25641	1006	0	0
T36	19708	5769	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	414372	0	0
T40	2138	0	0	0
T42	0	7248	0	0
T56	0	6932	0	0

MsgWidthidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T17	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0

NoPartialMsgFifo_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	47998500	0	0
T1	161611	12768	0	0
T2	167210	323	0	0
T3	191537	90348	0	0
T6	0	5291	0	0
T17	149490	194826	0	0
T35	25641	277	0	0
T36	19708	277	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	47532	0	0
T40	2138	0	0	0
T42	0	277	0	0
T56	0	277	0	0

Pad01NotAttheEndOfBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	334655	0	0
T1	161611	162	0	0
T2	167210	19	0	0
T3	191537	358	0	0
T6	0	78	0	0
T17	149490	2217	0	0
T35	25641	9	0	0
T36	19708	9	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	222	0	0
T40	2138	0	0	0
T42	0	9	0	0
T56	0	9	0	0

PartialEndOfMsg_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	196020	0	0
T1	161611	133	0	0
T2	167210	0	0	0
T3	191537	326	0	0
T6	0	76	0	0
T17	149490	890	0	0
T22	0	96	0	0
T35	25641	9	0	0
T36	19708	9	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	214	0	0
T40	2138	0	0	0
T42	0	9	0	0
T56	0	9	0	0

PrefixLessThanBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T17	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0

ProcessCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345310	0	0
T1	161611	174	0	0
T2	167210	19	0	0
T3	191537	374	0	0
T6	0	84	0	0
T17	149490	2265	0	0
T35	25641	9	0	0
T36	19708	9	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	246	0	0
T40	2138	0	0	0
T42	0	9	0	0
T56	0	9	0	0

ProcessPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345310	0	0
T1	161611	174	0	0
T2	167210	19	0	0
T3	191537	374	0	0
T6	0	84	0	0
T17	149490	2265	0	0
T35	25641	9	0	0
T36	19708	9	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	246	0	0
T40	2138	0	0	0
T42	0	9	0	0
T56	0	9	0	0

StartCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345355	0	0
T1	161611	174	0	0
T2	167210	19	0	0
T3	191537	374	0	0
T6	0	84	0	0
T17	149490	2265	0	0
T35	25641	9	0	0
T36	19708	9	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	246	0	0
T40	2138	0	0	0
T42	0	9	0	0
T56	0	9	0	0

StartProcessDoneMutex_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	161611	161603	0	0
T2	167210	167127	0	0
T3	191537	191530	0	0
T17	149490	149489	0	0
T35	25641	25589	0	0
T36	19708	19633	0	0
T37	1172	1104	0	0
T38	1957	1865	0	0
T39	490351	490344	0	0
T40	2138	2039	0	0

StartPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345355	0	0
T1	161611	174	0	0
T2	167210	19	0	0
T3	191537	374	0	0
T6	0	84	0	0
T17	149490	2265	0	0
T35	25641	9	0	0
T36	19708	9	0	0
T37	1172	0	0	0
T38	1957	0	0	0
T39	490351	246	0	0
T40	2138	0	0	0
T42	0	9	0	0
T56	0	9	0	0

StrengthStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39578	0	0
T1	161611	172	0	0
T2	167210	40	0	0
T3	191537	2	0	0
T17	149490	2	0	0
T35	25641	2	0	0
T36	19708	2	0	0
T37	1172	1	0	0
T38	1957	1	0	0
T39	490351	2	0	0
T40	2138	8	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	161611	161603	0	0
T2	167210	167127	0	0
T3	191537	191530	0	0
T17	149490	149489	0	0
T35	25641	25589	0	0
T36	19708	19633	0	0
T37	1172	1104	0	0
T38	1957	1865	0	0
T39	490351	490344	0	0
T40	2138	2039	0	0

---

Cover Directives for Properties: Details

Name	Attempts	Matches	Incomplete
StComplete_C	2147483647	33520287	0
StMessageFeed_C	2147483647	2147424573	0
StPadSendMsg_C	2147483647	3842053	0
StPad_C	2147483647	334655	0

StComplete_C

Name	Attempts	Matches	Incomplete
Total	2147483647	33520287	0
T1	161611	16878	0
T2	167210	1843	0
T3	191537	36278	0
T6	0	8148	0
T17	149490	219755	0
T35	25641	873	0
T36	19708	873	0
T37	1172	0	0
T38	1957	0	0
T39	490351	23862	0
T40	2138	0	0
T42	0	873	0
T56	0	873	0

StMessageFeed_C

Name	Attempts	Matches	Incomplete
Total	2147483647	2147424573	0
T1	161611	838005	0
T2	167210	156940	0
T3	191537	118046	0
T6	0	471462	0
T17	149490	117136	0
T35	25641	1028	0
T36	19708	5791	0
T37	1172	0	0
T38	1957	0	0
T39	490351	414915	0
T40	2138	0	0
T42	0	7270	0
T56	0	6954	0

StPadSendMsg_C

Name	Attempts	Matches	Incomplete
Total	2147483647	3842053	0
T1	161611	1557	0
T2	167210	304	0
T3	191537	3220	0
T6	0	758	0
T17	149490	23552	0
T35	25641	144	0
T36	19708	144	0
T37	1172	0	0
T38	1957	0	0
T39	490351	1065	0
T40	2138	0	0
T42	0	144	0
T56	0	144	0

StPad_C

Name	Attempts	Matches	Incomplete
Total	2147483647	334655	0
T1	161611	162	0
T2	167210	19	0
T3	191537	358	0
T6	0	78	0
T17	149490	2217	0
T35	25641	9	0
T36	19708	9	0
T37	1172	0	0
T38	1957	0	0
T39	490351	222	0
T40	2138	0	0
T42	0	9	0
T56	0	9	0