Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	153520	0	0
entropy_period_rd_A	2147483647	1594	0	0
intr_enable_rd_A	2147483647	2705	0	0
prefix_0_rd_A	2147483647	1524	0	0
prefix_10_rd_A	2147483647	1429	0	0
prefix_1_rd_A	2147483647	1348	0	0
prefix_2_rd_A	2147483647	1377	0	0
prefix_3_rd_A	2147483647	1378	0	0
prefix_4_rd_A	2147483647	1463	0	0
prefix_5_rd_A	2147483647	1643	0	0
prefix_6_rd_A	2147483647	1349	0	0
prefix_7_rd_A	2147483647	1431	0	0
prefix_8_rd_A	2147483647	1472	0	0
prefix_9_rd_A	2147483647	1468	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	153520	0	0
T13	3322	0	0	0
T15	128235	19419	0	0
T61	0	31718	0	0
T62	0	71983	0	0
T70	526704	0	0	0
T122	0	2	0	0
T129	0	26856	0	0
T130	0	1	0	0
T131	0	5	0	0
T132	0	139	0	0
T133	0	4	0	0
T135	594129	0	0	0
T136	537201	0	0	0
T137	605862	0	0	0
T138	115200	0	0	0
T139	290048	0	0	0
T140	220334	0	0	0
T141	218898	0	0	0
T142	0	2	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1594	0	0
T95	5808	1	0	0
T96	5105	16	0	0
T99	12483	84	0	0
T102	4016	18	0	0
T122	28945	133	0	0
T130	4072	1	0	0
T133	4515	8	0	0
T142	4427	6	0	0
T160	10986	9	0	0
T161	1986	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2705	0	0
T99	12483	83	0	0
T122	28945	198	0	0
T126	1105	15	0	0
T130	4072	9	0	0
T160	10986	20	0	0
T161	1986	10	0	0
T162	1356	23	0	0
T163	1542	1	0	0
T164	1052	10	0	0
T165	1788	21	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1524	0	0
T95	5808	8	0	0
T96	5105	26	0	0
T99	12483	57	0	0
T102	4016	4	0	0
T122	28945	71	0	0
T130	4072	8	0	0
T133	4515	4	0	0
T142	4427	11	0	0
T160	10986	49	0	0
T166	22468	107	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1429	0	0
T95	5808	8	0	0
T96	5105	12	0	0
T99	12483	66	0	0
T102	4016	13	0	0
T122	28945	74	0	0
T130	4072	12	0	0
T133	4515	4	0	0
T142	4427	9	0	0
T160	10986	31	0	0
T161	1986	2	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1348	0	0
T95	5808	10	0	0
T96	5105	19	0	0
T99	12483	51	0	0
T102	4016	6	0	0
T122	28945	57	0	0
T130	4072	5	0	0
T133	4515	6	0	0
T142	4427	14	0	0
T160	10986	25	0	0
T166	22468	87	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1377	0	0
T95	5808	1	0	0
T99	12483	54	0	0
T102	4016	25	0	0
T122	28945	59	0	0
T130	4072	3	0	0
T133	4515	8	0	0
T142	4427	6	0	0
T160	10986	37	0	0
T161	1986	8	0	0
T163	1542	2	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1378	0	0
T95	5808	2	0	0
T96	5105	14	0	0
T99	12483	66	0	0
T102	4016	4	0	0
T122	28945	86	0	0
T130	4072	3	0	0
T133	4515	4	0	0
T142	4427	4	0	0
T160	10986	51	0	0
T163	1542	3	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1463	0	0
T95	5808	5	0	0
T96	5105	4	0	0
T99	12483	52	0	0
T102	4016	5	0	0
T122	28945	69	0	0
T130	4072	7	0	0
T133	4515	7	0	0
T142	4427	13	0	0
T160	10986	18	0	0
T163	1542	2	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1643	0	0
T95	5808	5	0	0
T96	5105	13	0	0
T99	12483	66	0	0
T102	4016	16	0	0
T122	28945	108	0	0
T130	4072	7	0	0
T133	4515	8	0	0
T142	4427	9	0	0
T160	10986	22	0	0
T163	1542	6	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1349	0	0
T95	5808	5	0	0
T96	5105	5	0	0
T99	12483	35	0	0
T102	4016	10	0	0
T104	4460	11	0	0
T122	28945	55	0	0
T133	4515	6	0	0
T142	4427	3	0	0
T160	10986	22	0	0
T166	22468	73	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1431	0	0
T95	5808	4	0	0
T96	5105	10	0	0
T99	12483	44	0	0
T102	4016	12	0	0
T122	28945	77	0	0
T133	4515	6	0	0
T142	4427	4	0	0
T160	10986	12	0	0
T163	1542	4	0	0
T166	22468	81	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1472	0	0
T95	5808	6	0	0
T99	12483	56	0	0
T102	4016	2	0	0
T122	28945	86	0	0
T130	4072	6	0	0
T133	4515	4	0	0
T142	4427	11	0	0
T160	10986	34	0	0
T161	1986	4	0	0
T163	1542	9	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1468	0	0
T96	5105	6	0	0
T99	12483	53	0	0
T102	4016	12	0	0
T104	4460	10	0	0
T122	28945	100	0	0
T133	4515	13	0	0
T142	4427	11	0	0
T160	10986	29	0	0
T163	1542	2	0	0
T166	22468	73	0	0