Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
181076 |
1 |
|
|
T7 |
1976 |
|
T8 |
1754 |
|
T12 |
183 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
96175 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
62197 |
1 |
|
|
T7 |
45 |
|
T8 |
45 |
|
T12 |
181 |
seven_bytes |
3298 |
1 |
|
|
T7 |
62 |
|
T8 |
45 |
|
T17 |
22 |
six_bytes |
3207 |
1 |
|
|
T7 |
44 |
|
T8 |
52 |
|
T17 |
22 |
five_bytes |
3124 |
1 |
|
|
T7 |
61 |
|
T8 |
38 |
|
T17 |
28 |
four_bytes |
3304 |
1 |
|
|
T7 |
52 |
|
T8 |
52 |
|
T17 |
23 |
three_bytes |
3320 |
1 |
|
|
T7 |
55 |
|
T8 |
52 |
|
T17 |
37 |
two_bytes |
3317 |
1 |
|
|
T7 |
54 |
|
T8 |
49 |
|
T17 |
30 |
one_byte |
3134 |
1 |
|
|
T7 |
68 |
|
T8 |
38 |
|
T17 |
33 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
177674 |
1 |
|
|
T7 |
1958 |
|
T8 |
1732 |
|
T12 |
179 |
auto[1] |
3402 |
1 |
|
|
T7 |
18 |
|
T8 |
22 |
|
T12 |
4 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
181076 |
1 |
|
|
T7 |
1976 |
|
T8 |
1754 |
|
T12 |
183 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
181065 |
1 |
|
|
T7 |
1976 |
|
T8 |
1753 |
|
T12 |
183 |
auto[1] |
11 |
1 |
|
|
T8 |
1 |
|
T14 |
1 |
|
T81 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1160 |
1 |
|
|
T7 |
4 |
|
T8 |
1 |
|
T12 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3402 |
1 |
|
|
T7 |
18 |
|
T8 |
22 |
|
T12 |
4 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
179488 |
1 |
|
|
T3 |
127 |
|
T7 |
2186 |
|
T8 |
380 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
92091 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
65217 |
1 |
|
|
T3 |
125 |
|
T7 |
54 |
|
T8 |
10 |
seven_bytes |
3120 |
1 |
|
|
T7 |
55 |
|
T8 |
4 |
|
T17 |
32 |
six_bytes |
3222 |
1 |
|
|
T7 |
54 |
|
T8 |
8 |
|
T17 |
49 |
five_bytes |
3167 |
1 |
|
|
T7 |
57 |
|
T8 |
5 |
|
T17 |
39 |
four_bytes |
3147 |
1 |
|
|
T7 |
63 |
|
T8 |
16 |
|
T17 |
36 |
three_bytes |
3081 |
1 |
|
|
T7 |
63 |
|
T8 |
15 |
|
T17 |
39 |
two_bytes |
3244 |
1 |
|
|
T7 |
78 |
|
T8 |
13 |
|
T17 |
48 |
one_byte |
3199 |
1 |
|
|
T7 |
53 |
|
T8 |
8 |
|
T17 |
49 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176041 |
1 |
|
|
T3 |
123 |
|
T7 |
2164 |
|
T8 |
370 |
auto[1] |
3447 |
1 |
|
|
T3 |
4 |
|
T7 |
22 |
|
T8 |
10 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
179488 |
1 |
|
|
T3 |
127 |
|
T7 |
2186 |
|
T8 |
380 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
179471 |
1 |
|
|
T3 |
127 |
|
T7 |
2186 |
|
T8 |
380 |
auto[1] |
17 |
1 |
|
|
T42 |
1 |
|
T185 |
1 |
|
T94 |
2 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1189 |
1 |
|
|
T3 |
2 |
|
T7 |
7 |
|
T12 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3447 |
1 |
|
|
T3 |
4 |
|
T7 |
22 |
|
T8 |
10 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349278 |
1 |
|
|
T7 |
2042 |
|
T8 |
2481 |
|
T12 |
198 |
auto[1] |
526 |
1 |
|
|
T9 |
67 |
|
T10 |
87 |
|
T11 |
68 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
178665 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
129080 |
1 |
|
|
T7 |
48 |
|
T8 |
78 |
|
T12 |
194 |
seven_bytes |
6113 |
1 |
|
|
T7 |
58 |
|
T8 |
60 |
|
T17 |
85 |
six_bytes |
6037 |
1 |
|
|
T7 |
67 |
|
T8 |
68 |
|
T17 |
78 |
five_bytes |
6064 |
1 |
|
|
T7 |
57 |
|
T8 |
71 |
|
T17 |
79 |
four_bytes |
5918 |
1 |
|
|
T7 |
56 |
|
T8 |
76 |
|
T17 |
84 |
three_bytes |
6028 |
1 |
|
|
T7 |
49 |
|
T8 |
69 |
|
T17 |
91 |
two_bytes |
5879 |
1 |
|
|
T7 |
52 |
|
T8 |
64 |
|
T17 |
80 |
one_byte |
6020 |
1 |
|
|
T7 |
51 |
|
T8 |
69 |
|
T17 |
71 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
343136 |
1 |
|
|
T7 |
2018 |
|
T8 |
2449 |
|
T12 |
190 |
auto[1] |
6668 |
1 |
|
|
T7 |
24 |
|
T8 |
32 |
|
T12 |
8 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349804 |
1 |
|
|
T7 |
2042 |
|
T8 |
2481 |
|
T12 |
198 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349779 |
1 |
|
|
T7 |
2042 |
|
T8 |
2481 |
|
T12 |
198 |
auto[1] |
25 |
1 |
|
|
T42 |
3 |
|
T17 |
1 |
|
T115 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2326 |
1 |
|
|
T7 |
3 |
|
T8 |
8 |
|
T12 |
4 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6668 |
1 |
|
|
T7 |
24 |
|
T8 |
32 |
|
T12 |
8 |