Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	257803480	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

182570674

1

T1

792500

T2

324159

T3

1097

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	228608477	1			T1	102028		T2	424351		T3	1144
values[0x0]	101769106	1			T1	450312		T2	202535		T3	453
values[0x1]	109996571	1			T1	488751		T2	219066		T3	480

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	200365935	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

240008219

1

T1

105032

T2

437809

T3

1325

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1265657	1			T2	3270		T3	16		T32	30
valid_sources[0x01]	1717708	1			T2	3322		T3	28		T32	22
valid_sources[0x02]	1273538	1			T2	3289		T3	2		T32	24
valid_sources[0x03]	3907487	1			T2	3413		T3	4		T32	34
valid_sources[0x04]	1700303	1			T2	3374		T3	3		T32	6
valid_sources[0x05]	1397835	1			T2	3349		T3	4		T32	23
valid_sources[0x06]	1266308	1			T2	3242		T3	10		T32	8
valid_sources[0x07]	3613974	1			T2	3374		T3	17		T32	16
valid_sources[0x08]	3253513	1			T2	3281		T3	9		T32	22
valid_sources[0x09]	4674856	1			T2	3366		T32	23		T7	266
valid_sources[0x0a]	5605794	1			T2	3234		T3	9		T32	2
valid_sources[0x0b]	1397612	1			T2	3310		T3	1		T32	9
valid_sources[0x0c]	1415323	1			T2	3344		T32	53		T7	196
valid_sources[0x0d]	1274016	1			T2	3296		T3	4		T32	14
valid_sources[0x0e]	1271400	1			T2	3345		T3	5		T32	28
valid_sources[0x0f]	1263500	1			T2	3243		T3	6		T32	5
valid_sources[0x10]	1271614	1			T2	3340		T3	6		T32	3
valid_sources[0x11]	2177304	1			T2	3309		T3	32		T32	7
valid_sources[0x12]	1273490	1			T2	3358		T3	1		T32	21
valid_sources[0x13]	1265886	1			T2	3251		T3	4		T32	21
valid_sources[0x14]	1265531	1			T2	3306		T32	27		T7	249
valid_sources[0x15]	1502290	1			T2	3384		T3	3		T32	25
valid_sources[0x16]	2261560	1			T2	3257		T3	15		T32	43
valid_sources[0x17]	1989350	1			T2	3266		T3	5		T32	8
valid_sources[0x18]	1270118	1			T2	3280		T3	3		T32	40
valid_sources[0x19]	2173327	1			T2	3294		T3	4		T32	8
valid_sources[0x1a]	3217109	1			T2	3338		T3	12		T32	16
valid_sources[0x1b]	3237145	1			T1	195934		T2	3239		T3	26
valid_sources[0x1c]	1398627	1			T2	3234		T3	2		T32	48
valid_sources[0x1d]	1264603	1			T2	3284		T3	1		T32	36
valid_sources[0x1e]	3243281	1			T2	3281		T3	12		T32	7
valid_sources[0x1f]	3776796	1			T2	3392		T3	7		T32	33
valid_sources[0x20]	1263417	1			T2	3318		T3	5		T32	17
valid_sources[0x21]	1867815	1			T2	3285		T3	4		T32	28
valid_sources[0x22]	1267797	1			T2	3300		T3	7		T32	42
valid_sources[0x23]	1267815	1			T2	3339		T3	13		T32	36
valid_sources[0x24]	1278965	1			T2	3326		T3	2		T32	19
valid_sources[0x25]	4517204	1			T2	3226		T3	9		T32	19
valid_sources[0x26]	1266688	1			T2	3269		T3	12		T32	17
valid_sources[0x27]	1267993	1			T2	3281		T3	4		T32	27
valid_sources[0x28]	1766044	1			T2	3298		T3	11		T32	39
valid_sources[0x29]	1730659	1			T2	3442		T3	16		T32	17
valid_sources[0x2a]	1370595	1			T2	3324		T3	9		T32	29
valid_sources[0x2b]	1269526	1			T2	3369		T3	16		T32	31
valid_sources[0x2c]	1299937	1			T2	3196		T3	6		T32	8
valid_sources[0x2d]	1272265	1			T2	3292		T32	23		T7	255
valid_sources[0x2e]	1267761	1			T2	3434		T3	1		T7	263
valid_sources[0x2f]	1273334	1			T2	3268		T3	2		T32	19
valid_sources[0x30]	1397344	1			T2	3366		T3	2		T32	10
valid_sources[0x31]	2145928	1			T2	3286		T3	19		T32	18
valid_sources[0x32]	1297012	1			T2	3421		T3	19		T32	10
valid_sources[0x33]	1271676	1			T2	3345		T32	20		T7	247
valid_sources[0x34]	1394234	1			T2	3303		T3	17		T32	26
valid_sources[0x35]	3282983	1			T2	3307		T3	8		T32	10
valid_sources[0x36]	3649503	1			T2	3320		T3	24		T32	56
valid_sources[0x37]	1261168	1			T2	3208		T3	13		T32	17
valid_sources[0x38]	1403707	1			T2	3354		T3	4		T32	8
valid_sources[0x39]	1289886	1			T2	3175		T3	6		T32	29
valid_sources[0x3a]	1264953	1			T2	3279		T3	7		T32	13
valid_sources[0x3b]	1271954	1			T2	3388		T32	5		T7	237
valid_sources[0x3c]	1265161	1			T2	3350		T3	14		T32	38
valid_sources[0x3d]	1271422	1			T2	3266		T3	8		T32	29
valid_sources[0x3e]	1273080	1			T2	3295		T3	15		T32	14
valid_sources[0x3f]	1267464	1			T2	3307		T3	5		T32	3
valid_sources[0x40]	3220723	1			T2	3279		T3	19		T32	3
valid_sources[0x41]	1718515	1			T2	3296		T3	3		T32	9
valid_sources[0x42]	1289251	1			T2	3354		T3	11		T32	43
valid_sources[0x43]	1336407	1			T2	3272		T3	7		T32	8
valid_sources[0x44]	2024546	1			T2	3257		T3	7		T32	35
valid_sources[0x45]	1263910	1			T2	3318		T3	8		T32	17
valid_sources[0x46]	1262329	1			T2	3322		T3	5		T32	32
valid_sources[0x47]	1270432	1			T2	3307		T3	5		T32	33
valid_sources[0x48]	1269933	1			T2	3361		T3	5		T32	18
valid_sources[0x49]	1398877	1			T2	3266		T3	6		T32	9
valid_sources[0x4a]	2118914	1			T2	3362		T3	2		T32	38
valid_sources[0x4b]	2231743	1			T2	3299		T3	2		T32	30
valid_sources[0x4c]	2129909	1			T2	3385		T3	5		T32	9
valid_sources[0x4d]	1265545	1			T2	3255		T3	8		T32	45
valid_sources[0x4e]	1267868	1			T2	3300		T3	6		T32	21
valid_sources[0x4f]	1325803	1			T2	3234		T3	21		T32	44
valid_sources[0x50]	1336862	1			T2	3239		T3	6		T32	45
valid_sources[0x51]	1383873	1			T2	3279		T3	36		T32	37
valid_sources[0x52]	1275399	1			T2	3244		T3	1		T32	22
valid_sources[0x53]	2144982	1			T2	3332		T3	13		T32	15
valid_sources[0x54]	3870591	1			T2	3314		T3	1		T32	9
valid_sources[0x55]	1274128	1			T2	3231		T32	27		T7	247
valid_sources[0x56]	4513093	1			T2	3327		T3	16		T32	32
valid_sources[0x57]	2120457	1			T2	3299		T3	1		T32	14
valid_sources[0x58]	1265886	1			T2	3311		T3	3		T32	15
valid_sources[0x59]	2203873	1			T2	3276		T32	57		T7	271
valid_sources[0x5a]	1265026	1			T2	3313		T32	18		T7	250
valid_sources[0x5b]	1312490	1			T2	3284		T3	2		T32	16
valid_sources[0x5c]	2198293	1			T2	3348		T3	8		T32	28
valid_sources[0x5d]	1269479	1			T2	3305		T3	2		T32	18
valid_sources[0x5e]	1272049	1			T2	3253		T3	1		T32	34
valid_sources[0x5f]	3576151	1			T2	3307		T32	46		T7	290
valid_sources[0x60]	1389090	1			T2	3329		T32	41		T7	273
valid_sources[0x61]	1265362	1			T2	3290		T3	8		T32	13
valid_sources[0x62]	2231864	1			T2	3251		T3	7		T32	9
valid_sources[0x63]	1267104	1			T2	3257		T3	6		T32	14
valid_sources[0x64]	1263798	1			T2	3199		T3	4		T32	50
valid_sources[0x65]	1454009	1			T2	3322		T3	16		T32	17
valid_sources[0x66]	1269995	1			T2	3376		T3	10		T32	11
valid_sources[0x67]	1439344	1			T2	3253		T3	7		T32	49
valid_sources[0x68]	1345218	1			T2	3180		T3	9		T32	17
valid_sources[0x69]	1899403	1			T2	3316		T3	1		T32	72
valid_sources[0x6a]	1265655	1			T2	3340		T3	10		T32	30
valid_sources[0x6b]	2460894	1			T2	3406		T3	14		T32	29
valid_sources[0x6c]	2103412	1			T2	3272		T3	1		T32	21
valid_sources[0x6d]	1266633	1			T2	3309		T3	34		T32	10
valid_sources[0x6e]	1377050	1			T2	3365		T3	11		T32	7
valid_sources[0x6f]	1530983	1			T2	3361		T3	8		T32	3
valid_sources[0x70]	1268215	1			T2	3318		T3	38		T32	26
valid_sources[0x71]	1272559	1			T2	3251		T3	2		T32	24
valid_sources[0x72]	1270859	1			T2	3325		T3	6		T32	50
valid_sources[0x73]	1363100	1			T2	3133		T3	6		T32	24
valid_sources[0x74]	1270966	1			T2	3256		T3	1		T32	12
valid_sources[0x75]	1271986	1			T2	3338		T32	15		T7	277
valid_sources[0x76]	1725871	1			T2	3229		T3	5		T32	18
valid_sources[0x77]	1274845	1			T2	3369		T3	13		T32	11
valid_sources[0x78]	1271486	1			T2	3306		T3	5		T32	15
valid_sources[0x79]	3840168	1			T2	3336		T3	1		T32	25
valid_sources[0x7a]	3035536	1			T2	3190		T32	15		T7	260
valid_sources[0x7b]	1272801	1			T2	3370		T3	21		T32	18
valid_sources[0x7c]	1644652	1			T2	3302		T3	22		T32	1
valid_sources[0x7d]	2111700	1			T2	3286		T3	11		T32	7
valid_sources[0x7e]	4093408	1			T2	3330		T3	2		T32	44
valid_sources[0x7f]	1345250	1			T2	3309		T3	34		T32	40
valid_sources[0x80]	4021195	1			T2	3302		T3	12		T32	30

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

70793956

1

T1

325161

T2

110955

T3

563

values[0x0]

all_enables

biggest_size

60074897

1

T1

253270

T2

115448

T3

299

values[0x1]

all_enables

biggest_size

51701821

1

T1

214069

T2

97756

T3

235