Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

258575281

1

T1

116684

T2

521793

T3

980

full_word

182619773

1

T1

792500

T2

324159

T3

1097

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	441194804	1			T1	195934		T2	845952		T3	2077
auto[TlIntgErrCmd]	90	1			T146	5		T147	5		T148	6
auto[TlIntgErrData]	73	1			T146	3		T147	2		T148	4
auto[TlIntgErrBoth]	87	1			T146	2		T147	3		T187	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

228759686

1

T1

102028

T2

424351

T3

1144

auto[1]

212435368

1

T1

939063

T2

421601

T3

933

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	157953121	1			T1	695121		T2	313396		T3	581
auto[TlIntgErrNone]	partial	auto[1]	100621930	1			T1	471724		T2	208397		T3	399
auto[TlIntgErrNone]	full_word	auto[0]	70806455	1			T1	325161		T2	110955		T3	563
auto[TlIntgErrNone]	full_word	auto[1]	111813298	1			T1	467339		T2	213204		T3	534
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T146	1		T147	3		T148	2
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T146	2		T147	2		T148	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T146	1		T193	1		T194	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T146	1		T187	1		T193	1
auto[TlIntgErrData]	partial	auto[0]	30	1			T146	1		T147	1		T148	2
auto[TlIntgErrData]	partial	auto[1]	37	1			T146	2		T148	2		T188	6
auto[TlIntgErrData]	full_word	auto[0]	5	1			T147	1		T187	1		T188	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T191	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T146	1		T147	3		T188	3
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T187	3		T188	3		T193	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T195	1		T196	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T146	1		T197	1		T192	1