Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	181789	0	0
entropy_period_rd_A	2147483647	1795	0	0
intr_enable_rd_A	2147483647	2383	0	0
prefix_0_rd_A	2147483647	1632	0	0
prefix_10_rd_A	2147483647	1591	0	0
prefix_1_rd_A	2147483647	1615	0	0
prefix_2_rd_A	2147483647	1634	0	0
prefix_3_rd_A	2147483647	1548	0	0
prefix_4_rd_A	2147483647	1555	0	0
prefix_5_rd_A	2147483647	1625	0	0
prefix_6_rd_A	2147483647	1588	0	0
prefix_7_rd_A	2147483647	1607	0	0
prefix_8_rd_A	2147483647	1687	0	0
prefix_9_rd_A	2147483647	1548	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	181789	0	0
T11	500298	0	0	0
T24	0	88118	0	0
T63	302446	24040	0	0
T78	0	66300	0	0
T95	692577	0	0	0
T146	0	2	0	0
T147	0	2	0	0
T152	0	8	0	0
T153	0	5	0	0
T154	0	352	0	0
T155	0	6	0	0
T156	0	117	0	0
T159	281398	0	0	0
T160	394332	0	0	0
T161	44169	0	0	0
T162	331062	0	0	0
T163	151020	0	0	0
T164	207113	0	0	0
T165	122799	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1795	0	0
T11	500298	0	0	0
T63	302446	73	0	0
T95	692577	0	0	0
T100	0	13	0	0
T101	0	81	0	0
T111	0	44	0	0
T146	0	61	0	0
T152	0	9	0	0
T159	281398	0	0	0
T160	394332	0	0	0
T161	44169	0	0	0
T162	331062	0	0	0
T163	151020	0	0	0
T164	207113	0	0	0
T165	122799	0	0	0
T175	0	3	0	0
T176	0	39	0	0
T177	0	3	0	0
T178	0	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2383	0	0
T11	500298	0	0	0
T63	302446	44	0	0
T95	692577	0	0	0
T100	0	27	0	0
T111	0	46	0	0
T146	0	95	0	0
T152	0	3	0	0
T159	281398	0	0	0
T160	394332	0	0	0
T161	44169	0	0	0
T162	331062	0	0	0
T163	151020	0	0	0
T164	207113	0	0	0
T165	122799	0	0	0
T175	0	12	0	0
T176	0	61	0	0
T177	0	7	0	0
T178	0	5	0	0
T179	0	18	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1632	0	0
T11	500298	0	0	0
T63	302446	58	0	0
T95	692577	0	0	0
T100	0	11	0	0
T101	0	41	0	0
T111	0	26	0	0
T146	0	53	0	0
T152	0	11	0	0
T157	0	9	0	0
T159	281398	0	0	0
T160	394332	0	0	0
T161	44169	0	0	0
T162	331062	0	0	0
T163	151020	0	0	0
T164	207113	0	0	0
T165	122799	0	0	0
T176	0	55	0	0
T179	0	11	0	0
T180	0	3	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1591	0	0
T11	500298	0	0	0
T63	302446	76	0	0
T95	692577	0	0	0
T100	0	5	0	0
T111	0	32	0	0
T146	0	39	0	0
T152	0	8	0	0
T159	281398	0	0	0
T160	394332	0	0	0
T161	44169	0	0	0
T162	331062	0	0	0
T163	151020	0	0	0
T164	207113	0	0	0
T165	122799	0	0	0
T175	0	6	0	0
T176	0	53	0	0
T177	0	2	0	0
T178	0	7	0	0
T179	0	38	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1615	0	0
T11	500298	0	0	0
T63	302446	113	0	0
T95	692577	0	0	0
T100	0	11	0	0
T101	0	38	0	0
T111	0	17	0	0
T146	0	39	0	0
T152	0	2	0	0
T157	0	11	0	0
T159	281398	0	0	0
T160	394332	0	0	0
T161	44169	0	0	0
T162	331062	0	0	0
T163	151020	0	0	0
T164	207113	0	0	0
T165	122799	0	0	0
T176	0	23	0	0
T178	0	3	0	0
T179	0	19	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1634	0	0
T11	500298	0	0	0
T63	302446	67	0	0
T95	692577	0	0	0
T100	0	20	0	0
T111	0	41	0	0
T146	0	51	0	0
T152	0	12	0	0
T159	281398	0	0	0
T160	394332	0	0	0
T161	44169	0	0	0
T162	331062	0	0	0
T163	151020	0	0	0
T164	207113	0	0	0
T165	122799	0	0	0
T175	0	2	0	0
T176	0	63	0	0
T177	0	3	0	0
T178	0	7	0	0
T179	0	30	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1548	0	0
T11	500298	0	0	0
T63	302446	107	0	0
T95	692577	0	0	0
T100	0	12	0	0
T101	0	52	0	0
T111	0	23	0	0
T146	0	52	0	0
T152	0	2	0	0
T159	281398	0	0	0
T160	394332	0	0	0
T161	44169	0	0	0
T162	331062	0	0	0
T163	151020	0	0	0
T164	207113	0	0	0
T165	122799	0	0	0
T175	0	2	0	0
T176	0	46	0	0
T177	0	2	0	0
T179	0	16	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1555	0	0
T11	500298	0	0	0
T63	302446	50	0	0
T95	692577	0	0	0
T100	0	23	0	0
T101	0	53	0	0
T111	0	29	0	0
T146	0	40	0	0
T152	0	14	0	0
T159	281398	0	0	0
T160	394332	0	0	0
T161	44169	0	0	0
T162	331062	0	0	0
T163	151020	0	0	0
T164	207113	0	0	0
T165	122799	0	0	0
T175	0	4	0	0
T176	0	38	0	0
T178	0	3	0	0
T179	0	28	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1625	0	0
T11	500298	0	0	0
T63	302446	82	0	0
T95	692577	0	0	0
T100	0	18	0	0
T101	0	47	0	0
T111	0	21	0	0
T146	0	19	0	0
T152	0	5	0	0
T159	281398	0	0	0
T160	394332	0	0	0
T161	44169	0	0	0
T162	331062	0	0	0
T163	151020	0	0	0
T164	207113	0	0	0
T165	122799	0	0	0
T175	0	4	0	0
T176	0	34	0	0
T178	0	8	0	0
T179	0	7	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1588	0	0
T11	500298	0	0	0
T63	302446	42	0	0
T95	692577	0	0	0
T100	0	21	0	0
T101	0	61	0	0
T111	0	38	0	0
T146	0	38	0	0
T152	0	8	0	0
T157	0	13	0	0
T159	281398	0	0	0
T160	394332	0	0	0
T161	44169	0	0	0
T162	331062	0	0	0
T163	151020	0	0	0
T164	207113	0	0	0
T165	122799	0	0	0
T175	0	6	0	0
T176	0	23	0	0
T179	0	9	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1607	0	0
T11	500298	0	0	0
T63	302446	81	0	0
T95	692577	0	0	0
T100	0	18	0	0
T101	0	47	0	0
T111	0	55	0	0
T146	0	47	0	0
T159	281398	0	0	0
T160	394332	0	0	0
T161	44169	0	0	0
T162	331062	0	0	0
T163	151020	0	0	0
T164	207113	0	0	0
T165	122799	0	0	0
T175	0	3	0	0
T176	0	63	0	0
T177	0	5	0	0
T178	0	5	0	0
T179	0	5	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1687	0	0
T11	500298	0	0	0
T63	302446	68	0	0
T95	692577	0	0	0
T100	0	30	0	0
T101	0	32	0	0
T111	0	26	0	0
T146	0	36	0	0
T152	0	9	0	0
T159	281398	0	0	0
T160	394332	0	0	0
T161	44169	0	0	0
T162	331062	0	0	0
T163	151020	0	0	0
T164	207113	0	0	0
T165	122799	0	0	0
T176	0	45	0	0
T177	0	2	0	0
T178	0	8	0	0
T179	0	48	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1548	0	0
T11	500298	0	0	0
T63	302446	87	0	0
T95	692577	0	0	0
T100	0	20	0	0
T101	0	50	0	0
T111	0	39	0	0
T146	0	51	0	0
T152	0	12	0	0
T159	281398	0	0	0
T160	394332	0	0	0
T161	44169	0	0	0
T162	331062	0	0	0
T163	151020	0	0	0
T164	207113	0	0	0
T165	122799	0	0	0
T175	0	3	0	0
T176	0	42	0	0
T178	0	2	0	0
T179	0	23	0	0