Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 256264313 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 183588929 1 T1 6198 T2 342664 T3 795



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 227300007 1 T1 6954 T2 449229 T3 1168
values[0x0] 102177414 1 T1 1631 T2 214599 T3 331
values[0x1] 110375821 1 T1 1843 T2 232545 T3 344



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 199248571 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 240604671 1 T1 7199 T2 463359 T3 1072



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 1310044 1 T1 38 T2 2659 T3 3
valid_sources[0x01] 1302444 1 T1 39 T2 2981 T3 5
valid_sources[0x02] 1294414 1 T1 30 T2 4165 T3 11
valid_sources[0x03] 1332499 1 T1 51 T2 3794 T3 6
valid_sources[0x04] 1301856 1 T1 47 T2 3576 T3 5
valid_sources[0x05] 4547195 1 T1 37 T2 4359 T3 10
valid_sources[0x06] 1307199 1 T1 53 T2 3490 T3 18
valid_sources[0x07] 2177796 1 T1 53 T2 3277 T3 2
valid_sources[0x08] 3261394 1 T1 29 T2 3810 T3 6
valid_sources[0x09] 1303039 1 T1 50 T2 3092 T21 138
valid_sources[0x0a] 2160833 1 T1 30 T2 3959 T3 1
valid_sources[0x0b] 1413215 1 T1 31 T2 3665 T3 12
valid_sources[0x0c] 3307278 1 T1 29 T2 3850 T3 2
valid_sources[0x0d] 1305200 1 T1 45 T2 3093 T3 17
valid_sources[0x0e] 1402167 1 T1 35 T2 3432 T3 9
valid_sources[0x0f] 1297833 1 T1 39 T2 3470 T3 15
valid_sources[0x10] 1300406 1 T1 34 T2 3547 T21 220
valid_sources[0x11] 1961189 1 T1 29 T2 3922 T3 5
valid_sources[0x12] 1961519 1 T1 43 T2 3379 T3 17
valid_sources[0x13] 1305103 1 T1 41 T2 2611 T3 10
valid_sources[0x14] 1293851 1 T1 47 T2 3590 T3 2
valid_sources[0x15] 2750541 1 T1 45 T2 3483 T3 14
valid_sources[0x16] 1303458 1 T1 27 T2 2714 T3 6
valid_sources[0x17] 1300922 1 T1 52 T2 3542 T3 11
valid_sources[0x18] 1300149 1 T1 50 T2 3580 T3 4
valid_sources[0x19] 1302602 1 T1 70 T2 2822 T3 2
valid_sources[0x1a] 1339280 1 T1 41 T2 3389 T3 5
valid_sources[0x1b] 1305030 1 T1 41 T2 3824 T3 3
valid_sources[0x1c] 1305512 1 T1 44 T2 4289 T3 2
valid_sources[0x1d] 1306149 1 T1 39 T2 2760 T3 6
valid_sources[0x1e] 3293627 1 T1 29 T2 4481 T3 3
valid_sources[0x1f] 1401996 1 T1 33 T2 3362 T3 13
valid_sources[0x20] 1300285 1 T1 50 T2 3605 T3 3
valid_sources[0x21] 1682795 1 T1 43 T2 3979 T3 15
valid_sources[0x22] 1301528 1 T1 28 T2 3246 T21 139
valid_sources[0x23] 1293963 1 T1 39 T2 3841 T3 1
valid_sources[0x24] 1307975 1 T1 34 T2 3409 T3 2
valid_sources[0x25] 1305535 1 T1 33 T2 3340 T3 3
valid_sources[0x26] 1300846 1 T1 44 T2 3838 T3 1
valid_sources[0x27] 2173643 1 T1 34 T2 3606 T3 16
valid_sources[0x28] 1518211 1 T1 52 T2 3324 T3 5
valid_sources[0x29] 1291995 1 T1 32 T2 3360 T3 12
valid_sources[0x2a] 2190407 1 T1 40 T2 3273 T3 7
valid_sources[0x2b] 1296053 1 T1 58 T2 3653 T3 7
valid_sources[0x2c] 1302070 1 T1 51 T2 3820 T3 5
valid_sources[0x2d] 3276444 1 T1 38 T2 3229 T3 14
valid_sources[0x2e] 1379911 1 T1 43 T2 3786 T3 8
valid_sources[0x2f] 3374970 1 T1 52 T2 3562 T3 5
valid_sources[0x30] 4311005 1 T1 36 T2 3931 T3 6
valid_sources[0x31] 3619685 1 T1 48 T2 4247 T3 10
valid_sources[0x32] 2142557 1 T1 41 T2 3001 T3 12
valid_sources[0x33] 1534432 1 T1 59 T2 2770 T3 12
valid_sources[0x34] 1454473 1 T1 38 T2 3928 T3 3
valid_sources[0x35] 2362541 1 T1 28 T2 3292 T3 9
valid_sources[0x36] 1304977 1 T1 51 T2 3725 T3 13
valid_sources[0x37] 1305213 1 T1 53 T2 3566 T3 9
valid_sources[0x38] 1312104 1 T1 37 T2 3002 T3 12
valid_sources[0x39] 1381003 1 T1 44 T2 2467 T3 13
valid_sources[0x3a] 1333081 1 T1 37 T2 3328 T3 10
valid_sources[0x3b] 1351993 1 T1 28 T2 3049 T3 4
valid_sources[0x3c] 1303385 1 T1 37 T2 3959 T3 10
valid_sources[0x3d] 1304179 1 T1 39 T2 3842 T3 11
valid_sources[0x3e] 1303576 1 T1 40 T2 3618 T3 6
valid_sources[0x3f] 1352375 1 T1 30 T2 3450 T21 93
valid_sources[0x40] 1415255 1 T1 30 T2 3043 T3 4
valid_sources[0x41] 1875566 1 T1 52 T2 3349 T3 9
valid_sources[0x42] 1299742 1 T1 60 T2 3250 T3 3
valid_sources[0x43] 1298789 1 T1 58 T2 3525 T3 13
valid_sources[0x44] 1485195 1 T1 40 T2 3876 T3 5
valid_sources[0x45] 1334190 1 T1 45 T2 3111 T3 15
valid_sources[0x46] 1715236 1 T1 32 T2 3646 T3 4
valid_sources[0x47] 1299252 1 T1 38 T2 3692 T3 14
valid_sources[0x48] 1342041 1 T1 30 T2 4009 T3 13
valid_sources[0x49] 1291547 1 T1 46 T2 2805 T3 7
valid_sources[0x4a] 2166460 1 T1 45 T2 3440 T3 13
valid_sources[0x4b] 2436414 1 T1 37 T2 3090 T3 14
valid_sources[0x4c] 2305797 1 T1 31 T2 3726 T3 3
valid_sources[0x4d] 1305699 1 T1 54 T2 3539 T3 5
valid_sources[0x4e] 2141349 1 T1 44 T2 2862 T3 1
valid_sources[0x4f] 1421529 1 T1 29 T2 3399 T3 9
valid_sources[0x50] 1823329 1 T1 42 T2 3729 T3 6
valid_sources[0x51] 1303141 1 T1 45 T2 3663 T3 7
valid_sources[0x52] 1495425 1 T1 34 T2 4150 T3 3
valid_sources[0x53] 2194230 1 T1 48 T2 4297 T3 6
valid_sources[0x54] 1299930 1 T1 56 T2 2866 T3 2
valid_sources[0x55] 1306220 1 T1 46 T2 3204 T3 6
valid_sources[0x56] 1313577 1 T1 29 T2 3919 T3 1
valid_sources[0x57] 1304531 1 T1 46 T2 4220 T3 15
valid_sources[0x58] 2608446 1 T1 30 T2 2624 T3 2
valid_sources[0x59] 1291650 1 T1 45 T2 2322 T3 5
valid_sources[0x5a] 1310497 1 T1 32 T2 3236 T3 2
valid_sources[0x5b] 1304677 1 T1 23 T2 3305 T3 6
valid_sources[0x5c] 1300894 1 T1 27 T2 3035 T3 7
valid_sources[0x5d] 1414638 1 T1 55 T2 3372 T3 14
valid_sources[0x5e] 3699697 1 T1 51 T2 3124 T3 3
valid_sources[0x5f] 1751731 1 T1 36 T2 4011 T3 11
valid_sources[0x60] 2032490 1 T1 23 T2 3354 T3 1
valid_sources[0x61] 1300731 1 T1 43 T2 3373 T3 3
valid_sources[0x62] 3287404 1 T1 39 T2 3568 T3 1
valid_sources[0x63] 2002638 1 T1 44 T2 3760 T3 11
valid_sources[0x64] 1305392 1 T1 46 T2 3021 T3 14
valid_sources[0x65] 2222171 1 T1 39 T2 3804 T3 6
valid_sources[0x66] 1298610 1 T1 49 T2 4224 T3 1
valid_sources[0x67] 1300181 1 T1 40 T2 3248 T3 7
valid_sources[0x68] 1386615 1 T1 47 T2 4092 T3 4
valid_sources[0x69] 1304665 1 T1 40 T2 3674 T3 16
valid_sources[0x6a] 1301275 1 T1 49 T2 3458 T3 14
valid_sources[0x6b] 2390034 1 T1 40 T2 3403 T3 5
valid_sources[0x6c] 2421428 1 T1 53 T2 3616 T3 5
valid_sources[0x6d] 1304532 1 T1 43 T2 3965 T3 2
valid_sources[0x6e] 1368445 1 T1 45 T2 3421 T3 3
valid_sources[0x6f] 1506199 1 T1 18 T2 2798 T3 1
valid_sources[0x70] 1549608 1 T1 34 T2 3754 T3 10
valid_sources[0x71] 1451546 1 T1 51 T2 3155 T3 15
valid_sources[0x72] 1377417 1 T1 61 T2 3786 T3 7
valid_sources[0x73] 2204724 1 T1 37 T2 3271 T3 8
valid_sources[0x74] 1319890 1 T1 50 T2 3259 T3 11
valid_sources[0x75] 2185158 1 T1 42 T2 3502 T3 1
valid_sources[0x76] 1297585 1 T1 41 T2 3024 T3 7
valid_sources[0x77] 1308306 1 T1 31 T2 3353 T3 11
valid_sources[0x78] 1342175 1 T1 34 T2 3088 T3 15
valid_sources[0x79] 1513910 1 T1 65 T2 3060 T3 7
valid_sources[0x7a] 1303157 1 T1 48 T2 3625 T3 3
valid_sources[0x7b] 1765273 1 T1 36 T2 3624 T3 7
valid_sources[0x7c] 1301640 1 T1 42 T2 3725 T3 3
valid_sources[0x7d] 1968603 1 T1 24 T2 3897 T3 10
valid_sources[0x7e] 1304658 1 T1 44 T2 3351 T3 16
valid_sources[0x7f] 3231191 1 T1 27 T2 3668 T3 8
valid_sources[0x80] 1303245 1 T1 52 T2 3913 T3 6



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 70919160 1 T1 4261 T2 116687 T3 501
values[0x0] all_enables biggest_size 60516843 1 T1 1017 T2 122224 T3 175
values[0x1] all_enables biggest_size 52152926 1 T1 920 T2 103753 T3 119

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%