Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

257204854

1

T1

4230

T2

553709

T3

1048

full_word

183648222

1

T1

6198

T2

342664

T3

795

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	440852756	1			T1	10428		T2	896373		T3	1843
auto[TlIntgErrCmd]	112	1			T132	7		T133	7		T134	4
auto[TlIntgErrData]	105	1			T132	7		T133	5		T134	3
auto[TlIntgErrBoth]	103	1			T132	6		T133	8		T134	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

227483442

1

T1

6954

T2

449229

T3

1168

auto[1]

213369634

1

T1

3474

T2

447144

T3

675

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	156549217	1			T1	2693		T2	332542		T3	667
auto[TlIntgErrNone]	partial	auto[1]	100655347	1			T1	1537		T2	221167		T3	381
auto[TlIntgErrNone]	full_word	auto[0]	70934076	1			T1	4261		T2	116687		T3	501
auto[TlIntgErrNone]	full_word	auto[1]	112714116	1			T1	1937		T2	225977		T3	294
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T132	2		T133	6		T134	1
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T132	4		T133	1		T134	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T190	1		T192	1		T193	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T132	1		T188	1		T190	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T132	1		T133	1		T134	1
auto[TlIntgErrData]	partial	auto[1]	48	1			T132	3		T133	3		T134	1
auto[TlIntgErrData]	full_word	auto[0]	8	1			T132	2		T133	1		T134	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T132	1		T188	1		T194	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T132	4		T133	4		T134	2
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T132	2		T133	3		T134	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T195	1		T189	1		T196	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T133	1		T186	1		T187	1