Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	217567	0	0
entropy_period_rd_A	2147483647	928	0	0
intr_enable_rd_A	2147483647	1251	0	0
prefix_0_rd_A	2147483647	881	0	0
prefix_10_rd_A	2147483647	925	0	0
prefix_1_rd_A	2147483647	969	0	0
prefix_2_rd_A	2147483647	850	0	0
prefix_3_rd_A	2147483647	916	0	0
prefix_4_rd_A	2147483647	889	0	0
prefix_5_rd_A	2147483647	904	0	0
prefix_6_rd_A	2147483647	957	0	0
prefix_7_rd_A	2147483647	923	0	0
prefix_8_rd_A	2147483647	928	0	0
prefix_9_rd_A	2147483647	792	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	217567	0	0
T48	192351	18616	0	0
T49	0	80279	0	0
T50	0	114604	0	0
T132	0	1	0	0
T133	0	3	0	0
T138	0	5	0	0
T139	0	4	0	0
T140	0	183	0	0
T141	0	87	0	0
T142	0	345	0	0
T143	11862	0	0	0
T144	222298	0	0	0
T145	130290	0	0	0
T146	202994	0	0	0
T147	26815	0	0	0
T148	438031	0	0	0
T149	535833	0	0	0
T150	748162	0	0	0
T151	125340	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	928	0	0
T88	11544	86	0	0
T90	2561	2	0	0
T92	7113	37	0	0
T160	2581	14	0	0
T161	9842	32	0	0
T162	3234	5	0	0
T163	3881	4	0	0
T164	7885	24	0	0
T165	3785	18	0	0
T166	72329	107	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1251	0	0
T88	11544	81	0	0
T135	1357	12	0	0
T160	2581	25	0	0
T161	9842	64	0	0
T162	3234	10	0	0
T163	3881	25	0	0
T167	926	10	0	0
T168	1413	6	0	0
T169	1378	2	0	0
T170	1110	10	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	881	0	0
T88	11544	63	0	0
T90	2561	9	0	0
T92	7113	27	0	0
T160	2581	8	0	0
T161	9842	28	0	0
T162	3234	10	0	0
T163	3881	2	0	0
T164	7885	20	0	0
T165	3785	8	0	0
T166	72329	204	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	925	0	0
T88	11544	63	0	0
T90	2561	6	0	0
T92	7113	33	0	0
T160	2581	14	0	0
T161	9842	33	0	0
T163	3881	9	0	0
T164	7885	13	0	0
T165	3785	10	0	0
T166	72329	211	0	0
T171	5482	20	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	969	0	0
T88	11544	54	0	0
T90	2561	8	0	0
T92	7113	31	0	0
T160	2581	15	0	0
T161	9842	19	0	0
T162	3234	11	0	0
T164	7885	21	0	0
T165	3785	8	0	0
T166	72329	215	0	0
T171	5482	24	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	850	0	0
T88	11544	63	0	0
T90	2561	9	0	0
T92	7113	26	0	0
T160	2581	5	0	0
T161	9842	32	0	0
T162	3234	5	0	0
T163	3881	6	0	0
T164	7885	17	0	0
T165	3785	12	0	0
T166	72329	228	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	916	0	0
T88	11544	62	0	0
T92	7113	39	0	0
T160	2581	8	0	0
T161	9842	21	0	0
T162	3234	11	0	0
T163	3881	8	0	0
T164	7885	21	0	0
T165	3785	8	0	0
T166	72329	223	0	0
T171	5482	34	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	889	0	0
T88	11544	56	0	0
T90	2561	9	0	0
T92	7113	27	0	0
T160	2581	6	0	0
T161	9842	26	0	0
T162	3234	9	0	0
T163	3881	2	0	0
T164	7885	13	0	0
T165	3785	10	0	0
T166	72329	203	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	904	0	0
T88	11544	70	0	0
T90	2561	3	0	0
T92	7113	21	0	0
T160	2581	3	0	0
T161	9842	53	0	0
T162	3234	5	0	0
T163	3881	5	0	0
T164	7885	18	0	0
T165	3785	5	0	0
T166	72329	265	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	957	0	0
T88	11544	44	0	0
T92	7113	38	0	0
T160	2581	12	0	0
T161	9842	50	0	0
T162	3234	3	0	0
T164	7885	18	0	0
T165	3785	14	0	0
T166	72329	233	0	0
T171	5482	31	0	0
T172	2992	6	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	923	0	0
T88	11544	65	0	0
T90	2561	7	0	0
T92	7113	25	0	0
T160	2581	3	0	0
T161	9842	31	0	0
T163	3881	15	0	0
T164	7885	7	0	0
T165	3785	7	0	0
T166	72329	253	0	0
T171	5482	31	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	928	0	0
T88	11544	58	0	0
T92	7113	31	0	0
T160	2581	8	0	0
T161	9842	34	0	0
T163	3881	5	0	0
T164	7885	22	0	0
T165	3785	13	0	0
T166	72329	241	0	0
T171	5482	29	0	0
T172	2992	2	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	792	0	0
T88	11544	39	0	0
T92	7113	28	0	0
T160	2581	5	0	0
T161	9842	17	0	0
T164	7885	11	0	0
T165	3785	9	0	0
T166	72329	228	0	0
T171	5482	26	0	0
T172	2992	11	0	0
T173	5362	13	0	0