Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 257923642 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 182940216 1 T1 103527 T2 342180 T3 14155



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 228465978 1 T1 139191 T2 443867 T3 15708
values[0x0] 102081783 1 T1 32268 T2 212725 T3 3411
values[0x1] 110316097 1 T1 34287 T2 229046 T3 3730



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 200428614 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 240435244 1 T1 129341 T2 459509 T3 16288



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 1333668 1 T1 60 T2 3491 T3 81
valid_sources[0x01] 1335540 1 T1 49 T2 3437 T3 129
valid_sources[0x02] 1521836 1 T1 190543 T2 3511 T3 95
valid_sources[0x03] 1342399 1 T1 64 T2 3448 T3 74
valid_sources[0x04] 1346095 1 T1 54 T2 3726 T3 75
valid_sources[0x05] 1973146 1 T1 74 T2 3591 T3 70
valid_sources[0x06] 1339530 1 T1 60 T2 3376 T3 72
valid_sources[0x07] 2238537 1 T1 61 T2 3585 T3 79
valid_sources[0x08] 1330823 1 T1 57 T2 3471 T3 74
valid_sources[0x09] 1349222 1 T1 54 T2 3470 T3 103
valid_sources[0x0a] 1334650 1 T1 63 T2 3324 T3 85
valid_sources[0x0b] 1332341 1 T1 75 T2 3559 T3 88
valid_sources[0x0c] 1789282 1 T1 70 T2 3522 T3 64
valid_sources[0x0d] 1340899 1 T1 60 T2 3370 T3 89
valid_sources[0x0e] 1337222 1 T1 55 T2 3522 T3 92
valid_sources[0x0f] 1333199 1 T1 59 T2 3652 T3 102
valid_sources[0x10] 2108910 1 T1 53 T2 3563 T3 99
valid_sources[0x11] 1337429 1 T1 66 T2 3366 T3 88
valid_sources[0x12] 3328507 1 T1 66 T2 3440 T3 93
valid_sources[0x13] 1470405 1 T1 44 T2 3512 T3 94
valid_sources[0x14] 1360368 1 T1 60 T2 3477 T3 79
valid_sources[0x15] 1330820 1 T1 66 T2 3489 T3 90
valid_sources[0x16] 1329808 1 T1 66 T2 3391 T3 96
valid_sources[0x17] 1336176 1 T1 57 T2 3585 T3 87
valid_sources[0x18] 2322997 1 T1 60 T2 3729 T3 108
valid_sources[0x19] 1394020 1 T1 65 T2 3458 T3 94
valid_sources[0x1a] 1339362 1 T1 61 T2 3507 T3 99
valid_sources[0x1b] 1331581 1 T1 58 T2 3292 T3 93
valid_sources[0x1c] 1333485 1 T1 60 T2 3459 T3 84
valid_sources[0x1d] 1335260 1 T1 68 T2 3441 T3 82
valid_sources[0x1e] 1334091 1 T1 61 T2 3503 T3 85
valid_sources[0x1f] 2699249 1 T1 69 T2 3351 T3 90
valid_sources[0x20] 2166168 1 T1 60 T2 3564 T3 81
valid_sources[0x21] 2270678 1 T1 64 T2 3319 T3 103
valid_sources[0x22] 1344497 1 T1 50 T2 3525 T3 80
valid_sources[0x23] 1378094 1 T1 65 T2 3307 T3 87
valid_sources[0x24] 2292767 1 T1 59 T2 3579 T3 79
valid_sources[0x25] 1344167 1 T1 54 T2 3357 T3 99
valid_sources[0x26] 1335147 1 T1 61 T2 3347 T3 92
valid_sources[0x27] 1323806 1 T1 71 T2 3337 T3 85
valid_sources[0x28] 1386630 1 T1 63 T2 3512 T3 78
valid_sources[0x29] 1515693 1 T1 62 T2 3586 T3 104
valid_sources[0x2a] 2322240 1 T1 58 T2 3478 T3 87
valid_sources[0x2b] 2121691 1 T1 53 T2 3622 T3 67
valid_sources[0x2c] 1857424 1 T1 58 T2 3400 T3 78
valid_sources[0x2d] 2351802 1 T1 66 T2 3716 T3 82
valid_sources[0x2e] 1342786 1 T1 63 T2 3410 T3 90
valid_sources[0x2f] 5084158 1 T1 53 T2 3367 T3 83
valid_sources[0x30] 3610383 1 T1 65 T2 3277 T3 106
valid_sources[0x31] 1335587 1 T1 64 T2 3197 T3 99
valid_sources[0x32] 1331868 1 T1 65 T2 3423 T3 81
valid_sources[0x33] 1332692 1 T1 57 T2 3538 T3 77
valid_sources[0x34] 1427974 1 T1 51 T2 3375 T3 93
valid_sources[0x35] 1330826 1 T1 56 T2 3579 T3 84
valid_sources[0x36] 2405142 1 T1 46 T2 3456 T3 85
valid_sources[0x37] 1334105 1 T1 61 T2 3435 T3 74
valid_sources[0x38] 1827144 1 T1 52 T2 3597 T3 90
valid_sources[0x39] 1997325 1 T1 63 T2 3383 T3 81
valid_sources[0x3a] 1340273 1 T1 57 T2 3489 T3 96
valid_sources[0x3b] 1329035 1 T1 63 T2 3233 T3 119
valid_sources[0x3c] 1484453 1 T1 69 T2 3458 T3 85
valid_sources[0x3d] 1358785 1 T1 67 T2 3525 T3 97
valid_sources[0x3e] 2029050 1 T1 60 T2 3290 T3 91
valid_sources[0x3f] 1423170 1 T1 61 T2 3446 T3 90
valid_sources[0x40] 5643460 1 T1 55 T2 3409 T3 100
valid_sources[0x41] 1370858 1 T1 55 T2 3491 T3 89
valid_sources[0x42] 1335967 1 T1 70 T2 3566 T3 83
valid_sources[0x43] 1797369 1 T1 63 T2 3656 T3 105
valid_sources[0x44] 1336557 1 T1 58 T2 3603 T3 89
valid_sources[0x45] 1336141 1 T1 65 T2 3503 T3 83
valid_sources[0x46] 3312670 1 T1 55 T2 3304 T3 85
valid_sources[0x47] 1359335 1 T1 70 T2 3425 T3 86
valid_sources[0x48] 1336400 1 T1 68 T2 3322 T3 96
valid_sources[0x49] 1424700 1 T1 56 T2 3655 T3 99
valid_sources[0x4a] 1517829 1 T1 67 T2 3272 T3 82
valid_sources[0x4b] 1338050 1 T1 52 T2 3281 T3 96
valid_sources[0x4c] 1798326 1 T1 63 T2 3371 T3 76
valid_sources[0x4d] 1337607 1 T1 49 T2 3269 T3 71
valid_sources[0x4e] 1340571 1 T1 66 T2 3399 T3 99
valid_sources[0x4f] 3303665 1 T1 44 T2 3514 T3 113
valid_sources[0x50] 1326653 1 T1 53 T2 3550 T3 104
valid_sources[0x51] 3658640 1 T1 77 T2 3417 T3 81
valid_sources[0x52] 1991899 1 T1 50 T2 3419 T3 92
valid_sources[0x53] 1349401 1 T1 69 T2 3566 T3 86
valid_sources[0x54] 4237479 1 T1 61 T2 3557 T3 98
valid_sources[0x55] 3255657 1 T1 68 T2 3502 T3 76
valid_sources[0x56] 1448508 1 T1 53 T2 3348 T3 85
valid_sources[0x57] 2313109 1 T1 67 T2 3690 T3 100
valid_sources[0x58] 3683205 1 T1 67 T2 3447 T3 90
valid_sources[0x59] 1331681 1 T1 58 T2 3420 T3 71
valid_sources[0x5a] 5219555 1 T1 58 T2 3483 T3 94
valid_sources[0x5b] 1334545 1 T1 60 T2 3393 T3 75
valid_sources[0x5c] 3010117 1 T1 55 T2 3259 T3 95
valid_sources[0x5d] 1338732 1 T1 64 T2 3452 T3 80
valid_sources[0x5e] 1338712 1 T1 60 T2 3607 T3 93
valid_sources[0x5f] 3276098 1 T1 61 T2 3799 T3 104
valid_sources[0x60] 1340962 1 T1 71 T2 3359 T3 105
valid_sources[0x61] 1339034 1 T1 57 T2 3638 T3 101
valid_sources[0x62] 1338050 1 T1 67 T2 3639 T3 88
valid_sources[0x63] 3318936 1 T1 61 T2 3443 T3 96
valid_sources[0x64] 1354712 1 T1 66 T2 3120 T3 85
valid_sources[0x65] 1682421 1 T1 50 T2 3509 T3 92
valid_sources[0x66] 1329051 1 T1 49 T2 3451 T3 88
valid_sources[0x67] 1447670 1 T1 69 T2 3548 T3 103
valid_sources[0x68] 1497291 1 T1 56 T2 3498 T3 101
valid_sources[0x69] 1332911 1 T1 69 T2 3487 T3 88
valid_sources[0x6a] 2243702 1 T1 55 T2 3536 T3 89
valid_sources[0x6b] 1437026 1 T1 55 T2 3749 T3 96
valid_sources[0x6c] 1331948 1 T1 68 T2 3218 T3 84
valid_sources[0x6d] 1399665 1 T1 60 T2 3562 T3 78
valid_sources[0x6e] 1354728 1 T1 56 T2 3545 T3 88
valid_sources[0x6f] 1337900 1 T1 69 T2 3307 T3 80
valid_sources[0x70] 1334986 1 T1 52 T2 3672 T3 96
valid_sources[0x71] 1335438 1 T1 55 T2 3371 T3 83
valid_sources[0x72] 1407327 1 T1 49 T2 3248 T3 89
valid_sources[0x73] 1329091 1 T1 55 T2 3481 T3 99
valid_sources[0x74] 1344302 1 T1 63 T2 3405 T3 90
valid_sources[0x75] 1345258 1 T1 63 T2 3425 T3 76
valid_sources[0x76] 1334179 1 T1 47 T2 3396 T3 85
valid_sources[0x77] 2324249 1 T1 68 T2 3513 T3 84
valid_sources[0x78] 1336080 1 T1 59 T2 3370 T3 88
valid_sources[0x79] 1342243 1 T1 49 T2 3380 T3 112
valid_sources[0x7a] 1347429 1 T1 73 T2 3540 T3 79
valid_sources[0x7b] 3284892 1 T1 55 T2 3575 T3 102
valid_sources[0x7c] 1391576 1 T1 69 T2 3400 T3 106
valid_sources[0x7d] 1342114 1 T1 72 T2 3533 T3 88
valid_sources[0x7e] 1818562 1 T1 55 T2 3621 T3 77
valid_sources[0x7f] 1339200 1 T1 55 T2 3413 T3 90
valid_sources[0x80] 1406836 1 T1 61 T2 3513 T3 91



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 70608823 1 T1 66108 T2 115159 T3 10000
values[0x0] all_enables biggest_size 60360074 1 T1 20173 T2 122419 T3 2156
values[0x1] all_enables biggest_size 51971319 1 T1 17246 T2 104602 T3 1999

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%