Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

258845513

1

T1

102219

T2

543458

T3

8694

full_word

182998780

1

T1

103527

T2

342180

T3

14155

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	441843993	1			T1	205746		T2	885638		T3	22849
auto[TlIntgErrCmd]	102	1			T125	4		T126	2		T127	4
auto[TlIntgErrData]	93	1			T125	3		T126	9		T127	5
auto[TlIntgErrBoth]	105	1			T125	3		T126	9		T127	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

228646006

1

T1

139191

T2

443867

T3

15708

auto[1]

213198287

1

T1

66555

T2

441771

T3

7141

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	158022348	1			T1	73083		T2	328708		T3	5708
auto[TlIntgErrNone]	partial	auto[1]	100822896	1			T1	29136		T2	214750		T3	2986
auto[TlIntgErrNone]	full_word	auto[0]	70623525	1			T1	66108		T2	115159		T3	10000
auto[TlIntgErrNone]	full_word	auto[1]	112375224	1			T1	37419		T2	227021		T3	4155
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T125	1		T126	1		T127	2
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T125	3		T126	1		T127	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T182	1		T183	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T170	1		T184	1		T185	1
auto[TlIntgErrData]	partial	auto[0]	38	1			T125	1		T126	6		T127	3
auto[TlIntgErrData]	partial	auto[1]	41	1			T125	2		T126	2		T127	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T126	1		T182	1		T170	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T127	1		T170	1		T186	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T126	4		T127	5		T182	3
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T125	3		T126	5		T127	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T127	1		T187	1		T188	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T187	1		T189	1		T186	1