Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	2147483647	342537	0	0
RunThenComplete_M	2147483647	3042048	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	342537	0	0
T1	535647	172	0	0
T2	643659	390	0	0
T3	217345	32	0	0
T4	53568	6	0	0
T7	740629	161	0	0
T11	333478	0	0	0
T31	19359	9	0	0
T32	592138	2337	0	0
T33	1980	0	0	0
T34	61933	61	0	0
T36	0	122	0	0
T55	0	310	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3042048	0	0
T1	535647	1017	0	0
T2	643659	5542	0	0
T3	217345	151	0	0
T4	53568	18	0	0
T7	740629	832	0	0
T11	333478	0	0	0
T31	19359	31	0	0
T32	592138	13147	0	0
T33	1980	0	0	0
T34	61933	149	0	0
T36	0	671	0	0
T55	0	5462	0	0