Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	215029	0	0
entropy_period_rd_A	2147483647	2210	0	0
intr_enable_rd_A	2147483647	2746	0	0
prefix_0_rd_A	2147483647	1913	0	0
prefix_10_rd_A	2147483647	1948	0	0
prefix_1_rd_A	2147483647	1935	0	0
prefix_2_rd_A	2147483647	1887	0	0
prefix_3_rd_A	2147483647	1938	0	0
prefix_4_rd_A	2147483647	1841	0	0
prefix_5_rd_A	2147483647	1977	0	0
prefix_6_rd_A	2147483647	1951	0	0
prefix_7_rd_A	2147483647	1870	0	0
prefix_8_rd_A	2147483647	1991	0	0
prefix_9_rd_A	2147483647	2080	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	215029	0	0
T42	963198	130404	0	0
T43	0	46977	0	0
T44	0	34959	0	0
T76	2609	0	0	0
T127	0	2	0	0
T132	0	7	0	0
T133	0	44	0	0
T134	0	16	0	0
T135	0	1	0	0
T136	0	5	0	0
T137	0	43	0	0
T138	538869	0	0	0
T139	163935	0	0	0
T140	121544	0	0	0
T141	123990	0	0	0
T142	105782	0	0	0
T143	1709	0	0	0
T144	496010	0	0	0
T145	21618	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2210	0	0
T102	13343	122	0	0
T107	7929	43	0	0
T125	12098	68	0	0
T132	8852	18	0	0
T135	3975	5	0	0
T136	6858	15	0	0
T164	6450	27	0	0
T165	11044	39	0	0
T166	5338	8	0	0
T167	7906	12	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2746	0	0
T102	13343	106	0	0
T125	12098	82	0	0
T132	8852	28	0	0
T135	3975	7	0	0
T136	6858	12	0	0
T164	6450	15	0	0
T165	11044	58	0	0
T166	5338	2	0	0
T167	7906	18	0	0
T168	6220	37	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1913	0	0
T102	13343	41	0	0
T125	12098	42	0	0
T132	8852	20	0	0
T135	3975	9	0	0
T136	6858	19	0	0
T164	6450	5	0	0
T165	11044	77	0	0
T166	5338	13	0	0
T168	6220	41	0	0
T169	12461	6	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1948	0	0
T102	13343	51	0	0
T107	7929	29	0	0
T125	12098	38	0	0
T132	8852	19	0	0
T136	6858	11	0	0
T164	6450	23	0	0
T165	11044	37	0	0
T166	5338	8	0	0
T167	7906	19	0	0
T168	6220	28	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1935	0	0
T102	13343	57	0	0
T125	12098	31	0	0
T132	8852	21	0	0
T135	3975	11	0	0
T136	6858	5	0	0
T164	6450	39	0	0
T165	11044	70	0	0
T166	5338	6	0	0
T167	7906	22	0	0
T168	6220	12	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1887	0	0
T102	13343	75	0	0
T107	7929	30	0	0
T125	12098	48	0	0
T132	8852	27	0	0
T136	6858	17	0	0
T164	6450	15	0	0
T165	11044	26	0	0
T166	5338	8	0	0
T167	7906	8	0	0
T170	23656	93	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1938	0	0
T102	13343	46	0	0
T125	12098	46	0	0
T132	8852	16	0	0
T135	3975	6	0	0
T136	6858	6	0	0
T164	6450	30	0	0
T165	11044	56	0	0
T166	5338	6	0	0
T167	7906	12	0	0
T168	6220	5	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1841	0	0
T102	13343	53	0	0
T125	12098	51	0	0
T132	8852	26	0	0
T135	3975	9	0	0
T136	6858	1	0	0
T164	6450	11	0	0
T165	11044	10	0	0
T166	5338	5	0	0
T167	7906	18	0	0
T168	6220	3	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1977	0	0
T102	13343	65	0	0
T125	12098	53	0	0
T132	8852	17	0	0
T135	3975	8	0	0
T136	6858	7	0	0
T164	6450	6	0	0
T165	11044	81	0	0
T166	5338	5	0	0
T167	7906	20	0	0
T168	6220	10	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1951	0	0
T102	13343	51	0	0
T125	12098	36	0	0
T132	8852	16	0	0
T135	3975	8	0	0
T136	6858	2	0	0
T164	6450	4	0	0
T165	11044	43	0	0
T166	5338	9	0	0
T167	7906	13	0	0
T168	6220	51	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1870	0	0
T102	13343	52	0	0
T107	7929	31	0	0
T125	12098	41	0	0
T132	8852	11	0	0
T136	6858	6	0	0
T164	6450	17	0	0
T165	11044	30	0	0
T166	5338	11	0	0
T167	7906	19	0	0
T168	6220	43	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1991	0	0
T102	13343	56	0	0
T107	7929	23	0	0
T125	12098	46	0	0
T132	8852	13	0	0
T136	6858	5	0	0
T164	6450	6	0	0
T165	11044	49	0	0
T166	5338	13	0	0
T167	7906	14	0	0
T168	6220	13	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2080	0	0
T102	13343	68	0	0
T125	12098	43	0	0
T132	8852	29	0	0
T135	3975	3	0	0
T136	6858	15	0	0
T164	6450	1	0	0
T165	11044	46	0	0
T166	5338	3	0	0
T167	7906	8	0	0
T168	6220	28	0	0