Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

164702615

1

T1

3465

T2

12

T3

657

full_word

120839698

1

T1

18640

T2

6

T3

1100

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	285541993	1			T1	22105		T2	18		T3	1757
auto[TlIntgErrCmd]	118	1			T132	3		T133	4		T134	3
auto[TlIntgErrData]	105	1			T132	4		T133	3		T134	4
auto[TlIntgErrBoth]	97	1			T132	3		T133	3		T134	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

148420350

1

T1

7375

T2

1

T3

719

auto[1]

137121963

1

T1

14730

T2

17

T3

1038

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	101512883	1			T1	3280		T3	393		T18	239768
auto[TlIntgErrNone]	partial	auto[1]	63189440	1			T1	185		T2	12		T3	264
auto[TlIntgErrNone]	full_word	auto[0]	46907335	1			T1	4095		T2	1		T3	326
auto[TlIntgErrNone]	full_word	auto[1]	73932335	1			T1	14545		T2	5		T3	774
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T132	1		T133	2		T197	2
auto[TlIntgErrCmd]	partial	auto[1]	69	1			T132	2		T133	2		T134	3
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T197	3		T198	1		T199	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T132	3		T133	2		T134	3
auto[TlIntgErrData]	partial	auto[1]	45	1			T132	1		T133	1		T197	1
auto[TlIntgErrData]	full_word	auto[0]	1	1			T200	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	9	1			T134	1		T197	1		T201	2
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T132	2		T133	1		T134	1
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T132	1		T133	2		T134	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T134	1		T202	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T201	1		T203	1		T204	2