Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1391585569	296193	0	0
entropy_period_rd_A	1391585569	2244	0	0
intr_enable_rd_A	1391585569	2954	0	0
prefix_0_rd_A	1391585569	2290	0	0
prefix_10_rd_A	1391585569	2283	0	0
prefix_1_rd_A	1391585569	2217	0	0
prefix_2_rd_A	1391585569	2013	0	0
prefix_3_rd_A	1391585569	2315	0	0
prefix_4_rd_A	1391585569	2155	0	0
prefix_5_rd_A	1391585569	2206	0	0
prefix_6_rd_A	1391585569	2130	0	0
prefix_7_rd_A	1391585569	2237	0	0
prefix_8_rd_A	1391585569	2290	0	0
prefix_9_rd_A	1391585569	2178	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1391585569	296193	0	0
T25	651875	0	0	0
T27	4921	0	0	0
T34	1936	0	0	0
T58	893885	77038	0	0
T68	0	37938	0	0
T69	0	33329	0	0
T76	577378	0	0	0
T85	0	44706	0	0
T132	0	2	0	0
T139	0	100092	0	0
T140	0	248	0	0
T141	0	175	0	0
T142	0	2	0	0
T143	0	6	0	0
T145	17314	0	0	0
T146	139352	0	0	0
T147	603456	0	0	0
T148	993	0	0	0
T149	1268	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1391585569	2244	0	0
T85	556315	136	0	0
T97	0	6	0	0
T138	0	52	0	0
T150	0	16	0	0
T165	0	24	0	0
T166	0	39	0	0
T167	0	19	0	0
T168	0	10	0	0
T169	0	3	0	0
T170	0	443	0	0
T171	115934	0	0	0
T172	262085	0	0	0
T173	470970	0	0	0
T174	36380	0	0	0
T175	20591	0	0	0
T176	479242	0	0	0
T177	45303	0	0	0
T178	565820	0	0	0
T179	133990	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1391585569	2954	0	0
T85	556315	115	0	0
T97	0	8	0	0
T138	0	89	0	0
T150	0	36	0	0
T165	0	23	0	0
T166	0	92	0	0
T171	115934	0	0	0
T172	262085	0	0	0
T173	470970	0	0	0
T174	36380	0	0	0
T175	20591	0	0	0
T176	479242	0	0	0
T177	45303	0	0	0
T178	565820	0	0	0
T179	133990	0	0	0
T180	0	16	0	0
T181	0	4	0	0
T182	0	12	0	0
T183	0	13	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1391585569	2290	0	0
T85	556315	174	0	0
T97	0	12	0	0
T138	0	43	0	0
T150	0	15	0	0
T165	0	42	0	0
T166	0	12	0	0
T167	0	8	0	0
T168	0	15	0	0
T171	115934	0	0	0
T172	262085	0	0	0
T173	470970	0	0	0
T174	36380	0	0	0
T175	20591	0	0	0
T176	479242	0	0	0
T177	45303	0	0	0
T178	565820	0	0	0
T179	133990	0	0	0
T181	0	58	0	0
T182	0	6	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1391585569	2283	0	0
T85	556315	117	0	0
T97	0	7	0	0
T138	0	39	0	0
T150	0	14	0	0
T165	0	40	0	0
T166	0	38	0	0
T167	0	7	0	0
T168	0	20	0	0
T171	115934	0	0	0
T172	262085	0	0	0
T173	470970	0	0	0
T174	36380	0	0	0
T175	20591	0	0	0
T176	479242	0	0	0
T177	45303	0	0	0
T178	565820	0	0	0
T179	133990	0	0	0
T181	0	7	0	0
T182	0	2	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1391585569	2217	0	0
T85	556315	157	0	0
T97	0	11	0	0
T138	0	28	0	0
T150	0	19	0	0
T165	0	3	0	0
T166	0	38	0	0
T167	0	5	0	0
T168	0	15	0	0
T171	115934	0	0	0
T172	262085	0	0	0
T173	470970	0	0	0
T174	36380	0	0	0
T175	20591	0	0	0
T176	479242	0	0	0
T177	45303	0	0	0
T178	565820	0	0	0
T179	133990	0	0	0
T181	0	8	0	0
T182	0	7	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1391585569	2013	0	0
T85	556315	139	0	0
T97	0	10	0	0
T138	0	34	0	0
T150	0	10	0	0
T165	0	9	0	0
T166	0	10	0	0
T167	0	9	0	0
T168	0	12	0	0
T171	115934	0	0	0
T172	262085	0	0	0
T173	470970	0	0	0
T174	36380	0	0	0
T175	20591	0	0	0
T176	479242	0	0	0
T177	45303	0	0	0
T178	565820	0	0	0
T179	133990	0	0	0
T181	0	4	0	0
T182	0	5	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1391585569	2315	0	0
T85	556315	149	0	0
T97	0	13	0	0
T138	0	61	0	0
T150	0	28	0	0
T165	0	31	0	0
T166	0	70	0	0
T167	0	9	0	0
T168	0	5	0	0
T169	0	9	0	0
T171	115934	0	0	0
T172	262085	0	0	0
T173	470970	0	0	0
T174	36380	0	0	0
T175	20591	0	0	0
T176	479242	0	0	0
T177	45303	0	0	0
T178	565820	0	0	0
T179	133990	0	0	0
T181	0	22	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1391585569	2155	0	0
T85	556315	132	0	0
T97	0	4	0	0
T138	0	73	0	0
T150	0	14	0	0
T165	0	25	0	0
T166	0	25	0	0
T167	0	7	0	0
T168	0	10	0	0
T169	0	6	0	0
T171	115934	0	0	0
T172	262085	0	0	0
T173	470970	0	0	0
T174	36380	0	0	0
T175	20591	0	0	0
T176	479242	0	0	0
T177	45303	0	0	0
T178	565820	0	0	0
T179	133990	0	0	0
T181	0	4	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1391585569	2206	0	0
T85	556315	143	0	0
T97	0	15	0	0
T138	0	51	0	0
T150	0	21	0	0
T165	0	31	0	0
T166	0	37	0	0
T167	0	4	0	0
T168	0	12	0	0
T171	115934	0	0	0
T172	262085	0	0	0
T173	470970	0	0	0
T174	36380	0	0	0
T175	20591	0	0	0
T176	479242	0	0	0
T177	45303	0	0	0
T178	565820	0	0	0
T179	133990	0	0	0
T181	0	12	0	0
T182	0	14	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1391585569	2130	0	0
T85	556315	140	0	0
T97	0	13	0	0
T138	0	46	0	0
T150	0	20	0	0
T165	0	11	0	0
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T167	0	2	0	0
T168	0	10	0	0
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T173	470970	0	0	0
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T178	565820	0	0	0
T179	133990	0	0	0
T181	0	22	0	0
T182	0	7	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1391585569	2237	0	0
T85	556315	170	0	0
T97	0	7	0	0
T138	0	33	0	0
T150	0	27	0	0
T165	0	4	0	0
T166	0	33	0	0
T167	0	1	0	0
T168	0	8	0	0
T171	115934	0	0	0
T172	262085	0	0	0
T173	470970	0	0	0
T174	36380	0	0	0
T175	20591	0	0	0
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T177	45303	0	0	0
T178	565820	0	0	0
T179	133990	0	0	0
T181	0	17	0	0
T182	0	2	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1391585569	2290	0	0
T85	556315	119	0	0
T97	0	11	0	0
T138	0	37	0	0
T150	0	28	0	0
T165	0	26	0	0
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T168	0	16	0	0
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T179	133990	0	0	0
T181	0	9	0	0
T182	0	7	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1391585569	2178	0	0
T85	556315	115	0	0
T97	0	12	0	0
T138	0	39	0	0
T144	0	6	0	0
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T177	45303	0	0	0
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