Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
179441 |
1 |
|
|
T2 |
109 |
|
T3 |
86 |
|
T6 |
139 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
99930 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
55538 |
1 |
|
|
T2 |
107 |
|
T3 |
85 |
|
T6 |
137 |
seven_bytes |
3355 |
1 |
|
|
T18 |
78 |
|
T19 |
15 |
|
T13 |
87 |
six_bytes |
3400 |
1 |
|
|
T18 |
88 |
|
T19 |
12 |
|
T13 |
93 |
five_bytes |
3508 |
1 |
|
|
T18 |
76 |
|
T19 |
21 |
|
T13 |
76 |
four_bytes |
3485 |
1 |
|
|
T18 |
89 |
|
T19 |
19 |
|
T13 |
97 |
three_bytes |
3353 |
1 |
|
|
T18 |
77 |
|
T19 |
12 |
|
T13 |
92 |
two_bytes |
3390 |
1 |
|
|
T18 |
74 |
|
T19 |
13 |
|
T13 |
79 |
one_byte |
3482 |
1 |
|
|
T18 |
66 |
|
T19 |
15 |
|
T13 |
83 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176143 |
1 |
|
|
T2 |
105 |
|
T3 |
84 |
|
T6 |
135 |
auto[1] |
3298 |
1 |
|
|
T2 |
4 |
|
T3 |
2 |
|
T6 |
4 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
179441 |
1 |
|
|
T2 |
109 |
|
T3 |
86 |
|
T6 |
139 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
179438 |
1 |
|
|
T2 |
109 |
|
T3 |
86 |
|
T6 |
139 |
auto[1] |
3 |
1 |
|
|
T168 |
1 |
|
T169 |
1 |
|
T170 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1076 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T6 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3298 |
1 |
|
|
T2 |
4 |
|
T3 |
2 |
|
T6 |
4 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
181405 |
1 |
|
|
T2 |
59 |
|
T3 |
15 |
|
T6 |
427 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
101834 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
55207 |
1 |
|
|
T2 |
58 |
|
T3 |
14 |
|
T6 |
421 |
seven_bytes |
3449 |
1 |
|
|
T18 |
54 |
|
T19 |
16 |
|
T13 |
85 |
six_bytes |
3446 |
1 |
|
|
T18 |
43 |
|
T19 |
18 |
|
T13 |
70 |
five_bytes |
3517 |
1 |
|
|
T18 |
61 |
|
T19 |
18 |
|
T13 |
60 |
four_bytes |
3512 |
1 |
|
|
T18 |
45 |
|
T19 |
10 |
|
T13 |
66 |
three_bytes |
3526 |
1 |
|
|
T18 |
46 |
|
T19 |
15 |
|
T13 |
66 |
two_bytes |
3548 |
1 |
|
|
T18 |
38 |
|
T19 |
11 |
|
T13 |
68 |
one_byte |
3366 |
1 |
|
|
T18 |
43 |
|
T19 |
9 |
|
T13 |
66 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
178095 |
1 |
|
|
T2 |
57 |
|
T3 |
13 |
|
T6 |
415 |
auto[1] |
3310 |
1 |
|
|
T2 |
2 |
|
T3 |
2 |
|
T6 |
12 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
181405 |
1 |
|
|
T2 |
59 |
|
T3 |
15 |
|
T6 |
427 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
181395 |
1 |
|
|
T2 |
59 |
|
T3 |
15 |
|
T6 |
427 |
auto[1] |
10 |
1 |
|
|
T36 |
1 |
|
T19 |
1 |
|
T99 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1054 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
6 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3310 |
1 |
|
|
T2 |
2 |
|
T3 |
2 |
|
T6 |
12 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
353871 |
1 |
|
|
T2 |
246 |
|
T3 |
115 |
|
T6 |
99 |
auto[1] |
439 |
1 |
|
|
T5 |
71 |
|
T7 |
100 |
|
T8 |
2 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
198584 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
108593 |
1 |
|
|
T2 |
242 |
|
T3 |
113 |
|
T6 |
97 |
seven_bytes |
6779 |
1 |
|
|
T18 |
90 |
|
T19 |
32 |
|
T13 |
49 |
six_bytes |
6713 |
1 |
|
|
T18 |
86 |
|
T19 |
29 |
|
T13 |
41 |
five_bytes |
6732 |
1 |
|
|
T18 |
93 |
|
T19 |
31 |
|
T13 |
54 |
four_bytes |
6665 |
1 |
|
|
T18 |
94 |
|
T19 |
33 |
|
T13 |
47 |
three_bytes |
6771 |
1 |
|
|
T18 |
83 |
|
T19 |
36 |
|
T13 |
49 |
two_bytes |
6729 |
1 |
|
|
T18 |
87 |
|
T19 |
25 |
|
T13 |
57 |
one_byte |
6744 |
1 |
|
|
T18 |
89 |
|
T19 |
28 |
|
T13 |
48 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
347670 |
1 |
|
|
T2 |
238 |
|
T3 |
111 |
|
T6 |
95 |
auto[1] |
6640 |
1 |
|
|
T2 |
8 |
|
T3 |
4 |
|
T6 |
4 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
354310 |
1 |
|
|
T2 |
246 |
|
T3 |
115 |
|
T6 |
99 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
354283 |
1 |
|
|
T2 |
246 |
|
T3 |
115 |
|
T6 |
99 |
auto[1] |
27 |
1 |
|
|
T5 |
1 |
|
T63 |
1 |
|
T171 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2157 |
1 |
|
|
T2 |
4 |
|
T3 |
2 |
|
T6 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6640 |
1 |
|
|
T2 |
8 |
|
T3 |
4 |
|
T6 |
4 |