Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

154641190

1

T1

460

T2

11148

T3

52695

full_word

114681132

1

T1

406

T2

13974

T3

73099

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	269322052	1			T1	866		T2	25122		T3	125794
auto[TlIntgErrCmd]	87	1			T117	3		T118	5		T119	7
auto[TlIntgErrData]	95	1			T117	2		T118	4		T119	6
auto[TlIntgErrBoth]	88	1			T117	5		T118	1		T119	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

140569403

1

T1

456

T2

16732

T3

81919

auto[1]

128752919

1

T1

410

T2

8390

T3

43875

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	95643929	1			T1	443		T2	7313		T3	32876
auto[TlIntgErrNone]	partial	auto[1]	58997005	1			T1	17		T2	3835		T3	19819
auto[TlIntgErrNone]	full_word	auto[0]	44925349	1			T1	13		T2	9419		T3	49043
auto[TlIntgErrNone]	full_word	auto[1]	69755769	1			T1	393		T2	4555		T3	24056
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T117	1		T118	4		T119	1
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T117	2		T118	1		T119	6
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T172	2		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	51	1			T117	2		T118	4		T119	3
auto[TlIntgErrData]	partial	auto[1]	37	1			T119	3		T173	3		T174	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T175	1		T176	1		T177	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T174	1		T178	2		T179	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T117	2		T118	1		T119	4
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T117	2		T119	3		T174	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T117	1		T176	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T174	1		T180	1		T175	1