Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	1412918630	182483	0	0
RunThenComplete_M	1412918630	1993105	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1412918630	182483	0	0
T1	38319	7	0	0
T2	99422	51	0	0
T3	136683	125	0	0
T15	275921	188	0	0
T20	372746	118	0	0
T30	492650	168	0	0
T31	28822	9	0	0
T32	615156	374	0	0
T33	528099	2265	0	0
T34	39706	12	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1412918630	1993105	0	0
T1	38319	21	0	0
T2	99422	192	0	0
T3	136683	694	0	0
T15	275921	7227	0	0
T20	372746	636	0	0
T30	492650	889	0	0
T31	28822	31	0	0
T32	615156	5526	0	0
T33	528099	12979	0	0
T34	39706	62	0	0