Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1414145233	141169	0	0
entropy_period_rd_A	1414145233	770	0	0
intr_enable_rd_A	1414145233	1170	0	0
prefix_0_rd_A	1414145233	864	0	0
prefix_10_rd_A	1414145233	902	0	0
prefix_1_rd_A	1414145233	770	0	0
prefix_2_rd_A	1414145233	841	0	0
prefix_3_rd_A	1414145233	820	0	0
prefix_4_rd_A	1414145233	799	0	0
prefix_5_rd_A	1414145233	837	0	0
prefix_6_rd_A	1414145233	884	0	0
prefix_7_rd_A	1414145233	736	0	0
prefix_8_rd_A	1414145233	923	0	0
prefix_9_rd_A	1414145233	791	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1414145233	141169	0	0
T48	2615	0	0	0
T52	234755	21176	0	0
T53	0	67378	0	0
T75	0	26057	0	0
T118	0	1	0	0
T124	0	23358	0	0
T125	0	82	0	0
T126	0	138	0	0
T127	0	3	0	0
T129	0	269	0	0
T130	140850	0	0	0
T131	565971	0	0	0
T132	113678	0	0	0
T133	183153	0	0	0
T134	130118	0	0	0
T135	19733	0	0	0
T136	923	0	0	0
T137	102198	0	0	0
T138	0	195	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1414145233	770	0	0
T48	2615	0	0	0
T52	234755	29	0	0
T86	0	16	0	0
T127	0	12	0	0
T130	140850	0	0	0
T131	565971	0	0	0
T132	113678	0	0	0
T133	183153	0	0	0
T134	130118	0	0	0
T135	19733	0	0	0
T136	923	0	0	0
T137	102198	0	0	0
T149	0	30	0	0
T150	0	6	0	0
T151	0	3	0	0
T152	0	3	0	0
T153	0	28	0	0
T154	0	30	0	0
T155	0	14	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1414145233	1170	0	0
T48	2615	0	0	0
T52	234755	6	0	0
T86	0	17	0	0
T95	0	1	0	0
T127	0	26	0	0
T130	140850	0	0	0
T131	565971	0	0	0
T132	113678	0	0	0
T133	183153	0	0	0
T134	130118	0	0	0
T135	19733	0	0	0
T136	923	0	0	0
T137	102198	0	0	0
T149	0	17	0	0
T150	0	8	0	0
T151	0	13	0	0
T152	0	8	0	0
T156	0	9	0	0
T157	0	29	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1414145233	864	0	0
T48	2615	0	0	0
T52	234755	56	0	0
T86	0	8	0	0
T95	0	8	0	0
T127	0	20	0	0
T130	140850	0	0	0
T131	565971	0	0	0
T132	113678	0	0	0
T133	183153	0	0	0
T134	130118	0	0	0
T135	19733	0	0	0
T136	923	0	0	0
T137	102198	0	0	0
T149	0	45	0	0
T150	0	24	0	0
T151	0	2	0	0
T152	0	3	0	0
T153	0	55	0	0
T154	0	26	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1414145233	902	0	0
T48	2615	0	0	0
T52	234755	47	0	0
T86	0	11	0	0
T95	0	3	0	0
T126	0	6	0	0
T127	0	30	0	0
T130	140850	0	0	0
T131	565971	0	0	0
T132	113678	0	0	0
T133	183153	0	0	0
T134	130118	0	0	0
T135	19733	0	0	0
T136	923	0	0	0
T137	102198	0	0	0
T149	0	71	0	0
T150	0	16	0	0
T151	0	9	0	0
T152	0	9	0	0
T153	0	44	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1414145233	770	0	0
T48	2615	0	0	0
T52	234755	42	0	0
T86	0	10	0	0
T95	0	6	0	0
T127	0	12	0	0
T130	140850	0	0	0
T131	565971	0	0	0
T132	113678	0	0	0
T133	183153	0	0	0
T134	130118	0	0	0
T135	19733	0	0	0
T136	923	0	0	0
T137	102198	0	0	0
T149	0	31	0	0
T150	0	3	0	0
T152	0	1	0	0
T153	0	11	0	0
T154	0	26	0	0
T155	0	3	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1414145233	841	0	0
T48	2615	0	0	0
T52	234755	10	0	0
T86	0	12	0	0
T95	0	9	0	0
T126	0	9	0	0
T127	0	16	0	0
T130	140850	0	0	0
T131	565971	0	0	0
T132	113678	0	0	0
T133	183153	0	0	0
T134	130118	0	0	0
T135	19733	0	0	0
T136	923	0	0	0
T137	102198	0	0	0
T149	0	13	0	0
T150	0	20	0	0
T151	0	6	0	0
T152	0	8	0	0
T153	0	33	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1414145233	820	0	0
T48	2615	0	0	0
T52	234755	29	0	0
T86	0	6	0	0
T95	0	3	0	0
T127	0	17	0	0
T130	140850	0	0	0
T131	565971	0	0	0
T132	113678	0	0	0
T133	183153	0	0	0
T134	130118	0	0	0
T135	19733	0	0	0
T136	923	0	0	0
T137	102198	0	0	0
T149	0	24	0	0
T150	0	14	0	0
T152	0	6	0	0
T153	0	49	0	0
T154	0	1	0	0
T155	0	4	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1414145233	799	0	0
T48	2615	0	0	0
T52	234755	20	0	0
T86	0	24	0	0
T95	0	7	0	0
T127	0	12	0	0
T130	140850	0	0	0
T131	565971	0	0	0
T132	113678	0	0	0
T133	183153	0	0	0
T134	130118	0	0	0
T135	19733	0	0	0
T136	923	0	0	0
T137	102198	0	0	0
T149	0	36	0	0
T151	0	9	0	0
T153	0	103	0	0
T154	0	16	0	0
T155	0	8	0	0
T158	0	23	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1414145233	837	0	0
T48	2615	0	0	0
T52	234755	10	0	0
T86	0	11	0	0
T95	0	2	0	0
T127	0	9	0	0
T130	140850	0	0	0
T131	565971	0	0	0
T132	113678	0	0	0
T133	183153	0	0	0
T134	130118	0	0	0
T135	19733	0	0	0
T136	923	0	0	0
T137	102198	0	0	0
T149	0	88	0	0
T150	0	18	0	0
T151	0	6	0	0
T153	0	52	0	0
T154	0	3	0	0
T155	0	12	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1414145233	884	0	0
T48	2615	0	0	0
T52	234755	42	0	0
T86	0	10	0	0
T95	0	6	0	0
T127	0	16	0	0
T130	140850	0	0	0
T131	565971	0	0	0
T132	113678	0	0	0
T133	183153	0	0	0
T134	130118	0	0	0
T135	19733	0	0	0
T136	923	0	0	0
T137	102198	0	0	0
T149	0	33	0	0
T150	0	15	0	0
T151	0	9	0	0
T152	0	5	0	0
T153	0	44	0	0
T154	0	34	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1414145233	736	0	0
T48	2615	0	0	0
T52	234755	44	0	0
T86	0	14	0	0
T95	0	2	0	0
T127	0	6	0	0
T130	140850	0	0	0
T131	565971	0	0	0
T132	113678	0	0	0
T133	183153	0	0	0
T134	130118	0	0	0
T135	19733	0	0	0
T136	923	0	0	0
T137	102198	0	0	0
T149	0	47	0	0
T150	0	11	0	0
T151	0	3	0	0
T152	0	8	0	0
T153	0	46	0	0
T154	0	2	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1414145233	923	0	0
T48	2615	0	0	0
T52	234755	42	0	0
T86	0	10	0	0
T95	0	1	0	0
T127	0	19	0	0
T130	140850	0	0	0
T131	565971	0	0	0
T132	113678	0	0	0
T133	183153	0	0	0
T134	130118	0	0	0
T135	19733	0	0	0
T136	923	0	0	0
T137	102198	0	0	0
T149	0	28	0	0
T150	0	5	0	0
T152	0	7	0	0
T153	0	41	0	0
T154	0	21	0	0
T155	0	15	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1414145233	791	0	0
T48	2615	0	0	0
T52	234755	38	0	0
T86	0	17	0	0
T95	0	1	0	0
T127	0	22	0	0
T130	140850	0	0	0
T131	565971	0	0	0
T132	113678	0	0	0
T133	183153	0	0	0
T134	130118	0	0	0
T135	19733	0	0	0
T136	923	0	0	0
T137	102198	0	0	0
T149	0	46	0	0
T151	0	6	0	0
T152	0	9	0	0
T153	0	35	0	0
T154	0	31	0	0
T155	0	6	0	0