Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	55994555	1			T1	15477		T2	2866		T15	931
all_values[1]	55994555	1			T1	15477		T2	2866		T15	931
all_values[2]	55994555	1			T1	15477		T2	2866		T15	931

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

504572

1

T1

585

T2

1089

T15

161

auto[1]

167479093

1

T1

45846

T2

7509

T15

2632

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

167223939

1

T1

45393

T2

8508

T15

2775

auto[1]

759726

1

T1

1038

T2

90

T15

18

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	164315	1			T1	410		T7	2414		T19	223
all_values[0]	auto[0]	auto[1]	1793	1			T1	8		T7	18		T19	6
all_values[0]	auto[1]	auto[0]	55576998	1			T1	14721		T2	2836		T15	925
all_values[0]	auto[1]	auto[1]	251449	1			T1	338		T2	30		T15	6
all_values[1]	auto[0]	auto[0]	178558	1			T1	47		T2	745		T15	160
all_values[1]	auto[0]	auto[1]	1462	1			T1	5		T2	9		T15	1
all_values[1]	auto[1]	auto[0]	55562755	1			T1	15084		T2	2091		T15	765
all_values[1]	auto[1]	auto[1]	251780	1			T1	341		T2	21		T15	5
all_values[2]	auto[0]	auto[0]	157127	1			T1	111		T2	331		T30	2
all_values[2]	auto[0]	auto[1]	1317	1			T1	4		T2	4		T30	1
all_values[2]	auto[1]	auto[0]	55584186	1			T1	15020		T2	2505		T15	925
all_values[2]	auto[1]	auto[1]	251925	1			T1	342		T2	26		T15	6