Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176878 |
1 |
|
|
T1 |
188 |
|
T2 |
2 |
|
T15 |
8 |
auto[1] |
174940 |
1 |
|
|
T1 |
384 |
|
T2 |
44 |
|
T7 |
130 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
88326 |
1 |
|
|
T1 |
165 |
|
T2 |
7 |
|
T30 |
102 |
lower_val |
87041 |
1 |
|
|
T1 |
114 |
|
T2 |
16 |
|
T15 |
3 |
zero_val |
1352 |
1 |
|
|
T1 |
8 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
131990 |
1 |
|
|
T1 |
200 |
|
T2 |
8 |
|
T15 |
4 |
lower_val |
131556 |
1 |
|
|
T1 |
194 |
|
T2 |
16 |
|
T15 |
4 |
zero_val |
88272 |
1 |
|
|
T1 |
178 |
|
T2 |
22 |
|
T7 |
74 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
22215 |
1 |
|
|
T1 |
23 |
|
T30 |
49 |
|
T31 |
32 |
higher_val |
higher_val |
auto[1] |
10837 |
1 |
|
|
T1 |
24 |
|
T2 |
2 |
|
T7 |
12 |
higher_val |
lower_val |
auto[0] |
22038 |
1 |
|
|
T1 |
26 |
|
T30 |
53 |
|
T31 |
28 |
higher_val |
lower_val |
auto[1] |
11019 |
1 |
|
|
T1 |
35 |
|
T2 |
4 |
|
T7 |
10 |
higher_val |
zero_val |
auto[0] |
78 |
1 |
|
|
T1 |
1 |
|
T17 |
1 |
|
T186 |
1 |
higher_val |
zero_val |
auto[1] |
22139 |
1 |
|
|
T1 |
56 |
|
T2 |
1 |
|
T7 |
13 |
lower_val |
higher_val |
auto[0] |
21909 |
1 |
|
|
T1 |
25 |
|
T15 |
1 |
|
T30 |
69 |
lower_val |
higher_val |
auto[1] |
10855 |
1 |
|
|
T1 |
23 |
|
T2 |
2 |
|
T7 |
9 |
lower_val |
lower_val |
auto[0] |
21791 |
1 |
|
|
T1 |
21 |
|
T15 |
2 |
|
T30 |
71 |
lower_val |
lower_val |
auto[1] |
10784 |
1 |
|
|
T1 |
15 |
|
T2 |
5 |
|
T7 |
6 |
lower_val |
zero_val |
auto[0] |
68 |
1 |
|
|
T77 |
1 |
|
T14 |
2 |
|
T91 |
1 |
lower_val |
zero_val |
auto[1] |
21634 |
1 |
|
|
T1 |
30 |
|
T2 |
9 |
|
T7 |
22 |
zero_val |
higher_val |
auto[0] |
425 |
1 |
|
|
T1 |
1 |
|
T30 |
1 |
|
T31 |
1 |
zero_val |
higher_val |
auto[1] |
79 |
1 |
|
|
T1 |
2 |
|
T7 |
1 |
|
T18 |
3 |
zero_val |
lower_val |
auto[0] |
409 |
1 |
|
|
T15 |
1 |
|
T30 |
2 |
|
T7 |
2 |
zero_val |
lower_val |
auto[1] |
83 |
1 |
|
|
T77 |
1 |
|
T187 |
1 |
|
T18 |
1 |
zero_val |
zero_val |
auto[0] |
230 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T36 |
1 |
zero_val |
zero_val |
auto[1] |
126 |
1 |
|
|
T1 |
4 |
|
T7 |
2 |
|
T77 |
1 |