Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	55994555	1			T1	15477		T2	2866		T15	931
all_pins[1]	55994555	1			T1	15477		T2	2866		T15	931
all_pins[2]	55994555	1			T1	15477		T2	2866		T15	931

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	167420061	1			T1	43490		T2	8418		T15	2786
values[0x1]	563604	1			T1	2941		T2	180		T15	7
transitions[0x0=>0x1]	561483	1			T1	2927		T2	180		T15	7
transitions[0x1=>0x0]	561516	1			T1	2927		T2	180		T15	7

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	55743106	1			T1	15139		T2	2836		T15	925
all_pins[0]	values[0x1]	251449	1			T1	338		T2	30		T15	6
all_pins[0]	transitions[0x0=>0x1]	251438	1			T1	338		T2	30		T15	6
all_pins[0]	transitions[0x1=>0x0]	5553	1			T1	6		T2	3		T15	1
all_pins[1]	values[0x0]	55988991	1			T1	15471		T2	2863		T15	930
all_pins[1]	values[0x1]	5564	1			T1	6		T2	3		T15	1
all_pins[1]	transitions[0x0=>0x1]	5312	1			T1	6		T2	3		T15	1
all_pins[1]	transitions[0x1=>0x0]	306339	1			T1	2597		T2	147		T7	10409
all_pins[2]	values[0x0]	55687964	1			T1	12880		T2	2719		T15	931
all_pins[2]	values[0x1]	306591	1			T1	2597		T2	147		T7	10432
all_pins[2]	transitions[0x0=>0x1]	304733	1			T1	2583		T2	147		T7	10356
all_pins[2]	transitions[0x1=>0x0]	249624	1			T1	324		T2	30		T15	6