Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	614	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5091	1			T1	25		T31	19		T7	26
len_601_800	11536	1			T1	70		T2	12		T15	3
len_401_600	7724	1			T1	48		T2	2		T31	30
len_201_400	8404	1			T1	21		T2	1		T15	1
len_65_200	26152	1			T1	20		T31	9		T7	16
len_min_for_xof_require_squeeze	351	1			T1	1		T7	1		T188	10
len_keccak_block_sizes[72]	244	1			T1	1		T75	1		T188	5
len_keccak_block_sizes[104]	253	1			T75	1		T188	5		T189	9
len_keccak_block_sizes[136]	256	1			T188	5		T189	9		T190	1
len_keccak_block_sizes[144]	128	1			T75	1		T188	5		T190	1
len_keccak_block_sizes[168]	116	1			T188	5		T191	5		T192	5
len_datapath_width	13504	1			T1	12		T30	246		T31	2
len_2_63	101180	1			T1	84		T2	1		T31	7
len_1	52	1			T75	1		T18	1		T193	2