Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7699236 |
1 |
|
|
T1 |
34141 |
|
T2 |
3518 |
|
T15 |
633 |
auto[1] |
7699184 |
1 |
|
|
T1 |
34141 |
|
T2 |
3518 |
|
T15 |
633 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
15286565 |
1 |
|
|
T1 |
67978 |
|
T2 |
7010 |
|
T15 |
1258 |
triple_byte_access |
37114 |
1 |
|
|
T1 |
90 |
|
T2 |
14 |
|
T15 |
4 |
halfword_access |
37454 |
1 |
|
|
T1 |
102 |
|
T2 |
8 |
|
T15 |
4 |
byte_access |
37287 |
1 |
|
|
T1 |
112 |
|
T2 |
4 |
|
T31 |
84 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
7643308 |
1 |
|
|
T1 |
33989 |
|
T2 |
3505 |
|
T15 |
629 |
auto[0] |
triple_byte_access |
18557 |
1 |
|
|
T1 |
45 |
|
T2 |
7 |
|
T15 |
2 |
auto[0] |
halfword_access |
18727 |
1 |
|
|
T1 |
51 |
|
T2 |
4 |
|
T15 |
2 |
auto[0] |
byte_access |
18644 |
1 |
|
|
T1 |
56 |
|
T2 |
2 |
|
T31 |
42 |
auto[1] |
word_access |
7643257 |
1 |
|
|
T1 |
33989 |
|
T2 |
3505 |
|
T15 |
629 |
auto[1] |
triple_byte_access |
18557 |
1 |
|
|
T1 |
45 |
|
T2 |
7 |
|
T15 |
2 |
auto[1] |
halfword_access |
18727 |
1 |
|
|
T1 |
51 |
|
T2 |
4 |
|
T15 |
2 |
auto[1] |
byte_access |
18643 |
1 |
|
|
T1 |
56 |
|
T2 |
2 |
|
T31 |
42 |