Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 293 1 T120 7 T121 4 T162 4
all_values[1] 293 1 T120 7 T121 4 T162 4
all_values[2] 293 1 T120 7 T121 4 T162 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 505 1 T120 12 T121 11 T162 9
auto[1] 374 1 T120 9 T121 1 T162 3


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 420 1 T120 7 T121 4 T162 8
auto[1] 459 1 T120 14 T121 8 T162 4


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 526 1 T120 9 T121 4 T162 9
auto[1] 353 1 T120 12 T121 8 T162 3


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 77 1 T120 1 T121 1 T162 1
all_values[0] auto[0] auto[0] auto[1] 27 1 T120 1 T162 1 T156 1
all_values[0] auto[0] auto[1] auto[0] 57 1 T120 1 T121 1 T156 1
all_values[0] auto[0] auto[1] auto[1] 21 1 T163 1 T164 1 T165 1
all_values[0] auto[1] auto[0] auto[1] 69 1 T120 1 T121 2 T162 2
all_values[0] auto[1] auto[1] auto[1] 42 1 T120 3 T163 2 T166 2
all_values[1] auto[0] auto[0] auto[0] 93 1 T120 4 T121 1 T162 3
all_values[1] auto[0] auto[1] auto[0] 81 1 T156 1 T163 2 T157 2
all_values[1] auto[1] auto[0] auto[1] 76 1 T120 1 T121 3 T162 1
all_values[1] auto[1] auto[1] auto[1] 43 1 T120 2 T157 1 T166 2
all_values[2] auto[0] auto[0] auto[0] 66 1 T120 1 T121 1 T162 1
all_values[2] auto[0] auto[0] auto[1] 25 1 T157 1 T164 1 T167 1
all_values[2] auto[0] auto[1] auto[0] 46 1 T162 3 T156 1 T163 1
all_values[2] auto[0] auto[1] auto[1] 33 1 T120 1 T166 1 T167 1
all_values[2] auto[1] auto[0] auto[1] 72 1 T120 3 T121 3 T156 2
all_values[2] auto[1] auto[1] auto[1] 51 1 T120 2 T156 1 T166 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%