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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.30 97.89 92.55 99.89 77.46 95.53 98.89 97.88


Total test records in report: 1132
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T1013 /workspace/coverage/cover_reg_top/29.kmac_intr_test.498727353 Jul 29 04:54:46 PM PDT 24 Jul 29 04:54:47 PM PDT 24 72762434 ps
T127 /workspace/coverage/cover_reg_top/7.kmac_tl_errors.2172102372 Jul 29 04:54:35 PM PDT 24 Jul 29 04:54:38 PM PDT 24 94179403 ps
T1014 /workspace/coverage/cover_reg_top/12.kmac_intr_test.1698984680 Jul 29 04:54:36 PM PDT 24 Jul 29 04:54:37 PM PDT 24 12484146 ps
T89 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.4099831173 Jul 29 04:54:36 PM PDT 24 Jul 29 04:54:39 PM PDT 24 51236601 ps
T184 /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.416012943 Jul 29 04:54:49 PM PDT 24 Jul 29 04:54:54 PM PDT 24 1042646996 ps
T1015 /workspace/coverage/cover_reg_top/7.kmac_csr_rw.234376585 Jul 29 04:54:20 PM PDT 24 Jul 29 04:54:21 PM PDT 24 97849691 ps
T1016 /workspace/coverage/cover_reg_top/4.kmac_intr_test.1204011794 Jul 29 04:54:34 PM PDT 24 Jul 29 04:54:35 PM PDT 24 31517505 ps
T1017 /workspace/coverage/cover_reg_top/13.kmac_intr_test.2685260754 Jul 29 04:54:41 PM PDT 24 Jul 29 04:54:42 PM PDT 24 78661272 ps
T1018 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.416911782 Jul 29 04:54:31 PM PDT 24 Jul 29 04:54:33 PM PDT 24 66506579 ps
T1019 /workspace/coverage/cover_reg_top/11.kmac_intr_test.3228311596 Jul 29 04:54:34 PM PDT 24 Jul 29 04:54:35 PM PDT 24 17998281 ps
T1020 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2126403441 Jul 29 04:54:51 PM PDT 24 Jul 29 04:54:52 PM PDT 24 60322064 ps
T1021 /workspace/coverage/cover_reg_top/6.kmac_intr_test.374892130 Jul 29 04:54:41 PM PDT 24 Jul 29 04:54:42 PM PDT 24 52289758 ps
T1022 /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2324881183 Jul 29 04:54:07 PM PDT 24 Jul 29 04:54:09 PM PDT 24 207434199 ps
T183 /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.85945340 Jul 29 04:54:44 PM PDT 24 Jul 29 04:54:49 PM PDT 24 239622656 ps
T1023 /workspace/coverage/cover_reg_top/27.kmac_intr_test.96626901 Jul 29 04:54:54 PM PDT 24 Jul 29 04:54:55 PM PDT 24 49609418 ps
T1024 /workspace/coverage/cover_reg_top/26.kmac_intr_test.1241238781 Jul 29 04:54:48 PM PDT 24 Jul 29 04:54:49 PM PDT 24 14746860 ps
T1025 /workspace/coverage/cover_reg_top/8.kmac_csr_rw.529579490 Jul 29 04:54:44 PM PDT 24 Jul 29 04:54:45 PM PDT 24 63871746 ps
T131 /workspace/coverage/cover_reg_top/1.kmac_tl_errors.1787182821 Jul 29 04:54:29 PM PDT 24 Jul 29 04:54:30 PM PDT 24 41888107 ps
T1026 /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.4036040816 Jul 29 04:55:08 PM PDT 24 Jul 29 04:55:10 PM PDT 24 609213677 ps
T1027 /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.473953994 Jul 29 04:54:43 PM PDT 24 Jul 29 04:54:45 PM PDT 24 107855966 ps
T124 /workspace/coverage/cover_reg_top/15.kmac_tl_errors.710495847 Jul 29 04:54:48 PM PDT 24 Jul 29 04:54:50 PM PDT 24 74250322 ps
T1028 /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.2684133593 Jul 29 04:54:47 PM PDT 24 Jul 29 04:54:49 PM PDT 24 189265089 ps
T1029 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.2958419661 Jul 29 04:54:19 PM PDT 24 Jul 29 04:54:20 PM PDT 24 70340955 ps
T1030 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.3858160018 Jul 29 04:54:56 PM PDT 24 Jul 29 04:54:58 PM PDT 24 71602626 ps
T1031 /workspace/coverage/cover_reg_top/4.kmac_tl_errors.960639022 Jul 29 04:54:24 PM PDT 24 Jul 29 04:54:28 PM PDT 24 304214161 ps
T1032 /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.3598711487 Jul 29 04:54:45 PM PDT 24 Jul 29 04:54:47 PM PDT 24 77981289 ps
T1033 /workspace/coverage/cover_reg_top/7.kmac_intr_test.1858249002 Jul 29 04:54:42 PM PDT 24 Jul 29 04:54:43 PM PDT 24 48129898 ps
T1034 /workspace/coverage/cover_reg_top/16.kmac_tl_errors.207082472 Jul 29 04:54:44 PM PDT 24 Jul 29 04:54:46 PM PDT 24 61765861 ps
T1035 /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.2693185436 Jul 29 04:54:56 PM PDT 24 Jul 29 04:54:57 PM PDT 24 102411174 ps
T1036 /workspace/coverage/cover_reg_top/47.kmac_intr_test.4082267276 Jul 29 04:54:53 PM PDT 24 Jul 29 04:54:53 PM PDT 24 47970504 ps
T1037 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2837646086 Jul 29 04:55:10 PM PDT 24 Jul 29 04:55:12 PM PDT 24 145374305 ps
T1038 /workspace/coverage/cover_reg_top/34.kmac_intr_test.665647620 Jul 29 04:54:53 PM PDT 24 Jul 29 04:54:54 PM PDT 24 14984596 ps
T1039 /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.4215537172 Jul 29 04:54:29 PM PDT 24 Jul 29 04:54:50 PM PDT 24 6007941342 ps
T1040 /workspace/coverage/cover_reg_top/11.kmac_csr_rw.3316461006 Jul 29 04:54:40 PM PDT 24 Jul 29 04:54:41 PM PDT 24 20930666 ps
T1041 /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.360948577 Jul 29 04:54:54 PM PDT 24 Jul 29 04:54:56 PM PDT 24 44661930 ps
T1042 /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.2761330305 Jul 29 04:54:48 PM PDT 24 Jul 29 04:54:50 PM PDT 24 79287720 ps
T1043 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3852579179 Jul 29 04:54:33 PM PDT 24 Jul 29 04:54:34 PM PDT 24 66967133 ps
T1044 /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.2143295522 Jul 29 04:54:47 PM PDT 24 Jul 29 04:54:55 PM PDT 24 564689076 ps
T1045 /workspace/coverage/cover_reg_top/10.kmac_csr_rw.3595679009 Jul 29 04:54:31 PM PDT 24 Jul 29 04:54:33 PM PDT 24 17324303 ps
T145 /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.2864124168 Jul 29 04:54:14 PM PDT 24 Jul 29 04:54:16 PM PDT 24 59667234 ps
T1046 /workspace/coverage/cover_reg_top/33.kmac_intr_test.1083780391 Jul 29 04:55:08 PM PDT 24 Jul 29 04:55:09 PM PDT 24 23514902 ps
T1047 /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3317369031 Jul 29 04:54:51 PM PDT 24 Jul 29 04:54:53 PM PDT 24 491475940 ps
T1048 /workspace/coverage/cover_reg_top/41.kmac_intr_test.1447255591 Jul 29 04:55:07 PM PDT 24 Jul 29 04:55:08 PM PDT 24 43693049 ps
T146 /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.4278197882 Jul 29 04:54:32 PM PDT 24 Jul 29 04:54:34 PM PDT 24 29012998 ps
T1049 /workspace/coverage/cover_reg_top/31.kmac_intr_test.3325187041 Jul 29 04:54:52 PM PDT 24 Jul 29 04:54:53 PM PDT 24 12800609 ps
T1050 /workspace/coverage/cover_reg_top/6.kmac_tl_errors.465963042 Jul 29 04:54:44 PM PDT 24 Jul 29 04:54:47 PM PDT 24 431527621 ps
T1051 /workspace/coverage/cover_reg_top/9.kmac_intr_test.689231667 Jul 29 04:54:34 PM PDT 24 Jul 29 04:54:34 PM PDT 24 19788368 ps
T1052 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2307971510 Jul 29 04:54:41 PM PDT 24 Jul 29 04:54:42 PM PDT 24 31515092 ps
T1053 /workspace/coverage/cover_reg_top/24.kmac_intr_test.1951022098 Jul 29 04:54:59 PM PDT 24 Jul 29 04:55:00 PM PDT 24 13231151 ps
T1054 /workspace/coverage/cover_reg_top/13.kmac_tl_errors.1188086686 Jul 29 04:54:38 PM PDT 24 Jul 29 04:54:41 PM PDT 24 55609088 ps
T1055 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.907531942 Jul 29 04:54:41 PM PDT 24 Jul 29 04:54:44 PM PDT 24 734066147 ps
T179 /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.4115372664 Jul 29 04:54:34 PM PDT 24 Jul 29 04:54:39 PM PDT 24 288663885 ps
T1056 /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2030791991 Jul 29 04:54:32 PM PDT 24 Jul 29 04:54:34 PM PDT 24 403715871 ps
T1057 /workspace/coverage/cover_reg_top/5.kmac_tl_errors.3500443153 Jul 29 04:54:26 PM PDT 24 Jul 29 04:54:29 PM PDT 24 87399168 ps
T1058 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.1078653333 Jul 29 04:54:35 PM PDT 24 Jul 29 04:54:37 PM PDT 24 45412695 ps
T1059 /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.643262434 Jul 29 04:54:47 PM PDT 24 Jul 29 04:54:49 PM PDT 24 357455608 ps
T1060 /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.1056687979 Jul 29 04:54:24 PM PDT 24 Jul 29 04:54:25 PM PDT 24 56979309 ps
T1061 /workspace/coverage/cover_reg_top/2.kmac_intr_test.2930273497 Jul 29 04:54:34 PM PDT 24 Jul 29 04:54:35 PM PDT 24 73102277 ps
T1062 /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3411418871 Jul 29 04:54:53 PM PDT 24 Jul 29 04:54:55 PM PDT 24 69141774 ps
T1063 /workspace/coverage/cover_reg_top/38.kmac_intr_test.3620067845 Jul 29 04:54:56 PM PDT 24 Jul 29 04:54:57 PM PDT 24 25932842 ps
T1064 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.3599167591 Jul 29 04:54:44 PM PDT 24 Jul 29 04:54:45 PM PDT 24 66892073 ps
T1065 /workspace/coverage/cover_reg_top/11.kmac_tl_errors.3567348578 Jul 29 04:54:56 PM PDT 24 Jul 29 04:54:59 PM PDT 24 236214915 ps
T1066 /workspace/coverage/cover_reg_top/9.kmac_csr_rw.4065681538 Jul 29 04:54:33 PM PDT 24 Jul 29 04:54:35 PM PDT 24 20436715 ps
T1067 /workspace/coverage/cover_reg_top/22.kmac_intr_test.1526985960 Jul 29 04:54:46 PM PDT 24 Jul 29 04:54:47 PM PDT 24 40259129 ps
T1068 /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2600984307 Jul 29 04:54:40 PM PDT 24 Jul 29 04:54:41 PM PDT 24 63406735 ps
T1069 /workspace/coverage/cover_reg_top/18.kmac_csr_rw.751049802 Jul 29 04:54:42 PM PDT 24 Jul 29 04:54:44 PM PDT 24 37449693 ps
T1070 /workspace/coverage/cover_reg_top/25.kmac_intr_test.1334509105 Jul 29 04:54:45 PM PDT 24 Jul 29 04:54:46 PM PDT 24 84289243 ps
T1071 /workspace/coverage/cover_reg_top/4.kmac_mem_walk.320746694 Jul 29 04:54:41 PM PDT 24 Jul 29 04:54:42 PM PDT 24 16386509 ps
T1072 /workspace/coverage/cover_reg_top/42.kmac_intr_test.1050754703 Jul 29 04:54:58 PM PDT 24 Jul 29 04:54:59 PM PDT 24 22992884 ps
T1073 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.803425091 Jul 29 04:54:21 PM PDT 24 Jul 29 04:54:22 PM PDT 24 41800713 ps
T1074 /workspace/coverage/cover_reg_top/39.kmac_intr_test.3358272829 Jul 29 04:54:59 PM PDT 24 Jul 29 04:55:00 PM PDT 24 24824033 ps
T1075 /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.2455459403 Jul 29 04:54:20 PM PDT 24 Jul 29 04:54:40 PM PDT 24 3844174283 ps
T1076 /workspace/coverage/cover_reg_top/36.kmac_intr_test.1979212402 Jul 29 04:54:55 PM PDT 24 Jul 29 04:54:56 PM PDT 24 13861501 ps
T1077 /workspace/coverage/cover_reg_top/40.kmac_intr_test.420475593 Jul 29 04:54:56 PM PDT 24 Jul 29 04:54:57 PM PDT 24 43695762 ps
T1078 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3576028464 Jul 29 04:54:41 PM PDT 24 Jul 29 04:54:42 PM PDT 24 57501512 ps
T1079 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.430413696 Jul 29 04:54:39 PM PDT 24 Jul 29 04:54:40 PM PDT 24 54788923 ps
T1080 /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.2746102632 Jul 29 04:54:31 PM PDT 24 Jul 29 04:54:34 PM PDT 24 377392631 ps
T1081 /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.917665584 Jul 29 04:54:34 PM PDT 24 Jul 29 04:54:36 PM PDT 24 158205531 ps
T1082 /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.3288448324 Jul 29 04:54:47 PM PDT 24 Jul 29 04:54:49 PM PDT 24 275999790 ps
T1083 /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2336267876 Jul 29 04:54:39 PM PDT 24 Jul 29 04:54:41 PM PDT 24 114287763 ps
T1084 /workspace/coverage/cover_reg_top/1.kmac_csr_rw.2319888821 Jul 29 04:54:22 PM PDT 24 Jul 29 04:54:24 PM PDT 24 17636268 ps
T1085 /workspace/coverage/cover_reg_top/5.kmac_intr_test.430215288 Jul 29 04:54:55 PM PDT 24 Jul 29 04:54:56 PM PDT 24 49567109 ps
T1086 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3891800193 Jul 29 04:54:49 PM PDT 24 Jul 29 04:54:50 PM PDT 24 95003783 ps
T1087 /workspace/coverage/cover_reg_top/49.kmac_intr_test.822823550 Jul 29 04:54:42 PM PDT 24 Jul 29 04:54:43 PM PDT 24 58032156 ps
T1088 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.3677957857 Jul 29 04:54:36 PM PDT 24 Jul 29 04:54:38 PM PDT 24 228347706 ps
T1089 /workspace/coverage/cover_reg_top/12.kmac_csr_rw.3706737090 Jul 29 04:54:42 PM PDT 24 Jul 29 04:54:43 PM PDT 24 37495828 ps
T1090 /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1399656517 Jul 29 04:54:50 PM PDT 24 Jul 29 04:54:53 PM PDT 24 546542890 ps
T1091 /workspace/coverage/cover_reg_top/6.kmac_csr_rw.1598786181 Jul 29 04:54:42 PM PDT 24 Jul 29 04:54:43 PM PDT 24 19757152 ps
T1092 /workspace/coverage/cover_reg_top/2.kmac_mem_walk.4285045150 Jul 29 04:54:07 PM PDT 24 Jul 29 04:54:08 PM PDT 24 33827032 ps
T1093 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.4108484844 Jul 29 04:54:03 PM PDT 24 Jul 29 04:54:05 PM PDT 24 123147789 ps
T1094 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2415336198 Jul 29 04:54:44 PM PDT 24 Jul 29 04:54:45 PM PDT 24 95393702 ps
T1095 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1656415824 Jul 29 04:54:52 PM PDT 24 Jul 29 04:54:53 PM PDT 24 38628967 ps
T1096 /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.3381857244 Jul 29 04:54:46 PM PDT 24 Jul 29 04:54:48 PM PDT 24 60871504 ps
T1097 /workspace/coverage/cover_reg_top/0.kmac_mem_walk.814910912 Jul 29 04:54:05 PM PDT 24 Jul 29 04:54:06 PM PDT 24 113842986 ps
T1098 /workspace/coverage/cover_reg_top/14.kmac_tl_errors.1174209085 Jul 29 04:54:52 PM PDT 24 Jul 29 04:54:59 PM PDT 24 116391502 ps
T147 /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.315149379 Jul 29 04:54:43 PM PDT 24 Jul 29 04:54:44 PM PDT 24 78454197 ps
T1099 /workspace/coverage/cover_reg_top/10.kmac_intr_test.570188802 Jul 29 04:54:37 PM PDT 24 Jul 29 04:54:38 PM PDT 24 82285720 ps
T1100 /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.575799113 Jul 29 04:54:42 PM PDT 24 Jul 29 04:54:45 PM PDT 24 37871777 ps
T1101 /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1626967970 Jul 29 04:54:40 PM PDT 24 Jul 29 04:54:50 PM PDT 24 1908117342 ps
T1102 /workspace/coverage/cover_reg_top/19.kmac_csr_rw.3859956514 Jul 29 04:54:54 PM PDT 24 Jul 29 04:54:55 PM PDT 24 20003340 ps
T1103 /workspace/coverage/cover_reg_top/19.kmac_tl_errors.4207053847 Jul 29 04:54:58 PM PDT 24 Jul 29 04:55:01 PM PDT 24 178340939 ps
T1104 /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.4098232045 Jul 29 04:54:43 PM PDT 24 Jul 29 04:54:45 PM PDT 24 189161471 ps
T1105 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.2992535082 Jul 29 04:54:36 PM PDT 24 Jul 29 04:54:38 PM PDT 24 110003819 ps
T1106 /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.55841516 Jul 29 04:54:21 PM PDT 24 Jul 29 04:54:27 PM PDT 24 270909316 ps
T1107 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3835540710 Jul 29 04:54:45 PM PDT 24 Jul 29 04:54:46 PM PDT 24 55122038 ps
T1108 /workspace/coverage/cover_reg_top/19.kmac_intr_test.1457868946 Jul 29 04:54:43 PM PDT 24 Jul 29 04:54:45 PM PDT 24 83383847 ps
T1109 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.1720804189 Jul 29 04:54:48 PM PDT 24 Jul 29 04:54:49 PM PDT 24 29913756 ps
T1110 /workspace/coverage/cover_reg_top/14.kmac_intr_test.2369197463 Jul 29 04:54:59 PM PDT 24 Jul 29 04:55:00 PM PDT 24 13781174 ps
T1111 /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.4282868573 Jul 29 04:54:44 PM PDT 24 Jul 29 04:54:47 PM PDT 24 162718164 ps
T1112 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.2187554284 Jul 29 04:54:18 PM PDT 24 Jul 29 04:54:20 PM PDT 24 116552778 ps
T168 /workspace/coverage/cover_reg_top/8.kmac_tl_errors.3409651519 Jul 29 04:54:47 PM PDT 24 Jul 29 04:54:50 PM PDT 24 200619591 ps
T1113 /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.1791979750 Jul 29 04:54:51 PM PDT 24 Jul 29 04:54:54 PM PDT 24 130072373 ps
T1114 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1427803463 Jul 29 04:54:36 PM PDT 24 Jul 29 04:54:38 PM PDT 24 142899705 ps
T1115 /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.267321045 Jul 29 04:54:42 PM PDT 24 Jul 29 04:54:44 PM PDT 24 39496179 ps
T1116 /workspace/coverage/cover_reg_top/12.kmac_tl_errors.3004370836 Jul 29 04:54:44 PM PDT 24 Jul 29 04:54:48 PM PDT 24 55453098 ps
T1117 /workspace/coverage/cover_reg_top/5.kmac_csr_rw.1838005482 Jul 29 04:54:35 PM PDT 24 Jul 29 04:54:37 PM PDT 24 21928809 ps
T1118 /workspace/coverage/cover_reg_top/13.kmac_csr_rw.46671355 Jul 29 04:54:40 PM PDT 24 Jul 29 04:54:41 PM PDT 24 19217648 ps
T1119 /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3774548583 Jul 29 04:54:39 PM PDT 24 Jul 29 04:54:42 PM PDT 24 175795467 ps
T1120 /workspace/coverage/cover_reg_top/35.kmac_intr_test.1980766802 Jul 29 04:55:00 PM PDT 24 Jul 29 04:55:01 PM PDT 24 27759933 ps
T1121 /workspace/coverage/cover_reg_top/45.kmac_intr_test.2440338817 Jul 29 04:55:02 PM PDT 24 Jul 29 04:55:03 PM PDT 24 16775374 ps
T1122 /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1804344707 Jul 29 04:54:07 PM PDT 24 Jul 29 04:54:08 PM PDT 24 33241424 ps
T182 /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.1988170160 Jul 29 04:54:27 PM PDT 24 Jul 29 04:54:30 PM PDT 24 53381933 ps
T1123 /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.3185834840 Jul 29 04:54:58 PM PDT 24 Jul 29 04:55:00 PM PDT 24 47658361 ps
T1124 /workspace/coverage/cover_reg_top/48.kmac_intr_test.3992687087 Jul 29 04:54:51 PM PDT 24 Jul 29 04:54:51 PM PDT 24 14378568 ps
T1125 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.2775847863 Jul 29 04:54:52 PM PDT 24 Jul 29 04:54:54 PM PDT 24 306676019 ps
T1126 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.2370901194 Jul 29 04:54:40 PM PDT 24 Jul 29 04:54:42 PM PDT 24 50825525 ps
T1127 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3084913407 Jul 29 04:54:52 PM PDT 24 Jul 29 04:54:53 PM PDT 24 113172772 ps
T1128 /workspace/coverage/cover_reg_top/37.kmac_intr_test.2117336623 Jul 29 04:54:51 PM PDT 24 Jul 29 04:54:52 PM PDT 24 38880139 ps
T1129 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.14904890 Jul 29 04:54:32 PM PDT 24 Jul 29 04:54:35 PM PDT 24 167773335 ps
T1130 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2242720043 Jul 29 04:54:46 PM PDT 24 Jul 29 04:54:48 PM PDT 24 130449107 ps
T1131 /workspace/coverage/cover_reg_top/2.kmac_csr_rw.674160304 Jul 29 04:54:40 PM PDT 24 Jul 29 04:54:41 PM PDT 24 18809712 ps
T1132 /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.2330327494 Jul 29 04:54:48 PM PDT 24 Jul 29 04:54:53 PM PDT 24 920237899 ps

Test location /workspace/coverage/default/31.kmac_stress_all.3750204903
Short name T1
Test name
Test status
Simulation time 28177901320 ps
CPU time 962.52 seconds
Started Jul 29 04:57:00 PM PDT 24
Finished Jul 29 05:13:03 PM PDT 24
Peak memory 398544 kb
Host smart-8528b603-35cc-4dd6-a659-ae5efac24005
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3750204903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.3750204903 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.1168413022
Short name T116
Test name
Test status
Simulation time 238477834 ps
CPU time 2.97 seconds
Started Jul 29 04:54:54 PM PDT 24
Finished Jul 29 04:54:57 PM PDT 24
Peak memory 215828 kb
Host smart-24f5037c-cb0a-41bc-9719-50cb278099d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168413022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.1168
413022 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/48.kmac_error.2099613867
Short name T20
Test name
Test status
Simulation time 88100581454 ps
CPU time 268.57 seconds
Started Jul 29 04:59:31 PM PDT 24
Finished Jul 29 05:04:00 PM PDT 24
Peak memory 462992 kb
Host smart-7fbd222f-5a53-495c-a50e-0615d4ec66fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099613867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.2099613867 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_lc_escalation.1560353698
Short name T12
Test name
Test status
Simulation time 585521016 ps
CPU time 18.67 seconds
Started Jul 29 04:57:17 PM PDT 24
Finished Jul 29 04:57:36 PM PDT 24
Peak memory 241892 kb
Host smart-c7dbc4e4-3f43-4a1d-9bc5-bead0957ca7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560353698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.1560353698 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/34.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_stress_all_with_rand_reset.4230122781
Short name T22
Test name
Test status
Simulation time 226076016331 ps
CPU time 693.33 seconds
Started Jul 29 04:55:43 PM PDT 24
Finished Jul 29 05:07:16 PM PDT 24
Peak memory 289236 kb
Host smart-a52abcf5-83f4-4ed2-9f19-94b61ea729dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4230122781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all_with_rand_reset.4230122781 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.kmac_sec_cm.673709041
Short name T28
Test name
Test status
Simulation time 7330051966 ps
CPU time 86.48 seconds
Started Jul 29 04:55:36 PM PDT 24
Finished Jul 29 04:57:03 PM PDT 24
Peak memory 289920 kb
Host smart-a28cb810-b10a-4d9e-8da4-af564c138b29
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673709041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.673709041 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.1683877021
Short name T85
Test name
Test status
Simulation time 46281228 ps
CPU time 1.37 seconds
Started Jul 29 04:54:48 PM PDT 24
Finished Jul 29 04:54:50 PM PDT 24
Peak memory 217284 kb
Host smart-842cc0d9-7e71-4901-a0af-5142d2e37231
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683877021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_
errors.1683877021 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/default/15.kmac_key_error.954307890
Short name T5
Test name
Test status
Simulation time 7941935131 ps
CPU time 9.19 seconds
Started Jul 29 04:56:24 PM PDT 24
Finished Jul 29 04:56:33 PM PDT 24
Peak memory 226660 kb
Host smart-d4f07e57-08cd-4adf-9e31-32794d2925c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954307890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.954307890 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_key_error/latest

Test location /workspace/coverage/default/35.kmac_lc_escalation.4288889250
Short name T40
Test name
Test status
Simulation time 66719328 ps
CPU time 1.91 seconds
Started Jul 29 04:57:24 PM PDT 24
Finished Jul 29 04:57:26 PM PDT 24
Peak memory 226724 kb
Host smart-a3e9c121-1437-423e-abff-5d196daa3c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288889250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.4288889250 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/35.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_lc_escalation.4245959436
Short name T39
Test name
Test status
Simulation time 103681521 ps
CPU time 1.46 seconds
Started Jul 29 04:55:48 PM PDT 24
Finished Jul 29 04:55:49 PM PDT 24
Peak memory 226736 kb
Host smart-f0193c68-9cd3-486f-bcca-106afc9bf71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245959436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.4245959436 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/3.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_entropy_ready_error.1273412999
Short name T9
Test name
Test status
Simulation time 3285228347 ps
CPU time 31.23 seconds
Started Jul 29 04:55:47 PM PDT 24
Finished Jul 29 04:56:18 PM PDT 24
Peak memory 221896 kb
Host smart-705ffc81-db4b-42fb-aad8-379206f9fe1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273412999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.1273412999 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.2949960988
Short name T992
Test name
Test status
Simulation time 17675508 ps
CPU time 0.8 seconds
Started Jul 29 04:54:15 PM PDT 24
Finished Jul 29 04:54:16 PM PDT 24
Peak memory 215624 kb
Host smart-6dde5205-43db-4b7a-89e3-fe9f328955ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949960988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.2949960988 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_intr_test/latest

Test location /workspace/coverage/default/11.kmac_entropy_mode_error.3856656151
Short name T69
Test name
Test status
Simulation time 46686031 ps
CPU time 1.17 seconds
Started Jul 29 04:56:03 PM PDT 24
Finished Jul 29 04:56:04 PM PDT 24
Peak memory 218624 kb
Host smart-28dc893f-e11b-4f43-9e62-c27056e70470
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3856656151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.3856656151 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/17.kmac_lc_escalation.524273856
Short name T24
Test name
Test status
Simulation time 1274134869 ps
CPU time 16.22 seconds
Started Jul 29 04:56:26 PM PDT 24
Finished Jul 29 04:56:42 PM PDT 24
Peak memory 235584 kb
Host smart-bae1f88a-8552-4b71-abf1-f1679cbdda80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524273856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.524273856 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/17.kmac_lc_escalation/latest

Test location /workspace/coverage/default/39.kmac_lc_escalation.1174036365
Short name T53
Test name
Test status
Simulation time 36672329 ps
CPU time 1.35 seconds
Started Jul 29 04:57:53 PM PDT 24
Finished Jul 29 04:57:55 PM PDT 24
Peak memory 226772 kb
Host smart-592a5da0-c96f-4a41-a369-b3b7b9287db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174036365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.1174036365 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/39.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.3015155710
Short name T86
Test name
Test status
Simulation time 49819180 ps
CPU time 2.47 seconds
Started Jul 29 04:54:45 PM PDT 24
Finished Jul 29 04:54:47 PM PDT 24
Peak memory 218712 kb
Host smart-ee7ab8ac-35a3-41a9-a9e0-6d050223ab11
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015155710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma
c_shadow_reg_errors_with_csr_rw.3015155710 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.kmac_edn_timeout_error.1414279627
Short name T34
Test name
Test status
Simulation time 27282487 ps
CPU time 0.91 seconds
Started Jul 29 04:56:22 PM PDT 24
Finished Jul 29 04:56:23 PM PDT 24
Peak memory 218352 kb
Host smart-a60dc57e-0961-4a0c-a89d-1520bd476f20
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1414279627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.1414279627 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_256.3282938777
Short name T188
Test name
Test status
Simulation time 55434498425 ps
CPU time 5507.12 seconds
Started Jul 29 04:56:41 PM PDT 24
Finished Jul 29 06:28:29 PM PDT 24
Peak memory 2225560 kb
Host smart-9f298f82-59ae-4b61-bf56-aa3fcadc4dec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3282938777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.3282938777 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.2864124168
Short name T145
Test name
Test status
Simulation time 59667234 ps
CPU time 1.33 seconds
Started Jul 29 04:54:14 PM PDT 24
Finished Jul 29 04:54:16 PM PDT 24
Peak memory 215864 kb
Host smart-7349c226-c11d-4f1e-be51-ed53380651ce
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864124168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia
l_access.2864124168 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest

Test location /workspace/coverage/default/16.kmac_lc_escalation.3664634539
Short name T74
Test name
Test status
Simulation time 70058580 ps
CPU time 1.26 seconds
Started Jul 29 04:56:14 PM PDT 24
Finished Jul 29 04:56:16 PM PDT 24
Peak memory 226728 kb
Host smart-b64aeebb-4946-486c-8a2e-d7f0c43a596c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664634539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.3664634539 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/16.kmac_lc_escalation/latest

Test location /workspace/coverage/default/6.kmac_error.3160294474
Short name T136
Test name
Test status
Simulation time 23374990020 ps
CPU time 301.17 seconds
Started Jul 29 04:55:51 PM PDT 24
Finished Jul 29 05:00:53 PM PDT 24
Peak memory 466416 kb
Host smart-f936e244-cf0a-43e7-9967-e8bc43a7db7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160294474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.3160294474 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_error/latest

Test location /workspace/coverage/default/10.kmac_alert_test.4256477383
Short name T93
Test name
Test status
Simulation time 46082793 ps
CPU time 0.9 seconds
Started Jul 29 04:56:08 PM PDT 24
Finished Jul 29 04:56:09 PM PDT 24
Peak memory 218380 kb
Host smart-5608ca63-3c71-4827-948c-5fa1b0eb4a43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256477383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.4256477383 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_alert_test/latest

Test location /workspace/coverage/default/25.kmac_lc_escalation.2202842074
Short name T44
Test name
Test status
Simulation time 39635947 ps
CPU time 1.36 seconds
Started Jul 29 04:56:45 PM PDT 24
Finished Jul 29 04:56:46 PM PDT 24
Peak memory 226776 kb
Host smart-5a3216f0-3fe0-46c0-8cbb-c34c064f0a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202842074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.2202842074 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/25.kmac_lc_escalation/latest

Test location /workspace/coverage/default/5.kmac_stress_all.1206845405
Short name T18
Test name
Test status
Simulation time 276775067105 ps
CPU time 2371.83 seconds
Started Jul 29 04:55:49 PM PDT 24
Finished Jul 29 05:35:22 PM PDT 24
Peak memory 1167688 kb
Host smart-b5743d6d-9d22-4bea-8fa5-c70ce146674a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1206845405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.1206845405 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.4115372664
Short name T179
Test name
Test status
Simulation time 288663885 ps
CPU time 4.84 seconds
Started Jul 29 04:54:34 PM PDT 24
Finished Jul 29 04:54:39 PM PDT 24
Peak memory 215960 kb
Host smart-d8aedc6d-5366-45ca-9373-e43a49e385d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115372664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.41153
72664 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.2436671492
Short name T167
Test name
Test status
Simulation time 16396105 ps
CPU time 0.78 seconds
Started Jul 29 04:54:59 PM PDT 24
Finished Jul 29 04:55:00 PM PDT 24
Peak memory 215720 kb
Host smart-c723e7c3-aa59-46e6-8701-c87a86177444
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436671492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.2436671492 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.342083857
Short name T118
Test name
Test status
Simulation time 477709174 ps
CPU time 5.01 seconds
Started Jul 29 04:54:32 PM PDT 24
Finished Jul 29 04:54:37 PM PDT 24
Peak memory 216020 kb
Host smart-3a463d40-cb39-46ad-ba82-e8a74387bc33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342083857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.342083
857 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.416012943
Short name T184
Test name
Test status
Simulation time 1042646996 ps
CPU time 5.03 seconds
Started Jul 29 04:54:49 PM PDT 24
Finished Jul 29 04:54:54 PM PDT 24
Peak memory 216020 kb
Host smart-9621b6ef-10fe-450f-a503-b0f2c9e3db5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416012943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.41601
2943 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/46.kmac_app.2933787289
Short name T171
Test name
Test status
Simulation time 16567608200 ps
CPU time 302.4 seconds
Started Jul 29 04:58:51 PM PDT 24
Finished Jul 29 05:03:54 PM PDT 24
Peak memory 310524 kb
Host smart-db57ec93-79e4-49c7-aed4-89c89cd70ed3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933787289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.2933787289 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/46.kmac_app/latest

Test location /workspace/coverage/default/49.kmac_stress_all.188938250
Short name T14
Test name
Test status
Simulation time 4464123351 ps
CPU time 366.35 seconds
Started Jul 29 04:59:50 PM PDT 24
Finished Jul 29 05:05:57 PM PDT 24
Peak memory 357536 kb
Host smart-5f22b653-e6ab-4627-be4a-c7fc2b7b8b6a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=188938250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.188938250 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all/latest

Test location /workspace/coverage/default/11.kmac_entropy_refresh.3792151425
Short name T62
Test name
Test status
Simulation time 13040276302 ps
CPU time 337.02 seconds
Started Jul 29 04:55:51 PM PDT 24
Finished Jul 29 05:01:28 PM PDT 24
Peak memory 429440 kb
Host smart-da5c119d-46e3-4ee8-a994-377c446d8e1f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792151425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.3
792151425 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_refresh/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.3803530585
Short name T988
Test name
Test status
Simulation time 288542614 ps
CPU time 4.34 seconds
Started Jul 29 04:54:04 PM PDT 24
Finished Jul 29 04:54:09 PM PDT 24
Peak memory 215844 kb
Host smart-839e3686-3b80-4a63-a8b1-e7e67ca8971b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803530585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.3803530
585 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.4215537172
Short name T1039
Test name
Test status
Simulation time 6007941342 ps
CPU time 21.2 seconds
Started Jul 29 04:54:29 PM PDT 24
Finished Jul 29 04:54:50 PM PDT 24
Peak memory 215988 kb
Host smart-fe879b60-699b-4c7d-a353-f8426053416a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215537172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.4215537
172 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1804344707
Short name T1122
Test name
Test status
Simulation time 33241424 ps
CPU time 0.97 seconds
Started Jul 29 04:54:07 PM PDT 24
Finished Jul 29 04:54:08 PM PDT 24
Peak memory 215620 kb
Host smart-400bfb56-7077-4ba5-8204-716a542cc3b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804344707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1804344
707 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.3598711487
Short name T1032
Test name
Test status
Simulation time 77981289 ps
CPU time 1.74 seconds
Started Jul 29 04:54:45 PM PDT 24
Finished Jul 29 04:54:47 PM PDT 24
Peak memory 218088 kb
Host smart-7b44b0bb-b4dc-4b22-a44c-5680238dc5c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598711487 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.3598711487 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.3645270389
Short name T153
Test name
Test status
Simulation time 78080886 ps
CPU time 1.01 seconds
Started Jul 29 04:54:23 PM PDT 24
Finished Jul 29 04:54:24 PM PDT 24
Peak memory 215652 kb
Host smart-a5f41f5b-6c16-4590-b79e-7a8914cd419e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645270389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.3645270389 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.814910912
Short name T1097
Test name
Test status
Simulation time 113842986 ps
CPU time 0.8 seconds
Started Jul 29 04:54:05 PM PDT 24
Finished Jul 29 04:54:06 PM PDT 24
Peak memory 215692 kb
Host smart-59366e1f-6f46-4d09-8772-a19883a328b9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814910912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.814910912 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.2746102632
Short name T1080
Test name
Test status
Simulation time 377392631 ps
CPU time 2.41 seconds
Started Jul 29 04:54:31 PM PDT 24
Finished Jul 29 04:54:34 PM PDT 24
Peak memory 215860 kb
Host smart-aa7e1162-4c7e-479b-b322-450acc190b29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746102632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr
_outstanding.2746102632 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.2187554284
Short name T1112
Test name
Test status
Simulation time 116552778 ps
CPU time 0.99 seconds
Started Jul 29 04:54:18 PM PDT 24
Finished Jul 29 04:54:20 PM PDT 24
Peak memory 215736 kb
Host smart-c3a9d059-1922-4777-a518-faf8c48b788d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187554284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_
errors.2187554284 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.4108484844
Short name T1093
Test name
Test status
Simulation time 123147789 ps
CPU time 1.77 seconds
Started Jul 29 04:54:03 PM PDT 24
Finished Jul 29 04:54:05 PM PDT 24
Peak memory 219512 kb
Host smart-2c9839b6-9d6b-41d5-8549-c04985db9f6d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108484844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac
_shadow_reg_errors_with_csr_rw.4108484844 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.1531591207
Short name T123
Test name
Test status
Simulation time 272382016 ps
CPU time 2.08 seconds
Started Jul 29 04:54:33 PM PDT 24
Finished Jul 29 04:54:35 PM PDT 24
Peak memory 216016 kb
Host smart-b3a90740-c35d-4a92-86a8-b207f8830726
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531591207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.1531591207 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.55841516
Short name T1106
Test name
Test status
Simulation time 270909316 ps
CPU time 5.57 seconds
Started Jul 29 04:54:21 PM PDT 24
Finished Jul 29 04:54:27 PM PDT 24
Peak memory 216092 kb
Host smart-fe635983-55a8-4659-a0c8-42ec13dbd1e3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55841516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.55841516
+enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.2455459403
Short name T1075
Test name
Test status
Simulation time 3844174283 ps
CPU time 19.98 seconds
Started Jul 29 04:54:20 PM PDT 24
Finished Jul 29 04:54:40 PM PDT 24
Peak memory 215988 kb
Host smart-e844a20f-fd53-48e8-a3e0-91f8b3fdd6a9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455459403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.2455459
403 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2324881183
Short name T1022
Test name
Test status
Simulation time 207434199 ps
CPU time 1.18 seconds
Started Jul 29 04:54:07 PM PDT 24
Finished Jul 29 04:54:09 PM PDT 24
Peak memory 215864 kb
Host smart-cad3ea5f-25b9-46fa-930d-64806901311b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324881183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.2324881
183 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.2684133593
Short name T1028
Test name
Test status
Simulation time 189265089 ps
CPU time 1.68 seconds
Started Jul 29 04:54:47 PM PDT 24
Finished Jul 29 04:54:49 PM PDT 24
Peak memory 221300 kb
Host smart-cc042b18-36de-4879-b50c-61af32cc3411
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684133593 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.2684133593 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.2319888821
Short name T1084
Test name
Test status
Simulation time 17636268 ps
CPU time 1.13 seconds
Started Jul 29 04:54:22 PM PDT 24
Finished Jul 29 04:54:24 PM PDT 24
Peak memory 215796 kb
Host smart-631e3d58-ff9b-4438-942f-9202c8daa8bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319888821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.2319888821 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.3253982897
Short name T997
Test name
Test status
Simulation time 21970786 ps
CPU time 0.8 seconds
Started Jul 29 04:54:23 PM PDT 24
Finished Jul 29 04:54:24 PM PDT 24
Peak memory 215576 kb
Host smart-e4ae68c0-30c4-4bf2-9446-af9d814d3c47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253982897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.3253982897 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.4125721091
Short name T144
Test name
Test status
Simulation time 73399065 ps
CPU time 1.33 seconds
Started Jul 29 04:54:40 PM PDT 24
Finished Jul 29 04:54:42 PM PDT 24
Peak memory 215740 kb
Host smart-4f53f067-8b82-447d-82d9-d94c2e0b673c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125721091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia
l_access.4125721091 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.1174758882
Short name T1008
Test name
Test status
Simulation time 19479941 ps
CPU time 0.73 seconds
Started Jul 29 04:54:20 PM PDT 24
Finished Jul 29 04:54:21 PM PDT 24
Peak memory 215548 kb
Host smart-ff0a0aa2-6c05-412e-85fb-28233b661815
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174758882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.1174758882
+enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.2829829946
Short name T1005
Test name
Test status
Simulation time 935774748 ps
CPU time 2.59 seconds
Started Jul 29 04:54:13 PM PDT 24
Finished Jul 29 04:54:16 PM PDT 24
Peak memory 215788 kb
Host smart-934413bf-470e-433b-81db-f6cc542284ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829829946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr
_outstanding.2829829946 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.3677957857
Short name T1088
Test name
Test status
Simulation time 228347706 ps
CPU time 1.38 seconds
Started Jul 29 04:54:36 PM PDT 24
Finished Jul 29 04:54:38 PM PDT 24
Peak memory 217348 kb
Host smart-365e6eb7-6f43-4ae8-8e4f-5c1f1e973bf5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677957857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_
errors.3677957857 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.906549133
Short name T78
Test name
Test status
Simulation time 62397353 ps
CPU time 1.77 seconds
Started Jul 29 04:54:39 PM PDT 24
Finished Jul 29 04:54:41 PM PDT 24
Peak memory 216136 kb
Host smart-bc4124bf-590a-4a8d-9d73-5e65260fc91a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906549133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_
shadow_reg_errors_with_csr_rw.906549133 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.1787182821
Short name T131
Test name
Test status
Simulation time 41888107 ps
CPU time 1.52 seconds
Started Jul 29 04:54:29 PM PDT 24
Finished Jul 29 04:54:30 PM PDT 24
Peak memory 215972 kb
Host smart-799884b5-4270-48ff-b88c-2083c85caa73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787182821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.1787182821 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.4098232045
Short name T1104
Test name
Test status
Simulation time 189161471 ps
CPU time 1.63 seconds
Started Jul 29 04:54:43 PM PDT 24
Finished Jul 29 04:54:45 PM PDT 24
Peak memory 216868 kb
Host smart-9dff0410-fc1d-4dca-a745-bdfd58ef3595
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098232045 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.4098232045 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.3595679009
Short name T1045
Test name
Test status
Simulation time 17324303 ps
CPU time 0.97 seconds
Started Jul 29 04:54:31 PM PDT 24
Finished Jul 29 04:54:33 PM PDT 24
Peak memory 215620 kb
Host smart-7ce44e53-1c56-4069-b6f7-23601fb2bbf9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595679009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.3595679009 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.570188802
Short name T1099
Test name
Test status
Simulation time 82285720 ps
CPU time 0.77 seconds
Started Jul 29 04:54:37 PM PDT 24
Finished Jul 29 04:54:38 PM PDT 24
Peak memory 215564 kb
Host smart-011507c3-9c18-4010-b28a-6addafef902b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570188802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.570188802 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2336267876
Short name T1083
Test name
Test status
Simulation time 114287763 ps
CPU time 2.58 seconds
Started Jul 29 04:54:39 PM PDT 24
Finished Jul 29 04:54:41 PM PDT 24
Peak memory 215944 kb
Host smart-69d105b5-d813-4e29-9532-8427bd6fa6fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336267876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs
r_outstanding.2336267876 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3852579179
Short name T1043
Test name
Test status
Simulation time 66967133 ps
CPU time 1.28 seconds
Started Jul 29 04:54:33 PM PDT 24
Finished Jul 29 04:54:34 PM PDT 24
Peak memory 216296 kb
Host smart-9c379fe8-a260-4494-bb9d-0e2fd85cebc0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852579179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg
_errors.3852579179 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.4099831173
Short name T89
Test name
Test status
Simulation time 51236601 ps
CPU time 2.22 seconds
Started Jul 29 04:54:36 PM PDT 24
Finished Jul 29 04:54:39 PM PDT 24
Peak memory 218964 kb
Host smart-1449ee51-09a8-4726-bc2a-f7f7abdad0cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099831173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma
c_shadow_reg_errors_with_csr_rw.4099831173 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.3720047039
Short name T129
Test name
Test status
Simulation time 86045167 ps
CPU time 2.29 seconds
Started Jul 29 04:54:44 PM PDT 24
Finished Jul 29 04:54:46 PM PDT 24
Peak memory 216000 kb
Host smart-2d9ed800-5820-4335-91e5-aba592e35cb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720047039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.3720047039 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.1758681220
Short name T176
Test name
Test status
Simulation time 187983641 ps
CPU time 2.39 seconds
Started Jul 29 04:54:42 PM PDT 24
Finished Jul 29 04:54:45 PM PDT 24
Peak memory 216228 kb
Host smart-b2faec13-c756-4b5c-94ac-b9a56c6ed100
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758681220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.1758
681220 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.3469642068
Short name T130
Test name
Test status
Simulation time 46413454 ps
CPU time 1.53 seconds
Started Jul 29 04:54:54 PM PDT 24
Finished Jul 29 04:54:56 PM PDT 24
Peak memory 218436 kb
Host smart-c1927d30-256c-456b-a665-602e4478d985
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469642068 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.3469642068 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.3316461006
Short name T1040
Test name
Test status
Simulation time 20930666 ps
CPU time 0.94 seconds
Started Jul 29 04:54:40 PM PDT 24
Finished Jul 29 04:54:41 PM PDT 24
Peak memory 215600 kb
Host smart-669fcbc3-98b3-4589-a04e-37b9361c47fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316461006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.3316461006 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.3228311596
Short name T1019
Test name
Test status
Simulation time 17998281 ps
CPU time 0.82 seconds
Started Jul 29 04:54:34 PM PDT 24
Finished Jul 29 04:54:35 PM PDT 24
Peak memory 215664 kb
Host smart-432e35c8-7b79-48dc-882c-10761eb20f35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228311596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.3228311596 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.643262434
Short name T1059
Test name
Test status
Simulation time 357455608 ps
CPU time 1.73 seconds
Started Jul 29 04:54:47 PM PDT 24
Finished Jul 29 04:54:49 PM PDT 24
Peak memory 215944 kb
Host smart-b53ab897-5818-4e49-bab5-9a08efb3c3da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643262434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr
_outstanding.643262434 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2307971510
Short name T1052
Test name
Test status
Simulation time 31515092 ps
CPU time 1.21 seconds
Started Jul 29 04:54:41 PM PDT 24
Finished Jul 29 04:54:42 PM PDT 24
Peak memory 216276 kb
Host smart-b894eaa0-3589-4ea1-8227-246628e4102b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307971510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg
_errors.2307971510 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.907531942
Short name T1055
Test name
Test status
Simulation time 734066147 ps
CPU time 2.99 seconds
Started Jul 29 04:54:41 PM PDT 24
Finished Jul 29 04:54:44 PM PDT 24
Peak memory 218880 kb
Host smart-96ce9bd2-2ca4-4fd3-b18b-d81d2d454c3b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907531942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac
_shadow_reg_errors_with_csr_rw.907531942 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.3567348578
Short name T1065
Test name
Test status
Simulation time 236214915 ps
CPU time 2.91 seconds
Started Jul 29 04:54:56 PM PDT 24
Finished Jul 29 04:54:59 PM PDT 24
Peak memory 215984 kb
Host smart-ee3731cb-b7b0-4213-afb7-8a941906b083
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567348578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.3567348578 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.2330327494
Short name T1132
Test name
Test status
Simulation time 920237899 ps
CPU time 4.68 seconds
Started Jul 29 04:54:48 PM PDT 24
Finished Jul 29 04:54:53 PM PDT 24
Peak memory 215880 kb
Host smart-331e43ff-ce21-42d2-b5b2-a4b7c3739be2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330327494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.2330
327494 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.433662751
Short name T989
Test name
Test status
Simulation time 36251380 ps
CPU time 1.52 seconds
Started Jul 29 04:54:59 PM PDT 24
Finished Jul 29 04:55:00 PM PDT 24
Peak memory 216920 kb
Host smart-a157e215-6157-4343-b3f8-e0dafc64ca63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433662751 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.433662751 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.3706737090
Short name T1089
Test name
Test status
Simulation time 37495828 ps
CPU time 0.95 seconds
Started Jul 29 04:54:42 PM PDT 24
Finished Jul 29 04:54:43 PM PDT 24
Peak memory 215680 kb
Host smart-c4739633-252a-4a1c-bf0c-ec9da85a3267
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706737090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.3706737090 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.1698984680
Short name T1014
Test name
Test status
Simulation time 12484146 ps
CPU time 0.81 seconds
Started Jul 29 04:54:36 PM PDT 24
Finished Jul 29 04:54:37 PM PDT 24
Peak memory 215376 kb
Host smart-09c0b1dd-477a-4648-a75b-439c65890103
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698984680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.1698984680 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3411418871
Short name T1062
Test name
Test status
Simulation time 69141774 ps
CPU time 2.13 seconds
Started Jul 29 04:54:53 PM PDT 24
Finished Jul 29 04:54:55 PM PDT 24
Peak memory 215796 kb
Host smart-face1acc-229c-4067-a064-84c341ec34de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411418871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs
r_outstanding.3411418871 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.3599167591
Short name T1064
Test name
Test status
Simulation time 66892073 ps
CPU time 0.98 seconds
Started Jul 29 04:54:44 PM PDT 24
Finished Jul 29 04:54:45 PM PDT 24
Peak memory 216076 kb
Host smart-c6eb275d-80e6-4792-ae0b-e35318230191
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599167591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg
_errors.3599167591 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.3004370836
Short name T1116
Test name
Test status
Simulation time 55453098 ps
CPU time 3.33 seconds
Started Jul 29 04:54:44 PM PDT 24
Finished Jul 29 04:54:48 PM PDT 24
Peak memory 216024 kb
Host smart-2113ee08-1ce1-465d-a794-d9d1e9416b88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004370836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.3004370836 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.3951042403
Short name T994
Test name
Test status
Simulation time 461164367 ps
CPU time 3.1 seconds
Started Jul 29 04:54:38 PM PDT 24
Finished Jul 29 04:54:41 PM PDT 24
Peak memory 215952 kb
Host smart-3e77497b-2e73-41d4-a78e-7814fc12213f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951042403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.3951
042403 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.473953994
Short name T1027
Test name
Test status
Simulation time 107855966 ps
CPU time 2.68 seconds
Started Jul 29 04:54:43 PM PDT 24
Finished Jul 29 04:54:45 PM PDT 24
Peak memory 220916 kb
Host smart-7057dbc4-785d-4663-b2a0-14b694e04634
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473953994 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.473953994 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.46671355
Short name T1118
Test name
Test status
Simulation time 19217648 ps
CPU time 1 seconds
Started Jul 29 04:54:40 PM PDT 24
Finished Jul 29 04:54:41 PM PDT 24
Peak memory 215664 kb
Host smart-a75ef7bb-96d4-4ba3-bdf8-1bd17666121a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46671355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.46671355 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.2685260754
Short name T1017
Test name
Test status
Simulation time 78661272 ps
CPU time 0.81 seconds
Started Jul 29 04:54:41 PM PDT 24
Finished Jul 29 04:54:42 PM PDT 24
Peak memory 215660 kb
Host smart-2fa171fc-bb24-4491-8ef1-1e704ec21a1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685260754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.2685260754 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.4282868573
Short name T1111
Test name
Test status
Simulation time 162718164 ps
CPU time 2.07 seconds
Started Jul 29 04:54:44 PM PDT 24
Finished Jul 29 04:54:47 PM PDT 24
Peak memory 215864 kb
Host smart-933e1faf-92a5-4b7a-b5a5-601fbf3573b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282868573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs
r_outstanding.4282868573 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1058995086
Short name T1001
Test name
Test status
Simulation time 69373223 ps
CPU time 1.05 seconds
Started Jul 29 04:54:37 PM PDT 24
Finished Jul 29 04:54:38 PM PDT 24
Peak memory 216248 kb
Host smart-5f00c564-326f-4a31-9671-753bf6b5d775
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058995086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg
_errors.1058995086 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2242720043
Short name T1130
Test name
Test status
Simulation time 130449107 ps
CPU time 1.81 seconds
Started Jul 29 04:54:46 PM PDT 24
Finished Jul 29 04:54:48 PM PDT 24
Peak memory 218176 kb
Host smart-cb35ed44-4c51-4dd6-81ec-d75576174d39
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242720043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma
c_shadow_reg_errors_with_csr_rw.2242720043 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.1188086686
Short name T1054
Test name
Test status
Simulation time 55609088 ps
CPU time 3.4 seconds
Started Jul 29 04:54:38 PM PDT 24
Finished Jul 29 04:54:41 PM PDT 24
Peak memory 215940 kb
Host smart-be2cc901-94c7-42f3-a5d7-8d282b3bc874
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188086686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.1188086686 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.2693185436
Short name T1035
Test name
Test status
Simulation time 102411174 ps
CPU time 1.71 seconds
Started Jul 29 04:54:56 PM PDT 24
Finished Jul 29 04:54:57 PM PDT 24
Peak memory 217380 kb
Host smart-54adfd11-312a-4b67-bb27-e1c4f0006dc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693185436 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.2693185436 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.916177459
Short name T185
Test name
Test status
Simulation time 97397605 ps
CPU time 1.15 seconds
Started Jul 29 04:54:57 PM PDT 24
Finished Jul 29 04:55:04 PM PDT 24
Peak memory 215904 kb
Host smart-9a4d10b2-5c02-488d-86e4-63fbe972cad2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916177459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.916177459 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.2369197463
Short name T1110
Test name
Test status
Simulation time 13781174 ps
CPU time 0.82 seconds
Started Jul 29 04:54:59 PM PDT 24
Finished Jul 29 04:55:00 PM PDT 24
Peak memory 215320 kb
Host smart-2d97e94d-83a9-4aee-8d17-bd5967ee04d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369197463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.2369197463 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.3598501989
Short name T982
Test name
Test status
Simulation time 37117353 ps
CPU time 2.07 seconds
Started Jul 29 04:54:37 PM PDT 24
Finished Jul 29 04:54:39 PM PDT 24
Peak memory 215912 kb
Host smart-55919e92-58f3-4a8b-bc01-fa8d5764db37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598501989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs
r_outstanding.3598501989 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3576028464
Short name T1078
Test name
Test status
Simulation time 57501512 ps
CPU time 0.99 seconds
Started Jul 29 04:54:41 PM PDT 24
Finished Jul 29 04:54:42 PM PDT 24
Peak memory 216084 kb
Host smart-d769b8ec-c443-44d9-a9ee-73348b931e7d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576028464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg
_errors.3576028464 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.3356033151
Short name T114
Test name
Test status
Simulation time 58314349 ps
CPU time 1.58 seconds
Started Jul 29 04:54:46 PM PDT 24
Finished Jul 29 04:54:48 PM PDT 24
Peak memory 215776 kb
Host smart-ba22313a-de92-4681-b220-ee36bac15cca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356033151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma
c_shadow_reg_errors_with_csr_rw.3356033151 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.1174209085
Short name T1098
Test name
Test status
Simulation time 116391502 ps
CPU time 1.7 seconds
Started Jul 29 04:54:52 PM PDT 24
Finished Jul 29 04:54:59 PM PDT 24
Peak memory 216056 kb
Host smart-84226076-477b-416b-9251-639aebf999b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174209085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.1174209085 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.1791979750
Short name T1113
Test name
Test status
Simulation time 130072373 ps
CPU time 2.96 seconds
Started Jul 29 04:54:51 PM PDT 24
Finished Jul 29 04:54:54 PM PDT 24
Peak memory 216000 kb
Host smart-58bde773-7bb2-450f-b88f-dc548c3246bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791979750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.1791
979750 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.4036040816
Short name T1026
Test name
Test status
Simulation time 609213677 ps
CPU time 2.48 seconds
Started Jul 29 04:55:08 PM PDT 24
Finished Jul 29 04:55:10 PM PDT 24
Peak memory 221140 kb
Host smart-0a0d3214-4b5e-4103-82c9-fcc0e8d4278e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036040816 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.4036040816 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.3490039293
Short name T152
Test name
Test status
Simulation time 56495311 ps
CPU time 1.15 seconds
Started Jul 29 04:54:49 PM PDT 24
Finished Jul 29 04:54:50 PM PDT 24
Peak memory 215904 kb
Host smart-6949e932-6af7-4b1a-bbcf-8d5f35f7932e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490039293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.3490039293 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.2105602972
Short name T1011
Test name
Test status
Simulation time 28703819 ps
CPU time 0.81 seconds
Started Jul 29 04:54:52 PM PDT 24
Finished Jul 29 04:54:53 PM PDT 24
Peak memory 215760 kb
Host smart-7732ad10-0fff-47ea-8efe-73e489abe6ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105602972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.2105602972 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2600984307
Short name T1068
Test name
Test status
Simulation time 63406735 ps
CPU time 1.53 seconds
Started Jul 29 04:54:40 PM PDT 24
Finished Jul 29 04:54:41 PM PDT 24
Peak memory 215776 kb
Host smart-6b6898a1-6c32-4577-bf02-680bcef18933
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600984307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs
r_outstanding.2600984307 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.1720804189
Short name T1109
Test name
Test status
Simulation time 29913756 ps
CPU time 1.27 seconds
Started Jul 29 04:54:48 PM PDT 24
Finished Jul 29 04:54:49 PM PDT 24
Peak memory 216476 kb
Host smart-ff93011b-76f2-4c7a-b16a-4bf65fcf68d9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720804189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg
_errors.1720804189 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1831323429
Short name T88
Test name
Test status
Simulation time 248238171 ps
CPU time 2.87 seconds
Started Jul 29 04:54:54 PM PDT 24
Finished Jul 29 04:54:57 PM PDT 24
Peak memory 219768 kb
Host smart-c410b046-97c3-4851-8201-d2ffa1aab79a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831323429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kma
c_shadow_reg_errors_with_csr_rw.1831323429 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.710495847
Short name T124
Test name
Test status
Simulation time 74250322 ps
CPU time 1.51 seconds
Started Jul 29 04:54:48 PM PDT 24
Finished Jul 29 04:54:50 PM PDT 24
Peak memory 215968 kb
Host smart-fb3d8621-10d0-473e-8fc2-1a1e32633d62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710495847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.710495847 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.3288448324
Short name T1082
Test name
Test status
Simulation time 275999790 ps
CPU time 2.48 seconds
Started Jul 29 04:54:47 PM PDT 24
Finished Jul 29 04:54:49 PM PDT 24
Peak memory 215916 kb
Host smart-6b174c5b-b2b8-463b-93cc-e7277fb5de2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288448324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.3288
448324 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1399656517
Short name T1090
Test name
Test status
Simulation time 546542890 ps
CPU time 2.42 seconds
Started Jul 29 04:54:50 PM PDT 24
Finished Jul 29 04:54:53 PM PDT 24
Peak memory 221116 kb
Host smart-d2d973b7-cb06-4d0c-a736-4e9d2235b41a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399656517 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.1399656517 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.3189923785
Short name T1010
Test name
Test status
Simulation time 19856829 ps
CPU time 0.94 seconds
Started Jul 29 04:55:24 PM PDT 24
Finished Jul 29 04:55:26 PM PDT 24
Peak memory 215592 kb
Host smart-e5c85091-8ef7-4cc7-b58e-4ce0e1614897
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189923785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.3189923785 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.3714623322
Short name T165
Test name
Test status
Simulation time 12841731 ps
CPU time 0.76 seconds
Started Jul 29 04:54:45 PM PDT 24
Finished Jul 29 04:54:46 PM PDT 24
Peak memory 215364 kb
Host smart-ea41f79b-0d9d-46ce-a876-f41e71504701
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714623322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.3714623322 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.483108177
Short name T984
Test name
Test status
Simulation time 28898583 ps
CPU time 1.47 seconds
Started Jul 29 04:54:54 PM PDT 24
Finished Jul 29 04:54:56 PM PDT 24
Peak memory 215832 kb
Host smart-bdee7436-7078-4141-a98c-aa33df74bea6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483108177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr
_outstanding.483108177 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2126403441
Short name T1020
Test name
Test status
Simulation time 60322064 ps
CPU time 0.81 seconds
Started Jul 29 04:54:51 PM PDT 24
Finished Jul 29 04:54:52 PM PDT 24
Peak memory 215680 kb
Host smart-b006644d-a4ba-4a33-bdbd-8fe679507e54
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126403441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg
_errors.2126403441 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.815158633
Short name T87
Test name
Test status
Simulation time 113091207 ps
CPU time 2.87 seconds
Started Jul 29 04:54:46 PM PDT 24
Finished Jul 29 04:54:49 PM PDT 24
Peak memory 219692 kb
Host smart-15309dbd-7af9-47fa-ad4f-d735cd09d5b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815158633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac
_shadow_reg_errors_with_csr_rw.815158633 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.207082472
Short name T1034
Test name
Test status
Simulation time 61765861 ps
CPU time 1.68 seconds
Started Jul 29 04:54:44 PM PDT 24
Finished Jul 29 04:54:46 PM PDT 24
Peak memory 215908 kb
Host smart-9cf1147d-e1e5-4f53-863c-b824193e87bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207082472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.207082472 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.2552116573
Short name T177
Test name
Test status
Simulation time 154013497 ps
CPU time 3.91 seconds
Started Jul 29 04:54:44 PM PDT 24
Finished Jul 29 04:54:48 PM PDT 24
Peak memory 215988 kb
Host smart-55eebd2e-810e-42cf-bcd6-c210f1f1d8be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552116573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.2552
116573 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.3185834840
Short name T1123
Test name
Test status
Simulation time 47658361 ps
CPU time 1.61 seconds
Started Jul 29 04:54:58 PM PDT 24
Finished Jul 29 04:55:00 PM PDT 24
Peak memory 219312 kb
Host smart-d48d1c3e-7b21-4ee3-a0b2-b7e5ccb1d769
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185834840 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.3185834840 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.983349667
Short name T154
Test name
Test status
Simulation time 34065195 ps
CPU time 1.19 seconds
Started Jul 29 04:54:41 PM PDT 24
Finished Jul 29 04:54:42 PM PDT 24
Peak memory 215820 kb
Host smart-ed322fe7-dff8-4ef1-b08c-a2900917dae5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983349667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.983349667 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.3721036531
Short name T1012
Test name
Test status
Simulation time 25466518 ps
CPU time 0.78 seconds
Started Jul 29 04:54:45 PM PDT 24
Finished Jul 29 04:54:46 PM PDT 24
Peak memory 215632 kb
Host smart-e093324e-28b8-4744-bb3b-5bd9918e37d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721036531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.3721036531 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2611643854
Short name T993
Test name
Test status
Simulation time 34212665 ps
CPU time 1.46 seconds
Started Jul 29 04:54:52 PM PDT 24
Finished Jul 29 04:54:54 PM PDT 24
Peak memory 215856 kb
Host smart-879e1ef9-e46f-4699-a3a7-d84cd2f44ed1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611643854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs
r_outstanding.2611643854 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2867634039
Short name T80
Test name
Test status
Simulation time 84761354 ps
CPU time 1.2 seconds
Started Jul 29 04:54:39 PM PDT 24
Finished Jul 29 04:54:41 PM PDT 24
Peak memory 216400 kb
Host smart-3016d9ea-6844-464b-b603-3e0bc1a732de
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867634039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg
_errors.2867634039 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2837646086
Short name T1037
Test name
Test status
Simulation time 145374305 ps
CPU time 2.05 seconds
Started Jul 29 04:55:10 PM PDT 24
Finished Jul 29 04:55:12 PM PDT 24
Peak memory 218708 kb
Host smart-56dcf1bc-d6ca-41fb-a94c-60eee916fa0d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837646086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma
c_shadow_reg_errors_with_csr_rw.2837646086 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.2175365084
Short name T95
Test name
Test status
Simulation time 401847691 ps
CPU time 2.54 seconds
Started Jul 29 04:54:52 PM PDT 24
Finished Jul 29 04:54:54 PM PDT 24
Peak memory 215940 kb
Host smart-cbf87dcf-dbd7-4513-a6f5-4ba0260c0935
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175365084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.2175365084 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.427550110
Short name T158
Test name
Test status
Simulation time 370036646 ps
CPU time 2.48 seconds
Started Jul 29 04:54:56 PM PDT 24
Finished Jul 29 04:54:59 PM PDT 24
Peak memory 222112 kb
Host smart-f2b44bc6-f267-4f4a-a46e-7cfa8ead4ed5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427550110 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.427550110 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.751049802
Short name T1069
Test name
Test status
Simulation time 37449693 ps
CPU time 1.17 seconds
Started Jul 29 04:54:42 PM PDT 24
Finished Jul 29 04:54:44 PM PDT 24
Peak memory 215808 kb
Host smart-366728b3-ba8d-4654-b64f-1424aaf28a37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751049802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.751049802 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.655441706
Short name T157
Test name
Test status
Simulation time 89850716 ps
CPU time 0.8 seconds
Started Jul 29 04:54:56 PM PDT 24
Finished Jul 29 04:54:57 PM PDT 24
Peak memory 215612 kb
Host smart-a9688eb6-9914-4f47-806a-ce839d7fa49a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655441706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.655441706 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.3225639614
Short name T987
Test name
Test status
Simulation time 564690143 ps
CPU time 2.67 seconds
Started Jul 29 04:54:48 PM PDT 24
Finished Jul 29 04:54:51 PM PDT 24
Peak memory 215840 kb
Host smart-753bd223-4446-45c4-8d8d-bb15364010c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225639614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs
r_outstanding.3225639614 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1656415824
Short name T1095
Test name
Test status
Simulation time 38628967 ps
CPU time 1.18 seconds
Started Jul 29 04:54:52 PM PDT 24
Finished Jul 29 04:54:53 PM PDT 24
Peak memory 216256 kb
Host smart-f2979140-eb9a-4014-8ca7-690c01f3d2cb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656415824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg
_errors.1656415824 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3891800193
Short name T1086
Test name
Test status
Simulation time 95003783 ps
CPU time 1.54 seconds
Started Jul 29 04:54:49 PM PDT 24
Finished Jul 29 04:54:50 PM PDT 24
Peak memory 218456 kb
Host smart-18fdcdcf-9a1d-4b54-98ed-f1d90e022bd0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891800193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma
c_shadow_reg_errors_with_csr_rw.3891800193 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.2514119319
Short name T113
Test name
Test status
Simulation time 64245082 ps
CPU time 1.47 seconds
Started Jul 29 04:54:53 PM PDT 24
Finished Jul 29 04:54:54 PM PDT 24
Peak memory 215932 kb
Host smart-31d83349-67a2-4066-8b64-99af8f768f0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514119319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.2514119319 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.2214486771
Short name T174
Test name
Test status
Simulation time 143021668 ps
CPU time 2.79 seconds
Started Jul 29 04:54:55 PM PDT 24
Finished Jul 29 04:54:58 PM PDT 24
Peak memory 216080 kb
Host smart-0251c1a2-b0fd-4b3f-baf3-0273a35d58c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214486771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.2214
486771 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.1746987138
Short name T155
Test name
Test status
Simulation time 97357949 ps
CPU time 1.76 seconds
Started Jul 29 04:55:02 PM PDT 24
Finished Jul 29 04:55:03 PM PDT 24
Peak memory 220280 kb
Host smart-b17497f1-9788-4c30-b878-cb82901d7174
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746987138 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.1746987138 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.3859956514
Short name T1102
Test name
Test status
Simulation time 20003340 ps
CPU time 0.95 seconds
Started Jul 29 04:54:54 PM PDT 24
Finished Jul 29 04:54:55 PM PDT 24
Peak memory 215640 kb
Host smart-c955e49c-1def-459e-bb4f-3108ef342e83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859956514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.3859956514 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.1457868946
Short name T1108
Test name
Test status
Simulation time 83383847 ps
CPU time 0.79 seconds
Started Jul 29 04:54:43 PM PDT 24
Finished Jul 29 04:54:45 PM PDT 24
Peak memory 215396 kb
Host smart-857a2cb5-84b4-4ca9-8a98-9d684139c3a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457868946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.1457868946 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1743107616
Short name T985
Test name
Test status
Simulation time 477590004 ps
CPU time 2.53 seconds
Started Jul 29 04:54:34 PM PDT 24
Finished Jul 29 04:54:37 PM PDT 24
Peak memory 215884 kb
Host smart-77962df6-54d8-4501-ae02-1e4b381e5235
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743107616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_cs
r_outstanding.1743107616 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3084913407
Short name T1127
Test name
Test status
Simulation time 113172772 ps
CPU time 1.13 seconds
Started Jul 29 04:54:52 PM PDT 24
Finished Jul 29 04:54:53 PM PDT 24
Peak memory 216292 kb
Host smart-ef6a5cf9-1b25-485a-b648-525d32dace0f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084913407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg
_errors.3084913407 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.3858160018
Short name T1030
Test name
Test status
Simulation time 71602626 ps
CPU time 1.87 seconds
Started Jul 29 04:54:56 PM PDT 24
Finished Jul 29 04:54:58 PM PDT 24
Peak memory 218620 kb
Host smart-ca4e17b9-0e8b-4a8f-b487-817004ff97f2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858160018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma
c_shadow_reg_errors_with_csr_rw.3858160018 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.4207053847
Short name T1103
Test name
Test status
Simulation time 178340939 ps
CPU time 2.27 seconds
Started Jul 29 04:54:58 PM PDT 24
Finished Jul 29 04:55:01 PM PDT 24
Peak memory 216032 kb
Host smart-29d68747-c659-4c6a-9d1f-888fee700ebf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207053847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.4207053847 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.4109425712
Short name T117
Test name
Test status
Simulation time 337516800 ps
CPU time 2.37 seconds
Started Jul 29 04:54:54 PM PDT 24
Finished Jul 29 04:55:02 PM PDT 24
Peak memory 215908 kb
Host smart-51aa6cf7-c8dc-4c51-90cb-417207e603d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109425712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.4109
425712 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.3679051930
Short name T998
Test name
Test status
Simulation time 1588782675 ps
CPU time 9.44 seconds
Started Jul 29 04:54:41 PM PDT 24
Finished Jul 29 04:54:51 PM PDT 24
Peak memory 215884 kb
Host smart-4509be3c-9385-4baa-83e1-95e1d6bc7f45
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679051930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.3679051
930 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.1344589835
Short name T1004
Test name
Test status
Simulation time 2415199825 ps
CPU time 18.92 seconds
Started Jul 29 04:54:23 PM PDT 24
Finished Jul 29 04:54:42 PM PDT 24
Peak memory 215912 kb
Host smart-861c7676-f63f-4ffe-ae80-72a4c84d0e8d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344589835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.1344589
835 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.2502088433
Short name T1006
Test name
Test status
Simulation time 51932784 ps
CPU time 0.96 seconds
Started Jul 29 04:54:23 PM PDT 24
Finished Jul 29 04:54:24 PM PDT 24
Peak memory 215600 kb
Host smart-fe4f354f-a1af-4e8e-b4c3-6751c759d8d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502088433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.2502088
433 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.1966832603
Short name T999
Test name
Test status
Simulation time 75064316 ps
CPU time 2.24 seconds
Started Jul 29 04:54:46 PM PDT 24
Finished Jul 29 04:54:48 PM PDT 24
Peak memory 221180 kb
Host smart-be470c34-672b-4cc6-9d69-684162534a89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966832603 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.1966832603 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.674160304
Short name T1131
Test name
Test status
Simulation time 18809712 ps
CPU time 0.92 seconds
Started Jul 29 04:54:40 PM PDT 24
Finished Jul 29 04:54:41 PM PDT 24
Peak memory 215600 kb
Host smart-e82fbfd8-e276-44c2-9326-0eedaedd355b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674160304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.674160304 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.2930273497
Short name T1061
Test name
Test status
Simulation time 73102277 ps
CPU time 0.82 seconds
Started Jul 29 04:54:34 PM PDT 24
Finished Jul 29 04:54:35 PM PDT 24
Peak memory 215624 kb
Host smart-385dc2a1-944f-41c3-ac1d-af6789081a69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930273497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.2930273497 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.315149379
Short name T147
Test name
Test status
Simulation time 78454197 ps
CPU time 1.33 seconds
Started Jul 29 04:54:43 PM PDT 24
Finished Jul 29 04:54:44 PM PDT 24
Peak memory 215820 kb
Host smart-3c1afb60-ce0e-4bc7-94c5-e23b4e476fd5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315149379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial
_access.315149379 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.4285045150
Short name T1092
Test name
Test status
Simulation time 33827032 ps
CPU time 0.73 seconds
Started Jul 29 04:54:07 PM PDT 24
Finished Jul 29 04:54:08 PM PDT 24
Peak memory 215116 kb
Host smart-6171f84f-e176-456e-81ca-53e0dda150b8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285045150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.4285045150
+enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.99616148
Short name T82
Test name
Test status
Simulation time 258303278 ps
CPU time 1.59 seconds
Started Jul 29 04:54:50 PM PDT 24
Finished Jul 29 04:54:51 PM PDT 24
Peak memory 216008 kb
Host smart-5f8af01d-1cfb-4321-97b0-8d6d12fd295c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99616148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_o
utstanding.99616148 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.803425091
Short name T1073
Test name
Test status
Simulation time 41800713 ps
CPU time 1.28 seconds
Started Jul 29 04:54:21 PM PDT 24
Finished Jul 29 04:54:22 PM PDT 24
Peak memory 216240 kb
Host smart-5a634deb-dbea-4294-bbfc-9bd5a4558c1d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803425091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_e
rrors.803425091 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.14904890
Short name T1129
Test name
Test status
Simulation time 167773335 ps
CPU time 2.2 seconds
Started Jul 29 04:54:32 PM PDT 24
Finished Jul 29 04:54:35 PM PDT 24
Peak memory 218212 kb
Host smart-ac3d0d95-9745-40f2-8f04-6956e15257d5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14904890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_s
hadow_reg_errors_with_csr_rw.14904890 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.141369539
Short name T125
Test name
Test status
Simulation time 296576409 ps
CPU time 3.71 seconds
Started Jul 29 04:54:23 PM PDT 24
Finished Jul 29 04:54:27 PM PDT 24
Peak memory 215968 kb
Host smart-3eefa283-5354-47b4-9d61-38a70ef43631
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141369539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.141369539 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.1988170160
Short name T182
Test name
Test status
Simulation time 53381933 ps
CPU time 2.43 seconds
Started Jul 29 04:54:27 PM PDT 24
Finished Jul 29 04:54:30 PM PDT 24
Peak memory 215916 kb
Host smart-f99631d3-fc8e-4338-8987-8cc2806b36e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988170160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.19881
70160 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.152602319
Short name T121
Test name
Test status
Simulation time 69293858 ps
CPU time 0.76 seconds
Started Jul 29 04:55:23 PM PDT 24
Finished Jul 29 04:55:24 PM PDT 24
Peak memory 215680 kb
Host smart-3c307645-f21e-46f5-8382-0efa7c4c9031
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152602319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.152602319 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.3097706535
Short name T156
Test name
Test status
Simulation time 20997807 ps
CPU time 0.82 seconds
Started Jul 29 04:54:46 PM PDT 24
Finished Jul 29 04:54:47 PM PDT 24
Peak memory 215604 kb
Host smart-223fe621-b281-4ad8-a20b-129b386a6931
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097706535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.3097706535 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.1526985960
Short name T1067
Test name
Test status
Simulation time 40259129 ps
CPU time 0.79 seconds
Started Jul 29 04:54:46 PM PDT 24
Finished Jul 29 04:54:47 PM PDT 24
Peak memory 215604 kb
Host smart-24d433b0-89c1-4aca-8b08-38e540747e70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526985960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.1526985960 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.3757329344
Short name T1003
Test name
Test status
Simulation time 42341468 ps
CPU time 0.82 seconds
Started Jul 29 04:54:43 PM PDT 24
Finished Jul 29 04:54:43 PM PDT 24
Peak memory 215776 kb
Host smart-027b9d14-f4e1-44bc-bf75-339e94d970bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757329344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.3757329344 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.1951022098
Short name T1053
Test name
Test status
Simulation time 13231151 ps
CPU time 0.78 seconds
Started Jul 29 04:54:59 PM PDT 24
Finished Jul 29 04:55:00 PM PDT 24
Peak memory 215756 kb
Host smart-7e235b3b-3e73-491f-b111-96f0587a8653
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951022098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.1951022098 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.1334509105
Short name T1070
Test name
Test status
Simulation time 84289243 ps
CPU time 0.83 seconds
Started Jul 29 04:54:45 PM PDT 24
Finished Jul 29 04:54:46 PM PDT 24
Peak memory 215624 kb
Host smart-430b54e6-d6b5-46a2-aded-240deb33ea09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334509105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.1334509105 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.1241238781
Short name T1024
Test name
Test status
Simulation time 14746860 ps
CPU time 0.76 seconds
Started Jul 29 04:54:48 PM PDT 24
Finished Jul 29 04:54:49 PM PDT 24
Peak memory 215416 kb
Host smart-0bc4ad1a-19a3-482c-8bbc-a69649313f81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241238781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.1241238781 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.96626901
Short name T1023
Test name
Test status
Simulation time 49609418 ps
CPU time 0.86 seconds
Started Jul 29 04:54:54 PM PDT 24
Finished Jul 29 04:54:55 PM PDT 24
Peak memory 215656 kb
Host smart-d77db0bb-073f-4f02-996c-f5f9229643c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96626901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.96626901 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.1665850784
Short name T162
Test name
Test status
Simulation time 40247094 ps
CPU time 0.77 seconds
Started Jul 29 04:54:56 PM PDT 24
Finished Jul 29 04:54:57 PM PDT 24
Peak memory 215248 kb
Host smart-2f31124d-8e0b-425a-9eb2-d05c9723b93b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665850784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.1665850784 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.498727353
Short name T1013
Test name
Test status
Simulation time 72762434 ps
CPU time 0.86 seconds
Started Jul 29 04:54:46 PM PDT 24
Finished Jul 29 04:54:47 PM PDT 24
Peak memory 215628 kb
Host smart-b4b257cb-df8c-4503-9a83-768ffaa60c12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498727353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.498727353 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1626967970
Short name T1101
Test name
Test status
Simulation time 1908117342 ps
CPU time 10.01 seconds
Started Jul 29 04:54:40 PM PDT 24
Finished Jul 29 04:54:50 PM PDT 24
Peak memory 215764 kb
Host smart-865aaf19-af89-4ca1-9e3b-a0943e12a930
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626967970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.1626967
970 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.2503568137
Short name T991
Test name
Test status
Simulation time 1170058558 ps
CPU time 15.93 seconds
Started Jul 29 04:54:23 PM PDT 24
Finished Jul 29 04:54:39 PM PDT 24
Peak memory 215828 kb
Host smart-7d2f281f-e1a6-4705-b9f3-1eb023fed909
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503568137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.2503568
137 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.1056687979
Short name T1060
Test name
Test status
Simulation time 56979309 ps
CPU time 1.21 seconds
Started Jul 29 04:54:24 PM PDT 24
Finished Jul 29 04:54:25 PM PDT 24
Peak memory 215788 kb
Host smart-b5cf13e0-7984-4b42-91c1-3022f8cf814a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056687979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.1056687
979 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2396102326
Short name T94
Test name
Test status
Simulation time 32431982 ps
CPU time 1.97 seconds
Started Jul 29 04:54:16 PM PDT 24
Finished Jul 29 04:54:18 PM PDT 24
Peak memory 221172 kb
Host smart-4ff98074-9bcb-4ab0-8f75-fe6faa9e65e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396102326 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.2396102326 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.4020209168
Short name T81
Test name
Test status
Simulation time 25066953 ps
CPU time 1.01 seconds
Started Jul 29 04:54:39 PM PDT 24
Finished Jul 29 04:54:41 PM PDT 24
Peak memory 215696 kb
Host smart-491e570b-33fb-45d1-a8ec-cb20bdaf6301
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020209168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.4020209168 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.1838447319
Short name T1000
Test name
Test status
Simulation time 12771476 ps
CPU time 0.83 seconds
Started Jul 29 04:54:40 PM PDT 24
Finished Jul 29 04:54:41 PM PDT 24
Peak memory 215628 kb
Host smart-2b706a30-0684-4bca-bd3f-e1cc95853579
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838447319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.1838447319 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.1599116731
Short name T143
Test name
Test status
Simulation time 32801545 ps
CPU time 1.15 seconds
Started Jul 29 04:54:46 PM PDT 24
Finished Jul 29 04:54:47 PM PDT 24
Peak memory 215824 kb
Host smart-a289961f-21b9-4554-98da-8ca0e4d43f97
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599116731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia
l_access.1599116731 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.1268162102
Short name T986
Test name
Test status
Simulation time 14283890 ps
CPU time 0.76 seconds
Started Jul 29 04:54:41 PM PDT 24
Finished Jul 29 04:54:42 PM PDT 24
Peak memory 215660 kb
Host smart-45b8c886-4db4-48a6-a850-9f7175aaf977
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268162102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.1268162102
+enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.4237630447
Short name T983
Test name
Test status
Simulation time 97994007 ps
CPU time 1.55 seconds
Started Jul 29 04:54:36 PM PDT 24
Finished Jul 29 04:54:38 PM PDT 24
Peak memory 215792 kb
Host smart-ee59db03-0fbd-4a74-b2fc-c68a6992f129
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237630447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr
_outstanding.4237630447 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.2958419661
Short name T1029
Test name
Test status
Simulation time 70340955 ps
CPU time 1.19 seconds
Started Jul 29 04:54:19 PM PDT 24
Finished Jul 29 04:54:20 PM PDT 24
Peak memory 216308 kb
Host smart-365548d2-a032-4e77-a1cb-86792df95462
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958419661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_
errors.2958419661 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.416911782
Short name T1018
Test name
Test status
Simulation time 66506579 ps
CPU time 2.22 seconds
Started Jul 29 04:54:31 PM PDT 24
Finished Jul 29 04:54:33 PM PDT 24
Peak memory 216200 kb
Host smart-63fb49c6-4138-411f-8c61-dbd18e129bf9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416911782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_
shadow_reg_errors_with_csr_rw.416911782 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.347982581
Short name T115
Test name
Test status
Simulation time 294142550 ps
CPU time 3.41 seconds
Started Jul 29 04:54:10 PM PDT 24
Finished Jul 29 04:54:14 PM PDT 24
Peak memory 215992 kb
Host smart-e961452d-6e68-41d2-9c75-bd19929607b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347982581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.347982581 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.237831452
Short name T175
Test name
Test status
Simulation time 360047496 ps
CPU time 4.01 seconds
Started Jul 29 04:54:22 PM PDT 24
Finished Jul 29 04:54:26 PM PDT 24
Peak memory 215928 kb
Host smart-777381b4-f4cb-489c-8995-cb97afb619d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237831452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.237831
452 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.1761547810
Short name T120
Test name
Test status
Simulation time 16519395 ps
CPU time 0.84 seconds
Started Jul 29 04:55:06 PM PDT 24
Finished Jul 29 04:55:07 PM PDT 24
Peak memory 215652 kb
Host smart-80292120-79e2-4b99-a91b-ec4fae3dac6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761547810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.1761547810 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.3325187041
Short name T1049
Test name
Test status
Simulation time 12800609 ps
CPU time 0.76 seconds
Started Jul 29 04:54:52 PM PDT 24
Finished Jul 29 04:54:53 PM PDT 24
Peak memory 215672 kb
Host smart-daa30fe9-9ccf-43cb-9b56-49b2c4f4a420
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325187041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.3325187041 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.1576982833
Short name T166
Test name
Test status
Simulation time 16937287 ps
CPU time 0.81 seconds
Started Jul 29 04:54:55 PM PDT 24
Finished Jul 29 04:55:01 PM PDT 24
Peak memory 215648 kb
Host smart-26a96c78-e3a8-43e8-b7a8-b6f5ba9165bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576982833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.1576982833 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.1083780391
Short name T1046
Test name
Test status
Simulation time 23514902 ps
CPU time 0.84 seconds
Started Jul 29 04:55:08 PM PDT 24
Finished Jul 29 04:55:09 PM PDT 24
Peak memory 215612 kb
Host smart-6f17ad08-7d73-461e-a78a-e55213ccfbfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083780391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.1083780391 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.665647620
Short name T1038
Test name
Test status
Simulation time 14984596 ps
CPU time 0.79 seconds
Started Jul 29 04:54:53 PM PDT 24
Finished Jul 29 04:54:54 PM PDT 24
Peak memory 215668 kb
Host smart-3b1f21ef-0e96-4537-b4ac-728bc0b6821f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665647620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.665647620 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.1980766802
Short name T1120
Test name
Test status
Simulation time 27759933 ps
CPU time 0.76 seconds
Started Jul 29 04:55:00 PM PDT 24
Finished Jul 29 04:55:01 PM PDT 24
Peak memory 215724 kb
Host smart-c1c10f02-5405-4f5b-bc1d-d25d42e37752
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980766802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.1980766802 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.1979212402
Short name T1076
Test name
Test status
Simulation time 13861501 ps
CPU time 0.79 seconds
Started Jul 29 04:54:55 PM PDT 24
Finished Jul 29 04:54:56 PM PDT 24
Peak memory 215660 kb
Host smart-96ee1eaa-28a1-4339-bc0b-98ef4ee49a99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979212402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.1979212402 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.2117336623
Short name T1128
Test name
Test status
Simulation time 38880139 ps
CPU time 0.74 seconds
Started Jul 29 04:54:51 PM PDT 24
Finished Jul 29 04:54:52 PM PDT 24
Peak memory 215368 kb
Host smart-e732f898-5f8a-4ece-b722-24747a651cb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117336623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.2117336623 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.3620067845
Short name T1063
Test name
Test status
Simulation time 25932842 ps
CPU time 0.78 seconds
Started Jul 29 04:54:56 PM PDT 24
Finished Jul 29 04:54:57 PM PDT 24
Peak memory 215644 kb
Host smart-da11d9ab-58e9-4107-b2c1-09f573f4be77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620067845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.3620067845 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.3358272829
Short name T1074
Test name
Test status
Simulation time 24824033 ps
CPU time 0.8 seconds
Started Jul 29 04:54:59 PM PDT 24
Finished Jul 29 04:55:00 PM PDT 24
Peak memory 215624 kb
Host smart-d6eeaab1-8609-4dee-ae57-e9c04bc8df92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358272829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.3358272829 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.2143295522
Short name T1044
Test name
Test status
Simulation time 564689076 ps
CPU time 7.96 seconds
Started Jul 29 04:54:47 PM PDT 24
Finished Jul 29 04:54:55 PM PDT 24
Peak memory 215904 kb
Host smart-36351d6d-a23b-4fab-9e42-225e261a9ae5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143295522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.2143295
522 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.598776272
Short name T990
Test name
Test status
Simulation time 19172734016 ps
CPU time 24.18 seconds
Started Jul 29 04:54:36 PM PDT 24
Finished Jul 29 04:55:01 PM PDT 24
Peak memory 215908 kb
Host smart-d0cdfc71-a783-4984-b406-c22cec022020
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598776272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.59877627
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.733057647
Short name T119
Test name
Test status
Simulation time 35541998 ps
CPU time 1.25 seconds
Started Jul 29 04:54:20 PM PDT 24
Finished Jul 29 04:54:22 PM PDT 24
Peak memory 215840 kb
Host smart-bf8a5266-0521-4cce-a03f-8a879c9b117f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733057647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.73305764
7 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.917665584
Short name T1081
Test name
Test status
Simulation time 158205531 ps
CPU time 1.56 seconds
Started Jul 29 04:54:34 PM PDT 24
Finished Jul 29 04:54:36 PM PDT 24
Peak memory 216868 kb
Host smart-e495501a-b0ac-4e80-a976-1eb1a165b3de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917665584 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.917665584 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.4232191817
Short name T1002
Test name
Test status
Simulation time 76287008 ps
CPU time 0.99 seconds
Started Jul 29 04:54:39 PM PDT 24
Finished Jul 29 04:54:40 PM PDT 24
Peak memory 215672 kb
Host smart-3f31ca68-9e59-4503-8387-3792690f53ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232191817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.4232191817 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.1204011794
Short name T1016
Test name
Test status
Simulation time 31517505 ps
CPU time 0.86 seconds
Started Jul 29 04:54:34 PM PDT 24
Finished Jul 29 04:54:35 PM PDT 24
Peak memory 215324 kb
Host smart-e125e3b9-14fc-495f-a99d-398cd9d55231
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204011794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.1204011794 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.4278197882
Short name T146
Test name
Test status
Simulation time 29012998 ps
CPU time 1.18 seconds
Started Jul 29 04:54:32 PM PDT 24
Finished Jul 29 04:54:34 PM PDT 24
Peak memory 215860 kb
Host smart-dd293057-1e92-415f-b075-f1d046c12a15
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278197882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia
l_access.4278197882 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.320746694
Short name T1071
Test name
Test status
Simulation time 16386509 ps
CPU time 0.76 seconds
Started Jul 29 04:54:41 PM PDT 24
Finished Jul 29 04:54:42 PM PDT 24
Peak memory 215108 kb
Host smart-e793ea67-18c8-48cd-b966-a2cff94359af
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320746694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.320746694 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3317369031
Short name T1047
Test name
Test status
Simulation time 491475940 ps
CPU time 2.25 seconds
Started Jul 29 04:54:51 PM PDT 24
Finished Jul 29 04:54:53 PM PDT 24
Peak memory 215856 kb
Host smart-8170952b-18db-4d59-bad9-fff8682d1371
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317369031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr
_outstanding.3317369031 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.2332730757
Short name T84
Test name
Test status
Simulation time 36313157 ps
CPU time 1.03 seconds
Started Jul 29 04:54:23 PM PDT 24
Finished Jul 29 04:54:24 PM PDT 24
Peak memory 215984 kb
Host smart-b0929b0d-53b6-4a09-a965-c5c745307c10
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332730757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_
errors.2332730757 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.3975411662
Short name T79
Test name
Test status
Simulation time 90182969 ps
CPU time 2.37 seconds
Started Jul 29 04:54:23 PM PDT 24
Finished Jul 29 04:54:26 PM PDT 24
Peak memory 218932 kb
Host smart-71c97426-05a7-48bc-8013-f8134b5a6efa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975411662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac
_shadow_reg_errors_with_csr_rw.3975411662 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.960639022
Short name T1031
Test name
Test status
Simulation time 304214161 ps
CPU time 3.77 seconds
Started Jul 29 04:54:24 PM PDT 24
Finished Jul 29 04:54:28 PM PDT 24
Peak memory 215924 kb
Host smart-bb02bf13-c247-4158-a6c3-3581d3fe6242
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960639022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.960639022 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.2789513833
Short name T181
Test name
Test status
Simulation time 58397948 ps
CPU time 2.41 seconds
Started Jul 29 04:54:15 PM PDT 24
Finished Jul 29 04:54:17 PM PDT 24
Peak memory 215884 kb
Host smart-5d7687ba-55f0-49d0-b429-df3a33621242
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789513833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.27895
13833 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.420475593
Short name T1077
Test name
Test status
Simulation time 43695762 ps
CPU time 0.81 seconds
Started Jul 29 04:54:56 PM PDT 24
Finished Jul 29 04:54:57 PM PDT 24
Peak memory 215568 kb
Host smart-f0b703dc-424b-4540-a500-2bc58fd12699
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420475593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.420475593 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.1447255591
Short name T1048
Test name
Test status
Simulation time 43693049 ps
CPU time 0.78 seconds
Started Jul 29 04:55:07 PM PDT 24
Finished Jul 29 04:55:08 PM PDT 24
Peak memory 215756 kb
Host smart-fb2b71dc-acd2-4318-8fae-7c438dec2b32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447255591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.1447255591 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.1050754703
Short name T1072
Test name
Test status
Simulation time 22992884 ps
CPU time 0.79 seconds
Started Jul 29 04:54:58 PM PDT 24
Finished Jul 29 04:54:59 PM PDT 24
Peak memory 215760 kb
Host smart-5bf18cc1-6611-44d5-b638-ec63a7bd2cd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050754703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.1050754703 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.3037837764
Short name T163
Test name
Test status
Simulation time 12535397 ps
CPU time 0.76 seconds
Started Jul 29 04:54:44 PM PDT 24
Finished Jul 29 04:54:45 PM PDT 24
Peak memory 215620 kb
Host smart-5b2ccc3d-8163-4a8d-9561-4b0829cc3979
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037837764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.3037837764 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.2440338817
Short name T1121
Test name
Test status
Simulation time 16775374 ps
CPU time 0.76 seconds
Started Jul 29 04:55:02 PM PDT 24
Finished Jul 29 04:55:03 PM PDT 24
Peak memory 215652 kb
Host smart-e825dbfc-8def-4bef-8743-f71fd764ba8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440338817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.2440338817 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.1727752009
Short name T164
Test name
Test status
Simulation time 56991085 ps
CPU time 0.82 seconds
Started Jul 29 04:54:59 PM PDT 24
Finished Jul 29 04:55:00 PM PDT 24
Peak memory 215616 kb
Host smart-da5d31e1-b57e-4a0b-9ee6-c245dfc6616e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727752009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.1727752009 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.4082267276
Short name T1036
Test name
Test status
Simulation time 47970504 ps
CPU time 0.83 seconds
Started Jul 29 04:54:53 PM PDT 24
Finished Jul 29 04:54:53 PM PDT 24
Peak memory 215444 kb
Host smart-070ac2aa-c5cf-401c-85c8-4c4427ed720b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082267276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.4082267276 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.3992687087
Short name T1124
Test name
Test status
Simulation time 14378568 ps
CPU time 0.78 seconds
Started Jul 29 04:54:51 PM PDT 24
Finished Jul 29 04:54:51 PM PDT 24
Peak memory 215624 kb
Host smart-cf488a0d-cfbf-420a-a468-9ddb5e19bd2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992687087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.3992687087 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.822823550
Short name T1087
Test name
Test status
Simulation time 58032156 ps
CPU time 0.81 seconds
Started Jul 29 04:54:42 PM PDT 24
Finished Jul 29 04:54:43 PM PDT 24
Peak memory 215672 kb
Host smart-7fb70601-eddd-4a1d-8cb8-d1bc8521d8b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822823550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.822823550 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3078767227
Short name T996
Test name
Test status
Simulation time 70383030 ps
CPU time 2.36 seconds
Started Jul 29 04:54:32 PM PDT 24
Finished Jul 29 04:54:35 PM PDT 24
Peak memory 219836 kb
Host smart-d8bd6a65-538f-4dd6-9f59-370dd22435f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078767227 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.3078767227 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.1838005482
Short name T1117
Test name
Test status
Simulation time 21928809 ps
CPU time 1.05 seconds
Started Jul 29 04:54:35 PM PDT 24
Finished Jul 29 04:54:37 PM PDT 24
Peak memory 215664 kb
Host smart-d142d0e4-3967-494e-9723-834f1ee43e02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838005482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.1838005482 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.430215288
Short name T1085
Test name
Test status
Simulation time 49567109 ps
CPU time 0.8 seconds
Started Jul 29 04:54:55 PM PDT 24
Finished Jul 29 04:54:56 PM PDT 24
Peak memory 215564 kb
Host smart-1dea4297-8f6b-4238-ae82-0dc97afd1cb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430215288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.430215288 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3774548583
Short name T1119
Test name
Test status
Simulation time 175795467 ps
CPU time 2.32 seconds
Started Jul 29 04:54:39 PM PDT 24
Finished Jul 29 04:54:42 PM PDT 24
Peak memory 215840 kb
Host smart-550e0e66-6047-4363-b14b-591a17ea9b07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774548583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr
_outstanding.3774548583 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1427803463
Short name T1114
Test name
Test status
Simulation time 142899705 ps
CPU time 1.74 seconds
Started Jul 29 04:54:36 PM PDT 24
Finished Jul 29 04:54:38 PM PDT 24
Peak memory 219260 kb
Host smart-82cc39ab-251f-4f0e-8549-ca878fc3b287
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427803463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac
_shadow_reg_errors_with_csr_rw.1427803463 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.3500443153
Short name T1057
Test name
Test status
Simulation time 87399168 ps
CPU time 2.89 seconds
Started Jul 29 04:54:26 PM PDT 24
Finished Jul 29 04:54:29 PM PDT 24
Peak memory 215884 kb
Host smart-e9c2d170-54e8-43d5-8ed8-6bccb1527948
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500443153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.3500443153 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.3473243917
Short name T180
Test name
Test status
Simulation time 389286308 ps
CPU time 3.91 seconds
Started Jul 29 04:54:52 PM PDT 24
Finished Jul 29 04:54:56 PM PDT 24
Peak memory 215988 kb
Host smart-603b1c1c-c75e-4c78-9493-b0801735eb2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473243917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.34732
43917 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2012942090
Short name T128
Test name
Test status
Simulation time 116072975 ps
CPU time 2.35 seconds
Started Jul 29 04:54:43 PM PDT 24
Finished Jul 29 04:54:46 PM PDT 24
Peak memory 219944 kb
Host smart-6cbb8ad8-c50d-426d-94e3-e4b922857bb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012942090 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.2012942090 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.1598786181
Short name T1091
Test name
Test status
Simulation time 19757152 ps
CPU time 0.92 seconds
Started Jul 29 04:54:42 PM PDT 24
Finished Jul 29 04:54:43 PM PDT 24
Peak memory 215596 kb
Host smart-c06ed87b-6f41-49c4-857f-118452f959da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598786181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.1598786181 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.374892130
Short name T1021
Test name
Test status
Simulation time 52289758 ps
CPU time 0.76 seconds
Started Jul 29 04:54:41 PM PDT 24
Finished Jul 29 04:54:42 PM PDT 24
Peak memory 215572 kb
Host smart-046306c8-de5e-4e6d-9d83-b5e5b21a8bde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374892130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.374892130 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/6.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.2761330305
Short name T1042
Test name
Test status
Simulation time 79287720 ps
CPU time 1.39 seconds
Started Jul 29 04:54:48 PM PDT 24
Finished Jul 29 04:54:50 PM PDT 24
Peak memory 215964 kb
Host smart-421398a5-1bc4-4bbb-a7d9-6bd2dbce9517
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761330305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr
_outstanding.2761330305 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3835540710
Short name T1107
Test name
Test status
Simulation time 55122038 ps
CPU time 1.16 seconds
Started Jul 29 04:54:45 PM PDT 24
Finished Jul 29 04:54:46 PM PDT 24
Peak memory 216412 kb
Host smart-4ad28e6f-f0e5-4325-b757-a00308b8e1a5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835540710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_
errors.3835540710 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.2775847863
Short name T1125
Test name
Test status
Simulation time 306676019 ps
CPU time 1.79 seconds
Started Jul 29 04:54:52 PM PDT 24
Finished Jul 29 04:54:54 PM PDT 24
Peak memory 218560 kb
Host smart-d1d3b904-4651-4965-afcc-e320498aacd5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775847863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac
_shadow_reg_errors_with_csr_rw.2775847863 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.465963042
Short name T1050
Test name
Test status
Simulation time 431527621 ps
CPU time 3.36 seconds
Started Jul 29 04:54:44 PM PDT 24
Finished Jul 29 04:54:47 PM PDT 24
Peak memory 215920 kb
Host smart-870f4f2c-4063-42e1-b411-6be5b5ddb72a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465963042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.465963042 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.3381857244
Short name T1096
Test name
Test status
Simulation time 60871504 ps
CPU time 2.51 seconds
Started Jul 29 04:54:46 PM PDT 24
Finished Jul 29 04:54:48 PM PDT 24
Peak memory 215964 kb
Host smart-3e390f57-d140-4ce2-9368-e8ee3ed6fb70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381857244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.33818
57244 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.360948577
Short name T1041
Test name
Test status
Simulation time 44661930 ps
CPU time 1.53 seconds
Started Jul 29 04:54:54 PM PDT 24
Finished Jul 29 04:54:56 PM PDT 24
Peak memory 218948 kb
Host smart-677ed36e-f757-4480-a173-cbc58b82edc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360948577 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.360948577 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.234376585
Short name T1015
Test name
Test status
Simulation time 97849691 ps
CPU time 1.17 seconds
Started Jul 29 04:54:20 PM PDT 24
Finished Jul 29 04:54:21 PM PDT 24
Peak memory 215764 kb
Host smart-4b4bf896-b3ef-40d2-9c2a-171e7621a08b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234376585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.234376585 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.1858249002
Short name T1033
Test name
Test status
Simulation time 48129898 ps
CPU time 0.77 seconds
Started Jul 29 04:54:42 PM PDT 24
Finished Jul 29 04:54:43 PM PDT 24
Peak memory 215328 kb
Host smart-540cb010-20b3-416f-b432-e19ae7e323c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858249002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.1858249002 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.2649048456
Short name T995
Test name
Test status
Simulation time 26124155 ps
CPU time 1.55 seconds
Started Jul 29 04:54:34 PM PDT 24
Finished Jul 29 04:54:36 PM PDT 24
Peak memory 215864 kb
Host smart-c300a281-16e5-4ca2-badb-532d98bac60d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649048456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr
_outstanding.2649048456 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.219137443
Short name T83
Test name
Test status
Simulation time 192652391 ps
CPU time 0.95 seconds
Started Jul 29 04:54:39 PM PDT 24
Finished Jul 29 04:54:40 PM PDT 24
Peak memory 215876 kb
Host smart-1201a44a-4da0-497d-b49f-1b9381a05a0b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219137443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_e
rrors.219137443 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.2370901194
Short name T1126
Test name
Test status
Simulation time 50825525 ps
CPU time 2.28 seconds
Started Jul 29 04:54:40 PM PDT 24
Finished Jul 29 04:54:42 PM PDT 24
Peak memory 218908 kb
Host smart-e5efd1cf-b421-4216-81c7-dbd9cf08a9ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370901194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac
_shadow_reg_errors_with_csr_rw.2370901194 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.2172102372
Short name T127
Test name
Test status
Simulation time 94179403 ps
CPU time 2.66 seconds
Started Jul 29 04:54:35 PM PDT 24
Finished Jul 29 04:54:38 PM PDT 24
Peak memory 216004 kb
Host smart-2ecebd9c-30f3-4e9a-9f9d-aa8de91294cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172102372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.2172102372 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.2519082501
Short name T178
Test name
Test status
Simulation time 130462535 ps
CPU time 2.91 seconds
Started Jul 29 04:54:41 PM PDT 24
Finished Jul 29 04:54:44 PM PDT 24
Peak memory 215984 kb
Host smart-aa9c2fbe-e413-4eb5-9bc1-f6c001e0a3f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519082501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.25190
82501 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.575799113
Short name T1100
Test name
Test status
Simulation time 37871777 ps
CPU time 2.45 seconds
Started Jul 29 04:54:42 PM PDT 24
Finished Jul 29 04:54:45 PM PDT 24
Peak memory 221064 kb
Host smart-87a3f5b7-3c47-4f6b-8252-416670c7459c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575799113 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.575799113 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.529579490
Short name T1025
Test name
Test status
Simulation time 63871746 ps
CPU time 0.98 seconds
Started Jul 29 04:54:44 PM PDT 24
Finished Jul 29 04:54:45 PM PDT 24
Peak memory 215576 kb
Host smart-a07ac993-0a9c-42f7-8876-cd1459a34ea1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529579490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.529579490 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.2640954875
Short name T1009
Test name
Test status
Simulation time 10897357 ps
CPU time 0.79 seconds
Started Jul 29 04:54:43 PM PDT 24
Finished Jul 29 04:54:44 PM PDT 24
Peak memory 215584 kb
Host smart-17326df7-de8f-450c-8361-a04862040281
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640954875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.2640954875 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2030791991
Short name T1056
Test name
Test status
Simulation time 403715871 ps
CPU time 2.61 seconds
Started Jul 29 04:54:32 PM PDT 24
Finished Jul 29 04:54:34 PM PDT 24
Peak memory 215892 kb
Host smart-4e7ee536-fa42-4f5a-afb9-90478ad8addb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030791991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr
_outstanding.2030791991 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.1078653333
Short name T1058
Test name
Test status
Simulation time 45412695 ps
CPU time 1.33 seconds
Started Jul 29 04:54:35 PM PDT 24
Finished Jul 29 04:54:37 PM PDT 24
Peak memory 216444 kb
Host smart-e14a7774-c335-410f-82ef-8539230bd608
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078653333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_
errors.1078653333 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2415336198
Short name T1094
Test name
Test status
Simulation time 95393702 ps
CPU time 1.54 seconds
Started Jul 29 04:54:44 PM PDT 24
Finished Jul 29 04:54:45 PM PDT 24
Peak memory 215928 kb
Host smart-be5ec94c-d232-4bda-8166-316452bdaed1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415336198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac
_shadow_reg_errors_with_csr_rw.2415336198 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.3409651519
Short name T168
Test name
Test status
Simulation time 200619591 ps
CPU time 3.42 seconds
Started Jul 29 04:54:47 PM PDT 24
Finished Jul 29 04:54:50 PM PDT 24
Peak memory 215908 kb
Host smart-70cc435a-2313-43ea-88c6-3ccb9f60c987
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409651519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.3409651519 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.1967373724
Short name T1007
Test name
Test status
Simulation time 932877878 ps
CPU time 4.87 seconds
Started Jul 29 04:54:31 PM PDT 24
Finished Jul 29 04:54:36 PM PDT 24
Peak memory 215928 kb
Host smart-f2a65830-8421-4e12-8fd4-c2edaa3c7e39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967373724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.19673
73724 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3542577537
Short name T126
Test name
Test status
Simulation time 67884575 ps
CPU time 1.64 seconds
Started Jul 29 04:54:39 PM PDT 24
Finished Jul 29 04:54:41 PM PDT 24
Peak memory 221144 kb
Host smart-71c90880-8572-4bf9-b7f7-e52e911cde0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542577537 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.3542577537 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.4065681538
Short name T1066
Test name
Test status
Simulation time 20436715 ps
CPU time 1.15 seconds
Started Jul 29 04:54:33 PM PDT 24
Finished Jul 29 04:54:35 PM PDT 24
Peak memory 214840 kb
Host smart-818d303e-ceea-43f5-b49d-802972c7c740
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065681538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.4065681538 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.689231667
Short name T1051
Test name
Test status
Simulation time 19788368 ps
CPU time 0.78 seconds
Started Jul 29 04:54:34 PM PDT 24
Finished Jul 29 04:54:34 PM PDT 24
Peak memory 215684 kb
Host smart-d021ed6f-7132-44a9-adde-80c24c6c3bd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689231667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.689231667 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/9.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.267321045
Short name T1115
Test name
Test status
Simulation time 39496179 ps
CPU time 2.26 seconds
Started Jul 29 04:54:42 PM PDT 24
Finished Jul 29 04:54:44 PM PDT 24
Peak memory 215840 kb
Host smart-d5b2686d-2fa6-49eb-abda-f7f879c83f00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267321045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_
outstanding.267321045 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.430413696
Short name T1079
Test name
Test status
Simulation time 54788923 ps
CPU time 1.28 seconds
Started Jul 29 04:54:39 PM PDT 24
Finished Jul 29 04:54:40 PM PDT 24
Peak memory 217304 kb
Host smart-90b8f35d-3522-478a-bc57-370df73cf699
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430413696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_e
rrors.430413696 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.2992535082
Short name T1105
Test name
Test status
Simulation time 110003819 ps
CPU time 1.54 seconds
Started Jul 29 04:54:36 PM PDT 24
Finished Jul 29 04:54:38 PM PDT 24
Peak memory 216068 kb
Host smart-3728f733-017b-4401-96b0-1a206b8b958e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992535082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac
_shadow_reg_errors_with_csr_rw.2992535082 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.1580174126
Short name T122
Test name
Test status
Simulation time 169369544 ps
CPU time 2.78 seconds
Started Jul 29 04:54:34 PM PDT 24
Finished Jul 29 04:54:42 PM PDT 24
Peak memory 215980 kb
Host smart-998589d7-35b6-467f-95df-34e88466202d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580174126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.1580174126 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.85945340
Short name T183
Test name
Test status
Simulation time 239622656 ps
CPU time 4.53 seconds
Started Jul 29 04:54:44 PM PDT 24
Finished Jul 29 04:54:49 PM PDT 24
Peak memory 215828 kb
Host smart-b6ac1925-ee2a-41e8-8d68-546022fe52f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85945340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.8594534
0 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_alert_test.15982360
Short name T394
Test name
Test status
Simulation time 19265870 ps
CPU time 0.87 seconds
Started Jul 29 04:55:45 PM PDT 24
Finished Jul 29 04:55:46 PM PDT 24
Peak memory 218424 kb
Host smart-213e9ac3-1cf8-4c08-98a0-397e67b628a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15982360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.15982360 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/0.kmac_alert_test/latest

Test location /workspace/coverage/default/0.kmac_app.4072141912
Short name T957
Test name
Test status
Simulation time 17218715612 ps
CPU time 447.54 seconds
Started Jul 29 04:55:39 PM PDT 24
Finished Jul 29 05:03:06 PM PDT 24
Peak memory 528756 kb
Host smart-3bd4e926-f2e4-480e-b0a1-5c90b14701ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072141912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.4072141912 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/0.kmac_app/latest

Test location /workspace/coverage/default/0.kmac_app_with_partial_data.888989022
Short name T358
Test name
Test status
Simulation time 2778697384 ps
CPU time 23.6 seconds
Started Jul 29 04:55:47 PM PDT 24
Finished Jul 29 04:56:10 PM PDT 24
Peak memory 233248 kb
Host smart-a9456e7a-2e7b-4759-9e56-f27ee58327d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888989022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_part
ial_data.888989022 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/0.kmac_burst_write.2555992772
Short name T473
Test name
Test status
Simulation time 23493589963 ps
CPU time 906.52 seconds
Started Jul 29 04:55:40 PM PDT 24
Finished Jul 29 05:10:47 PM PDT 24
Peak memory 251784 kb
Host smart-4bf15a17-8a84-4b8f-b3a0-7660940fec80
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555992772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.2555992772
+enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest

Test location /workspace/coverage/default/0.kmac_edn_timeout_error.1107336325
Short name T507
Test name
Test status
Simulation time 332668487 ps
CPU time 26.93 seconds
Started Jul 29 04:55:49 PM PDT 24
Finished Jul 29 04:56:16 PM PDT 24
Peak memory 228248 kb
Host smart-55ac4efe-fe09-485b-83c2-69020d3d4108
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1107336325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.1107336325 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_mode_error.1873265838
Short name T354
Test name
Test status
Simulation time 342268910 ps
CPU time 7.93 seconds
Started Jul 29 04:55:35 PM PDT 24
Finished Jul 29 04:55:43 PM PDT 24
Peak memory 226600 kb
Host smart-62c78b60-ac56-495c-afa9-dfcc05874ee7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1873265838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.1873265838 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_ready_error.3695802404
Short name T936
Test name
Test status
Simulation time 8223190820 ps
CPU time 21.96 seconds
Started Jul 29 04:55:40 PM PDT 24
Finished Jul 29 04:56:03 PM PDT 24
Peak memory 226880 kb
Host smart-1406e48e-47af-41a4-819b-7b562982042a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695802404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.3695802404 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_refresh.3134272519
Short name T640
Test name
Test status
Simulation time 18263320902 ps
CPU time 153.32 seconds
Started Jul 29 04:55:43 PM PDT 24
Finished Jul 29 04:58:16 PM PDT 24
Peak memory 274244 kb
Host smart-17b6c08c-c319-49a6-aca9-34c47c252cf2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134272519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.31
34272519 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/0.kmac_error.804603270
Short name T160
Test name
Test status
Simulation time 15347371957 ps
CPU time 104.33 seconds
Started Jul 29 04:55:45 PM PDT 24
Finished Jul 29 04:57:29 PM PDT 24
Peak memory 305100 kb
Host smart-926425f7-7b75-4e54-908a-1ce4255995c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804603270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.804603270 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_error/latest

Test location /workspace/coverage/default/0.kmac_key_error.2237254629
Short name T418
Test name
Test status
Simulation time 867874389 ps
CPU time 4.57 seconds
Started Jul 29 04:55:45 PM PDT 24
Finished Jul 29 04:55:55 PM PDT 24
Peak memory 226616 kb
Host smart-4a6ab127-994b-48ae-b958-858d31ce238a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237254629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.2237254629 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest

Test location /workspace/coverage/default/0.kmac_lc_escalation.2866361633
Short name T783
Test name
Test status
Simulation time 125663172 ps
CPU time 1.44 seconds
Started Jul 29 04:55:45 PM PDT 24
Finished Jul 29 04:55:46 PM PDT 24
Peak memory 226768 kb
Host smart-1f29476d-4942-4270-a2b7-cd89779500f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866361633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.2866361633 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/0.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_mubi.3778114457
Short name T439
Test name
Test status
Simulation time 10032899240 ps
CPU time 259.5 seconds
Started Jul 29 04:55:43 PM PDT 24
Finished Jul 29 05:00:03 PM PDT 24
Peak memory 418696 kb
Host smart-f85bc344-698c-4619-a05a-84c4c0036ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778114457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.3778114457 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest

Test location /workspace/coverage/default/0.kmac_sec_cm.2955451928
Short name T104
Test name
Test status
Simulation time 4107742840 ps
CPU time 52.66 seconds
Started Jul 29 04:55:45 PM PDT 24
Finished Jul 29 04:56:38 PM PDT 24
Peak memory 258980 kb
Host smart-52958e4c-dde2-4946-a554-af84ef701c69
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955451928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.2955451928 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/0.kmac_sec_cm/latest

Test location /workspace/coverage/default/0.kmac_sideload.644918623
Short name T386
Test name
Test status
Simulation time 10103908669 ps
CPU time 173.64 seconds
Started Jul 29 04:55:18 PM PDT 24
Finished Jul 29 04:58:11 PM PDT 24
Peak memory 288216 kb
Host smart-4b99e217-91e4-4d0d-842b-a0e1699b54a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644918623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.644918623 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest

Test location /workspace/coverage/default/0.kmac_smoke.3925003595
Short name T381
Test name
Test status
Simulation time 8743327408 ps
CPU time 38.13 seconds
Started Jul 29 04:55:23 PM PDT 24
Finished Jul 29 04:56:01 PM PDT 24
Peak memory 226860 kb
Host smart-e56fe21f-58b9-4421-a6d0-59284ca2c58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925003595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.3925003595 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_smoke/latest

Test location /workspace/coverage/default/0.kmac_stress_all.96710711
Short name T934
Test name
Test status
Simulation time 60297573397 ps
CPU time 2139.47 seconds
Started Jul 29 04:55:32 PM PDT 24
Finished Jul 29 05:31:12 PM PDT 24
Peak memory 637264 kb
Host smart-bac71e7b-13b0-497c-9862-d43d82c841b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=96710711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.96710711 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.3513448320
Short name T560
Test name
Test status
Simulation time 109049090 ps
CPU time 5.88 seconds
Started Jul 29 04:55:44 PM PDT 24
Finished Jul 29 04:55:50 PM PDT 24
Peak memory 218784 kb
Host smart-47217ad0-9b96-4230-9825-e5102205e845
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513448320 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.kmac_test_vectors_kmac.3513448320 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.2588067107
Short name T900
Test name
Test status
Simulation time 850909693 ps
CPU time 6.23 seconds
Started Jul 29 04:55:35 PM PDT 24
Finished Jul 29 04:55:42 PM PDT 24
Peak memory 219744 kb
Host smart-ec923489-4bb0-4a4c-89dd-0daec104bb11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588067107 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.kmac_test_vectors_kmac_xof.2588067107 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.1806227329
Short name T554
Test name
Test status
Simulation time 170679286300 ps
CPU time 2112.22 seconds
Started Jul 29 04:55:45 PM PDT 24
Finished Jul 29 05:30:58 PM PDT 24
Peak memory 1119040 kb
Host smart-c49f8384-9b28-4b5f-8076-4dfd3847ad40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1806227329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.1806227329 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.3227429889
Short name T392
Test name
Test status
Simulation time 30499767081 ps
CPU time 1462.24 seconds
Started Jul 29 04:55:45 PM PDT 24
Finished Jul 29 05:20:08 PM PDT 24
Peak memory 916232 kb
Host smart-34fd80af-5187-4729-90e4-00a2749a556d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3227429889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.3227429889 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_512.1879898950
Short name T266
Test name
Test status
Simulation time 197233097546 ps
CPU time 1693.15 seconds
Started Jul 29 04:55:46 PM PDT 24
Finished Jul 29 05:24:00 PM PDT 24
Peak memory 1667480 kb
Host smart-fecd3b2a-592a-4669-a40d-2aa27e31d663
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1879898950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.1879898950 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_128.2655811302
Short name T189
Test name
Test status
Simulation time 67015333434 ps
CPU time 6261.59 seconds
Started Jul 29 04:55:47 PM PDT 24
Finished Jul 29 06:40:09 PM PDT 24
Peak memory 2657676 kb
Host smart-fa3698bf-3b29-4d5f-ac0b-8671500ff055
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2655811302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.2655811302 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_256.625884023
Short name T464
Test name
Test status
Simulation time 105898754302 ps
CPU time 5068.15 seconds
Started Jul 29 04:55:47 PM PDT 24
Finished Jul 29 06:20:15 PM PDT 24
Peak memory 2215860 kb
Host smart-0f5e0688-3f42-4941-96cc-e4fddf760165
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=625884023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.625884023 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/1.kmac_alert_test.3783434875
Short name T387
Test name
Test status
Simulation time 24267664 ps
CPU time 0.83 seconds
Started Jul 29 04:55:49 PM PDT 24
Finished Jul 29 04:55:50 PM PDT 24
Peak memory 218448 kb
Host smart-e6745e63-df47-4a95-82b3-363a6e9ae937
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783434875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.3783434875 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_alert_test/latest

Test location /workspace/coverage/default/1.kmac_app.2557111507
Short name T211
Test name
Test status
Simulation time 3662297480 ps
CPU time 133.84 seconds
Started Jul 29 04:55:39 PM PDT 24
Finished Jul 29 04:57:53 PM PDT 24
Peak memory 260912 kb
Host smart-fc5cac90-6b7a-45b3-bb7b-50e5f4370f73
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557111507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.2557111507 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/1.kmac_app/latest

Test location /workspace/coverage/default/1.kmac_app_with_partial_data.1515017407
Short name T463
Test name
Test status
Simulation time 15960123970 ps
CPU time 415.68 seconds
Started Jul 29 04:56:00 PM PDT 24
Finished Jul 29 05:02:56 PM PDT 24
Peak memory 492280 kb
Host smart-4cf8fa26-0141-400a-a9f0-37ed8514f6f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515017407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_par
tial_data.1515017407 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/1.kmac_burst_write.2244016233
Short name T148
Test name
Test status
Simulation time 9975521193 ps
CPU time 108.41 seconds
Started Jul 29 04:55:43 PM PDT 24
Finished Jul 29 04:57:32 PM PDT 24
Peak memory 227876 kb
Host smart-0a681aa8-a6f8-4a2a-a82b-f9a2d98d73ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244016233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.2244016233
+enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest

Test location /workspace/coverage/default/1.kmac_edn_timeout_error.3431687640
Short name T269
Test name
Test status
Simulation time 1143716629 ps
CPU time 7.27 seconds
Started Jul 29 04:55:51 PM PDT 24
Finished Jul 29 04:55:58 PM PDT 24
Peak memory 224496 kb
Host smart-f79cade7-0d14-4eeb-a95c-b0bc564221f4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3431687640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.3431687640 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_mode_error.1772856709
Short name T483
Test name
Test status
Simulation time 59850448 ps
CPU time 0.91 seconds
Started Jul 29 04:55:46 PM PDT 24
Finished Jul 29 04:55:50 PM PDT 24
Peak memory 220776 kb
Host smart-9ca30dcb-a0c4-46fb-8843-38355490d4a7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1772856709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.1772856709 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_ready_error.2187326019
Short name T470
Test name
Test status
Simulation time 5610566480 ps
CPU time 18.85 seconds
Started Jul 29 04:55:49 PM PDT 24
Finished Jul 29 04:56:08 PM PDT 24
Peak memory 226936 kb
Host smart-aafa02ca-5895-4838-956a-6e26c3d48403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187326019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.2187326019 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_refresh.510584229
Short name T571
Test name
Test status
Simulation time 31453097132 ps
CPU time 399.63 seconds
Started Jul 29 04:55:39 PM PDT 24
Finished Jul 29 05:02:19 PM PDT 24
Peak memory 344736 kb
Host smart-bc0048aa-437f-422b-ba3a-761e0e496c98
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510584229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.510
584229 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/1.kmac_error.1791161362
Short name T655
Test name
Test status
Simulation time 3075500141 ps
CPU time 241.79 seconds
Started Jul 29 04:55:38 PM PDT 24
Finished Jul 29 04:59:40 PM PDT 24
Peak memory 308708 kb
Host smart-1e7a1a1c-7564-48cb-aa6c-1758fbae961a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791161362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.1791161362 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_error/latest

Test location /workspace/coverage/default/1.kmac_key_error.1745184679
Short name T583
Test name
Test status
Simulation time 7810430613 ps
CPU time 12.34 seconds
Started Jul 29 04:55:42 PM PDT 24
Finished Jul 29 04:55:54 PM PDT 24
Peak memory 226628 kb
Host smart-6e28a777-9e94-4cc2-960f-5c573739afd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745184679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.1745184679 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_key_error/latest

Test location /workspace/coverage/default/1.kmac_lc_escalation.4089729990
Short name T937
Test name
Test status
Simulation time 154344002 ps
CPU time 1.43 seconds
Started Jul 29 04:55:44 PM PDT 24
Finished Jul 29 04:55:45 PM PDT 24
Peak memory 226860 kb
Host smart-f86ee29e-265f-4198-9d4e-f0e23f6b9c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089729990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.4089729990 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/1.kmac_lc_escalation/latest

Test location /workspace/coverage/default/1.kmac_long_msg_and_output.192838405
Short name T476
Test name
Test status
Simulation time 232645174450 ps
CPU time 1902.93 seconds
Started Jul 29 04:55:44 PM PDT 24
Finished Jul 29 05:27:28 PM PDT 24
Peak memory 1889564 kb
Host smart-c1e31da7-1ac9-4f7a-920f-925990bc6592
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192838405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and
_output.192838405 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/1.kmac_mubi.2472195716
Short name T47
Test name
Test status
Simulation time 3151409502 ps
CPU time 167.66 seconds
Started Jul 29 04:55:43 PM PDT 24
Finished Jul 29 04:58:30 PM PDT 24
Peak memory 283156 kb
Host smart-118cb299-29df-4bd1-b9cc-7c34c76f7cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472195716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.2472195716 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mubi/latest

Test location /workspace/coverage/default/1.kmac_sideload.2255075172
Short name T690
Test name
Test status
Simulation time 5592483568 ps
CPU time 182.9 seconds
Started Jul 29 04:55:41 PM PDT 24
Finished Jul 29 04:58:44 PM PDT 24
Peak memory 382744 kb
Host smart-e5352625-49c2-4ea7-9cf3-794e58eab10c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255075172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.2255075172 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest

Test location /workspace/coverage/default/1.kmac_smoke.1020068909
Short name T975
Test name
Test status
Simulation time 1644594267 ps
CPU time 51.11 seconds
Started Jul 29 04:55:41 PM PDT 24
Finished Jul 29 04:56:33 PM PDT 24
Peak memory 226752 kb
Host smart-11c7ada4-e586-4bd1-88c5-2622f0c12848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020068909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.1020068909 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest

Test location /workspace/coverage/default/1.kmac_stress_all.1120868684
Short name T678
Test name
Test status
Simulation time 11213095755 ps
CPU time 510.44 seconds
Started Jul 29 04:56:08 PM PDT 24
Finished Jul 29 05:04:38 PM PDT 24
Peak memory 464040 kb
Host smart-54a5ed59-91ec-4395-9359-eb978a714436
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1120868684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.1120868684 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.241105740
Short name T801
Test name
Test status
Simulation time 723821243 ps
CPU time 6.17 seconds
Started Jul 29 04:55:44 PM PDT 24
Finished Jul 29 04:55:50 PM PDT 24
Peak memory 219660 kb
Host smart-b611132d-6b81-4d3d-892c-6483a66ea3ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241105740 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.kmac_test_vectors_kmac.241105740 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.297504437
Short name T214
Test name
Test status
Simulation time 230277989 ps
CPU time 6.91 seconds
Started Jul 29 04:55:39 PM PDT 24
Finished Jul 29 04:55:46 PM PDT 24
Peak memory 219696 kb
Host smart-ca3e5eb5-f27b-4133-8eb8-22e00cdb96eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297504437 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.kmac_test_vectors_kmac_xof.297504437 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.616538818
Short name T369
Test name
Test status
Simulation time 47205100986 ps
CPU time 2167.91 seconds
Started Jul 29 04:55:40 PM PDT 24
Finished Jul 29 05:31:48 PM PDT 24
Peak memory 2343676 kb
Host smart-44b5b04a-2126-40a9-9109-32d02a285448
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=616538818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.616538818 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.3690867783
Short name T920
Test name
Test status
Simulation time 47431804998 ps
CPU time 1415.78 seconds
Started Jul 29 04:55:54 PM PDT 24
Finished Jul 29 05:19:30 PM PDT 24
Peak memory 713200 kb
Host smart-372a488a-a6b4-4317-81e1-2810cc5f40df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3690867783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.3690867783 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_256.2422881514
Short name T453
Test name
Test status
Simulation time 99899448459 ps
CPU time 5528.39 seconds
Started Jul 29 04:55:44 PM PDT 24
Finished Jul 29 06:27:53 PM PDT 24
Peak memory 2241992 kb
Host smart-526c50ba-9b2c-4dd8-8295-ad7d816fafd8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2422881514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.2422881514 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/10.kmac_app.75792618
Short name T170
Test name
Test status
Simulation time 31042541537 ps
CPU time 313.34 seconds
Started Jul 29 04:56:12 PM PDT 24
Finished Jul 29 05:01:25 PM PDT 24
Peak memory 448796 kb
Host smart-d3c8e954-e4bc-411a-9d21-cda03dccc5e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75792618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.75792618 +enable_masking=1
+sw_key_masked=0
Directory /workspace/10.kmac_app/latest

Test location /workspace/coverage/default/10.kmac_burst_write.546662038
Short name T890
Test name
Test status
Simulation time 168015122114 ps
CPU time 1407.12 seconds
Started Jul 29 04:55:58 PM PDT 24
Finished Jul 29 05:19:25 PM PDT 24
Peak memory 264168 kb
Host smart-b10b6c26-1174-4ae9-b0dc-fc59f4cb7901
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546662038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.546662038
+enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest

Test location /workspace/coverage/default/10.kmac_edn_timeout_error.1441505805
Short name T107
Test name
Test status
Simulation time 156674279 ps
CPU time 5.37 seconds
Started Jul 29 04:56:15 PM PDT 24
Finished Jul 29 04:56:20 PM PDT 24
Peak memory 219700 kb
Host smart-b0a3f6ab-7f15-44f1-b3da-6f00c1d1c5c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1441505805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.1441505805 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_mode_error.3323248255
Short name T698
Test name
Test status
Simulation time 38147180 ps
CPU time 1.08 seconds
Started Jul 29 04:55:53 PM PDT 24
Finished Jul 29 04:55:54 PM PDT 24
Peak memory 222316 kb
Host smart-c9b4e4d8-ba04-4c58-bd0f-4e707310ea70
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3323248255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.3323248255 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_refresh.2375262347
Short name T970
Test name
Test status
Simulation time 2910537198 ps
CPU time 80.54 seconds
Started Jul 29 04:56:05 PM PDT 24
Finished Jul 29 04:57:25 PM PDT 24
Peak memory 287172 kb
Host smart-dbf479f3-eba4-4569-970b-b533c3309d2e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375262347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.2
375262347 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/10.kmac_error.1857000028
Short name T866
Test name
Test status
Simulation time 18653854436 ps
CPU time 381.31 seconds
Started Jul 29 04:55:51 PM PDT 24
Finished Jul 29 05:02:13 PM PDT 24
Peak memory 357672 kb
Host smart-ad8815fa-0093-4e04-99c9-569eaa3d2613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857000028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.1857000028 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest

Test location /workspace/coverage/default/10.kmac_key_error.3816141596
Short name T608
Test name
Test status
Simulation time 396876935 ps
CPU time 2.34 seconds
Started Jul 29 04:56:07 PM PDT 24
Finished Jul 29 04:56:10 PM PDT 24
Peak memory 226632 kb
Host smart-5b322bf0-7221-4627-b805-851af00c898b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816141596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.3816141596 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest

Test location /workspace/coverage/default/10.kmac_lc_escalation.3166395139
Short name T776
Test name
Test status
Simulation time 89127504 ps
CPU time 1.42 seconds
Started Jul 29 04:56:13 PM PDT 24
Finished Jul 29 04:56:20 PM PDT 24
Peak memory 226852 kb
Host smart-cfa2ffc6-b93d-41d4-a8c8-3470fe27e2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166395139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.3166395139 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/10.kmac_lc_escalation/latest

Test location /workspace/coverage/default/10.kmac_long_msg_and_output.1914577141
Short name T978
Test name
Test status
Simulation time 53629828248 ps
CPU time 2909.61 seconds
Started Jul 29 04:56:09 PM PDT 24
Finished Jul 29 05:44:39 PM PDT 24
Peak memory 2699180 kb
Host smart-88911289-0e25-497a-bb45-819fc9cfeb6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914577141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_a
nd_output.1914577141 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/10.kmac_sideload.175850683
Short name T108
Test name
Test status
Simulation time 6195529023 ps
CPU time 524.36 seconds
Started Jul 29 04:56:20 PM PDT 24
Finished Jul 29 05:05:04 PM PDT 24
Peak memory 404160 kb
Host smart-70c6cb85-93b8-42c9-a141-8769f992c355
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175850683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.175850683 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_sideload/latest

Test location /workspace/coverage/default/10.kmac_smoke.2305989856
Short name T561
Test name
Test status
Simulation time 1390782095 ps
CPU time 27.18 seconds
Started Jul 29 04:56:11 PM PDT 24
Finished Jul 29 04:56:39 PM PDT 24
Peak memory 226936 kb
Host smart-8427d6b1-4e71-43ea-b2fd-5a9642a4c68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305989856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.2305989856 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac.3365273849
Short name T391
Test name
Test status
Simulation time 118816285 ps
CPU time 5.65 seconds
Started Jul 29 04:55:54 PM PDT 24
Finished Jul 29 04:56:05 PM PDT 24
Peak memory 219780 kb
Host smart-86ccd8ab-283f-417f-8446-52c135e74e7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365273849 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.kmac_test_vectors_kmac.3365273849 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac_xof.1402269826
Short name T566
Test name
Test status
Simulation time 309286920 ps
CPU time 5.84 seconds
Started Jul 29 04:56:06 PM PDT 24
Finished Jul 29 04:56:12 PM PDT 24
Peak memory 219660 kb
Host smart-f3263bba-e559-4f62-8cfd-d5d31d3ec02b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402269826 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.kmac_test_vectors_kmac_xof.1402269826 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_256.292017512
Short name T597
Test name
Test status
Simulation time 91736778863 ps
CPU time 3377.3 seconds
Started Jul 29 04:56:13 PM PDT 24
Finished Jul 29 05:52:31 PM PDT 24
Peak memory 3063528 kb
Host smart-81fbba94-ac00-4a9d-bbfe-0fdf4d7b4596
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=292017512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.292017512 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_384.1619870767
Short name T275
Test name
Test status
Simulation time 122874337801 ps
CPU time 2190.45 seconds
Started Jul 29 04:56:16 PM PDT 24
Finished Jul 29 05:32:47 PM PDT 24
Peak memory 2411880 kb
Host smart-878da6e4-6245-4abb-b563-d7fb8d8075e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1619870767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.1619870767 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_512.137261706
Short name T785
Test name
Test status
Simulation time 151445745352 ps
CPU time 1616.22 seconds
Started Jul 29 04:56:15 PM PDT 24
Finished Jul 29 05:23:12 PM PDT 24
Peak memory 1725180 kb
Host smart-1c8dd847-9240-4606-b4d4-30cfe21bf98c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=137261706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.137261706 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/11.kmac_alert_test.3650912869
Short name T550
Test name
Test status
Simulation time 28267204 ps
CPU time 0.83 seconds
Started Jul 29 04:56:19 PM PDT 24
Finished Jul 29 04:56:20 PM PDT 24
Peak memory 218408 kb
Host smart-ca01accf-30d2-41a9-959b-3ad09702d24e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650912869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.3650912869 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_alert_test/latest

Test location /workspace/coverage/default/11.kmac_app.1601518198
Short name T471
Test name
Test status
Simulation time 6102332411 ps
CPU time 323.49 seconds
Started Jul 29 04:56:00 PM PDT 24
Finished Jul 29 05:01:23 PM PDT 24
Peak memory 333700 kb
Host smart-c83087f0-8b37-4556-a5bc-f4f3084d44ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601518198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.1601518198 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/11.kmac_app/latest

Test location /workspace/coverage/default/11.kmac_burst_write.3322248881
Short name T814
Test name
Test status
Simulation time 28157900023 ps
CPU time 1240.55 seconds
Started Jul 29 04:56:01 PM PDT 24
Finished Jul 29 05:16:42 PM PDT 24
Peak memory 260080 kb
Host smart-4357cf82-a89a-4f15-8a71-b8c33f93660f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322248881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.332224888
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest

Test location /workspace/coverage/default/11.kmac_error.365161392
Short name T859
Test name
Test status
Simulation time 17400773493 ps
CPU time 490.04 seconds
Started Jul 29 04:55:46 PM PDT 24
Finished Jul 29 05:03:56 PM PDT 24
Peak memory 601860 kb
Host smart-e788ad3f-b54a-4f00-b643-7f17f535f69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365161392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.365161392 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest

Test location /workspace/coverage/default/11.kmac_key_error.1670795690
Short name T745
Test name
Test status
Simulation time 394367842 ps
CPU time 3.62 seconds
Started Jul 29 04:56:21 PM PDT 24
Finished Jul 29 04:56:25 PM PDT 24
Peak memory 226568 kb
Host smart-13309e44-19ef-44d8-b8b6-5fc66ee6676f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670795690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.1670795690 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_key_error/latest

Test location /workspace/coverage/default/11.kmac_lc_escalation.687555954
Short name T822
Test name
Test status
Simulation time 121345452 ps
CPU time 1.22 seconds
Started Jul 29 04:55:57 PM PDT 24
Finished Jul 29 04:55:59 PM PDT 24
Peak memory 226804 kb
Host smart-7ea146aa-bc21-4196-9904-a6b944cd9500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687555954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.687555954 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/11.kmac_lc_escalation/latest

Test location /workspace/coverage/default/11.kmac_long_msg_and_output.1842087143
Short name T505
Test name
Test status
Simulation time 55003521428 ps
CPU time 1210.49 seconds
Started Jul 29 04:56:01 PM PDT 24
Finished Jul 29 05:16:11 PM PDT 24
Peak memory 852392 kb
Host smart-20692fcd-f0e0-4209-b171-4c36b972bc29
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842087143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_a
nd_output.1842087143 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/11.kmac_sideload.2478681297
Short name T141
Test name
Test status
Simulation time 4734612079 ps
CPU time 210.41 seconds
Started Jul 29 04:56:02 PM PDT 24
Finished Jul 29 04:59:32 PM PDT 24
Peak memory 292964 kb
Host smart-573ce700-493a-4506-a4b3-1c5a5e4bfc00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478681297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.2478681297 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest

Test location /workspace/coverage/default/11.kmac_smoke.1554019763
Short name T213
Test name
Test status
Simulation time 4834587880 ps
CPU time 96.89 seconds
Started Jul 29 04:55:55 PM PDT 24
Finished Jul 29 04:57:32 PM PDT 24
Peak memory 230064 kb
Host smart-e05c3f16-690b-404e-948b-e0a2d96801d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554019763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.1554019763 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest

Test location /workspace/coverage/default/11.kmac_stress_all.2859232547
Short name T498
Test name
Test status
Simulation time 197676039416 ps
CPU time 1460.77 seconds
Started Jul 29 04:56:17 PM PDT 24
Finished Jul 29 05:20:38 PM PDT 24
Peak memory 1730448 kb
Host smart-f0718ca6-891a-43b0-9395-ba0aba2e1df0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2859232547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.2859232547 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac.725124123
Short name T427
Test name
Test status
Simulation time 1031288042 ps
CPU time 7.03 seconds
Started Jul 29 04:55:55 PM PDT 24
Finished Jul 29 04:56:02 PM PDT 24
Peak memory 218828 kb
Host smart-ba1ac682-e64b-4f8a-be0f-6c481693a0ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725124123 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.kmac_test_vectors_kmac.725124123 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac_xof.908640035
Short name T806
Test name
Test status
Simulation time 280965106 ps
CPU time 6.98 seconds
Started Jul 29 04:56:08 PM PDT 24
Finished Jul 29 04:56:15 PM PDT 24
Peak memory 219632 kb
Host smart-8a532fea-9d5a-4870-a7ef-f9f17b04af29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908640035 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.kmac_test_vectors_kmac_xof.908640035 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_224.323188288
Short name T691
Test name
Test status
Simulation time 137220617527 ps
CPU time 3411.58 seconds
Started Jul 29 04:56:17 PM PDT 24
Finished Jul 29 05:53:09 PM PDT 24
Peak memory 3211092 kb
Host smart-afe08274-4d02-4928-9f28-9fc96d9f3af5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=323188288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.323188288 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_256.4257940400
Short name T956
Test name
Test status
Simulation time 84513764136 ps
CPU time 3422.45 seconds
Started Jul 29 04:56:02 PM PDT 24
Finished Jul 29 05:53:05 PM PDT 24
Peak memory 3107784 kb
Host smart-7db82fd6-b1d4-4b69-aa5c-f9e566505bfe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4257940400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.4257940400 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_384.48378276
Short name T940
Test name
Test status
Simulation time 14437418243 ps
CPU time 1629.59 seconds
Started Jul 29 04:56:07 PM PDT 24
Finished Jul 29 05:23:17 PM PDT 24
Peak memory 892808 kb
Host smart-ef66c0c3-0643-4791-9ffc-7734fb5fd2e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=48378276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.48378276 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_512.3503812692
Short name T264
Test name
Test status
Simulation time 10468846963 ps
CPU time 1172.09 seconds
Started Jul 29 04:56:08 PM PDT 24
Finished Jul 29 05:15:40 PM PDT 24
Peak memory 698768 kb
Host smart-54f0ec4c-4832-42de-bf81-1a6e5c766837
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3503812692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.3503812692 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/12.kmac_alert_test.1521413633
Short name T366
Test name
Test status
Simulation time 52346809 ps
CPU time 0.89 seconds
Started Jul 29 04:56:09 PM PDT 24
Finished Jul 29 04:56:10 PM PDT 24
Peak memory 218348 kb
Host smart-951372f8-4e58-47de-8fec-7ec664ceccfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521413633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.1521413633 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest

Test location /workspace/coverage/default/12.kmac_app.149971146
Short name T546
Test name
Test status
Simulation time 27920322806 ps
CPU time 167.45 seconds
Started Jul 29 04:56:25 PM PDT 24
Finished Jul 29 04:59:13 PM PDT 24
Peak memory 351212 kb
Host smart-39d87bc3-a422-4a3c-ba22-00a212e29fc3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149971146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.149971146 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest

Test location /workspace/coverage/default/12.kmac_burst_write.559441610
Short name T644
Test name
Test status
Simulation time 31079274261 ps
CPU time 169.54 seconds
Started Jul 29 04:56:30 PM PDT 24
Finished Jul 29 04:59:20 PM PDT 24
Peak memory 230516 kb
Host smart-36426a49-9af3-4300-9751-7787e243bfb6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559441610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.559441610
+enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest

Test location /workspace/coverage/default/12.kmac_edn_timeout_error.2128625838
Short name T367
Test name
Test status
Simulation time 89395603 ps
CPU time 1.12 seconds
Started Jul 29 04:56:21 PM PDT 24
Finished Jul 29 04:56:22 PM PDT 24
Peak memory 218600 kb
Host smart-7675e60f-6313-43c7-afff-d97e73ae9e07
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2128625838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.2128625838 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_mode_error.1533767272
Short name T927
Test name
Test status
Simulation time 28613617 ps
CPU time 1.01 seconds
Started Jul 29 04:56:31 PM PDT 24
Finished Jul 29 04:56:32 PM PDT 24
Peak memory 222104 kb
Host smart-77011591-483c-411d-9d99-74eae075ff8e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1533767272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.1533767272 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_refresh.3168454774
Short name T57
Test name
Test status
Simulation time 4513702267 ps
CPU time 167.25 seconds
Started Jul 29 04:55:55 PM PDT 24
Finished Jul 29 04:58:43 PM PDT 24
Peak memory 275824 kb
Host smart-706c3543-7aa5-4a8a-8128-5354902b0d11
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168454774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.3
168454774 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/12.kmac_error.2576712883
Short name T334
Test name
Test status
Simulation time 55089897674 ps
CPU time 369.93 seconds
Started Jul 29 04:56:34 PM PDT 24
Finished Jul 29 05:02:45 PM PDT 24
Peak memory 500572 kb
Host smart-fa7d13dc-220b-4b68-bd4b-e6b151248fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576712883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.2576712883 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_error/latest

Test location /workspace/coverage/default/12.kmac_key_error.3060075856
Short name T556
Test name
Test status
Simulation time 1803481561 ps
CPU time 6.74 seconds
Started Jul 29 04:56:20 PM PDT 24
Finished Jul 29 04:56:27 PM PDT 24
Peak memory 226660 kb
Host smart-008ba394-ac50-417d-80c1-fe064ac61c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060075856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.3060075856 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_lc_escalation.83921297
Short name T52
Test name
Test status
Simulation time 2716573343 ps
CPU time 44.73 seconds
Started Jul 29 04:56:12 PM PDT 24
Finished Jul 29 04:56:57 PM PDT 24
Peak memory 247140 kb
Host smart-24eb02ba-6875-486b-b39e-3df041dbb885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83921297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.83921297 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_lc_escalation/latest

Test location /workspace/coverage/default/12.kmac_long_msg_and_output.676477406
Short name T105
Test name
Test status
Simulation time 21778784496 ps
CPU time 2850.14 seconds
Started Jul 29 04:56:01 PM PDT 24
Finished Jul 29 05:43:32 PM PDT 24
Peak memory 1513964 kb
Host smart-cd9f6581-e332-455e-b83e-64ffdbb35100
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676477406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_an
d_output.676477406 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/12.kmac_sideload.3586889648
Short name T290
Test name
Test status
Simulation time 37133325674 ps
CPU time 324.91 seconds
Started Jul 29 04:56:33 PM PDT 24
Finished Jul 29 05:01:59 PM PDT 24
Peak memory 475548 kb
Host smart-6049f428-fdda-4869-9ccc-7297ac2622b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586889648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.3586889648 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest

Test location /workspace/coverage/default/12.kmac_smoke.3140391117
Short name T299
Test name
Test status
Simulation time 6269054529 ps
CPU time 35.18 seconds
Started Jul 29 04:56:09 PM PDT 24
Finished Jul 29 04:56:44 PM PDT 24
Peak memory 226884 kb
Host smart-0339bf4d-e17c-46b9-8b79-9a198c0154e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140391117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.3140391117 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest

Test location /workspace/coverage/default/12.kmac_stress_all.4065341646
Short name T494
Test name
Test status
Simulation time 70204064747 ps
CPU time 2547.11 seconds
Started Jul 29 04:56:11 PM PDT 24
Finished Jul 29 05:38:38 PM PDT 24
Peak memory 1160060 kb
Host smart-90acfc99-a882-461f-8f17-0ce9889db1b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4065341646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.4065341646 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac.2276120369
Short name T368
Test name
Test status
Simulation time 371135109 ps
CPU time 5.72 seconds
Started Jul 29 04:55:59 PM PDT 24
Finished Jul 29 04:56:04 PM PDT 24
Peak memory 218872 kb
Host smart-dd6dcefd-f62b-42e8-833e-3f3db2b8a9d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276120369 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.kmac_test_vectors_kmac.2276120369 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac_xof.135499078
Short name T457
Test name
Test status
Simulation time 119881706 ps
CPU time 5.92 seconds
Started Jul 29 04:56:05 PM PDT 24
Finished Jul 29 04:56:11 PM PDT 24
Peak memory 218820 kb
Host smart-d5da8599-ce78-4349-91d4-3a6e9249e993
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135499078 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.kmac_test_vectors_kmac_xof.135499078 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_224.415057875
Short name T363
Test name
Test status
Simulation time 371360287937 ps
CPU time 3491.75 seconds
Started Jul 29 04:56:22 PM PDT 24
Finished Jul 29 05:54:34 PM PDT 24
Peak memory 3255780 kb
Host smart-f7f8cacb-7860-47bc-a325-e0ad823396da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=415057875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.415057875 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_256.614369617
Short name T651
Test name
Test status
Simulation time 80517539948 ps
CPU time 1979.93 seconds
Started Jul 29 04:56:22 PM PDT 24
Finished Jul 29 05:29:22 PM PDT 24
Peak memory 1146708 kb
Host smart-778e59ec-372f-4f35-81b3-6b102cf72b34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=614369617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.614369617 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_384.2066299307
Short name T346
Test name
Test status
Simulation time 49191143844 ps
CPU time 2334.82 seconds
Started Jul 29 04:56:23 PM PDT 24
Finished Jul 29 05:35:18 PM PDT 24
Peak memory 2394804 kb
Host smart-f792bcf9-4bd7-43fc-926b-97d0e396a383
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2066299307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.2066299307 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_512.285633699
Short name T509
Test name
Test status
Simulation time 52562976176 ps
CPU time 1695.09 seconds
Started Jul 29 04:56:07 PM PDT 24
Finished Jul 29 05:24:23 PM PDT 24
Peak memory 1720456 kb
Host smart-75bddf9b-fa03-455e-a1b8-e0d6d8435e5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=285633699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.285633699 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/13.kmac_alert_test.827685770
Short name T918
Test name
Test status
Simulation time 16554916 ps
CPU time 0.79 seconds
Started Jul 29 04:56:09 PM PDT 24
Finished Jul 29 04:56:10 PM PDT 24
Peak memory 218392 kb
Host smart-0a7c4867-05f2-44b4-bbda-392ed9e23808
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827685770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.827685770 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest

Test location /workspace/coverage/default/13.kmac_app.2277075806
Short name T484
Test name
Test status
Simulation time 14816882800 ps
CPU time 146.85 seconds
Started Jul 29 04:56:08 PM PDT 24
Finished Jul 29 04:58:35 PM PDT 24
Peak memory 272356 kb
Host smart-9a54370b-a005-4f2e-ac54-370574c521f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277075806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.2277075806 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/13.kmac_app/latest

Test location /workspace/coverage/default/13.kmac_burst_write.3304933656
Short name T599
Test name
Test status
Simulation time 6756901497 ps
CPU time 444.08 seconds
Started Jul 29 04:55:52 PM PDT 24
Finished Jul 29 05:03:16 PM PDT 24
Peak memory 233060 kb
Host smart-9060b450-d519-444c-9f43-5152d35bf235
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304933656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.330493365
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest

Test location /workspace/coverage/default/13.kmac_edn_timeout_error.174241255
Short name T830
Test name
Test status
Simulation time 39370780 ps
CPU time 1.21 seconds
Started Jul 29 04:56:22 PM PDT 24
Finished Jul 29 04:56:24 PM PDT 24
Peak memory 218680 kb
Host smart-f8690339-2114-454b-9a57-ee77826cc6e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=174241255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.174241255 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_mode_error.1817705808
Short name T37
Test name
Test status
Simulation time 205338203 ps
CPU time 4.72 seconds
Started Jul 29 04:55:59 PM PDT 24
Finished Jul 29 04:56:04 PM PDT 24
Peak memory 226596 kb
Host smart-9ba460b2-0e10-4a45-9fd3-2b7bdcb309f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1817705808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.1817705808 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_refresh.1829221768
Short name T673
Test name
Test status
Simulation time 19143585359 ps
CPU time 95.16 seconds
Started Jul 29 04:55:56 PM PDT 24
Finished Jul 29 04:57:31 PM PDT 24
Peak memory 286456 kb
Host smart-06d70a65-0d4c-478b-91e2-e519ccb5f21f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829221768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.1
829221768 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/13.kmac_error.99357608
Short name T344
Test name
Test status
Simulation time 40177167233 ps
CPU time 566.05 seconds
Started Jul 29 04:56:32 PM PDT 24
Finished Jul 29 05:05:58 PM PDT 24
Peak memory 638800 kb
Host smart-8e5c8bd7-d6e8-456b-a603-23cdb5454a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99357608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.99357608 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest

Test location /workspace/coverage/default/13.kmac_key_error.184614628
Short name T516
Test name
Test status
Simulation time 473181502 ps
CPU time 2.86 seconds
Started Jul 29 04:55:57 PM PDT 24
Finished Jul 29 04:56:00 PM PDT 24
Peak memory 226560 kb
Host smart-2ceaa6d4-90f7-408a-a7ad-9019479010f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184614628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.184614628 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest

Test location /workspace/coverage/default/13.kmac_lc_escalation.2401276625
Short name T38
Test name
Test status
Simulation time 38778042 ps
CPU time 1.44 seconds
Started Jul 29 04:56:16 PM PDT 24
Finished Jul 29 04:56:18 PM PDT 24
Peak memory 226764 kb
Host smart-831d7d40-f0d8-4391-8731-1e770533fc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401276625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.2401276625 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/13.kmac_lc_escalation/latest

Test location /workspace/coverage/default/13.kmac_long_msg_and_output.2608173635
Short name T249
Test name
Test status
Simulation time 15277934191 ps
CPU time 1857.7 seconds
Started Jul 29 04:56:37 PM PDT 24
Finished Jul 29 05:27:35 PM PDT 24
Peak memory 1092196 kb
Host smart-dc1ebcb7-11c9-4bb7-83de-b0a8ff19d70e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608173635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_a
nd_output.2608173635 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/13.kmac_sideload.2666800218
Short name T197
Test name
Test status
Simulation time 19030533012 ps
CPU time 390.23 seconds
Started Jul 29 04:56:17 PM PDT 24
Finished Jul 29 05:02:47 PM PDT 24
Peak memory 494940 kb
Host smart-fa5d3bfa-e7d0-43cb-b415-7b5432da5379
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666800218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.2666800218 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest

Test location /workspace/coverage/default/13.kmac_smoke.1557456006
Short name T193
Test name
Test status
Simulation time 7609431567 ps
CPU time 68.35 seconds
Started Jul 29 04:56:12 PM PDT 24
Finished Jul 29 04:57:20 PM PDT 24
Peak memory 221632 kb
Host smart-7fc9f215-6c9f-47c3-ba7b-c7f0bbe366b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557456006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.1557456006 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest

Test location /workspace/coverage/default/13.kmac_stress_all.3807830184
Short name T730
Test name
Test status
Simulation time 169076093807 ps
CPU time 3046.01 seconds
Started Jul 29 04:56:11 PM PDT 24
Finished Jul 29 05:46:58 PM PDT 24
Peak memory 1679700 kb
Host smart-de8ad58e-ef90-46eb-944a-ff685566d435
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3807830184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.3807830184 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac.697333749
Short name T793
Test name
Test status
Simulation time 461264925 ps
CPU time 5.7 seconds
Started Jul 29 04:56:11 PM PDT 24
Finished Jul 29 04:56:16 PM PDT 24
Peak memory 219672 kb
Host smart-83e1aa42-a8d8-42bf-97d9-595cc9bbfa4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697333749 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.kmac_test_vectors_kmac.697333749 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac_xof.2960668158
Short name T518
Test name
Test status
Simulation time 108145241 ps
CPU time 6.02 seconds
Started Jul 29 04:56:11 PM PDT 24
Finished Jul 29 04:56:17 PM PDT 24
Peak memory 219692 kb
Host smart-d58a0892-e3f9-4583-92b2-3a6877f0f75c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960668158 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.kmac_test_vectors_kmac_xof.2960668158 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_224.1066662819
Short name T530
Test name
Test status
Simulation time 100744258851 ps
CPU time 3493.7 seconds
Started Jul 29 04:56:01 PM PDT 24
Finished Jul 29 05:54:15 PM PDT 24
Peak memory 3210200 kb
Host smart-5f780c04-cbbb-4723-bb34-25b29700ce81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1066662819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.1066662819 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_256.3690687005
Short name T307
Test name
Test status
Simulation time 67113518534 ps
CPU time 2227.79 seconds
Started Jul 29 04:56:33 PM PDT 24
Finished Jul 29 05:33:41 PM PDT 24
Peak memory 1165756 kb
Host smart-348b5090-2d7f-4f7b-ab56-7e82b5c41bc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3690687005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.3690687005 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_384.2787238394
Short name T960
Test name
Test status
Simulation time 81382119849 ps
CPU time 2705.81 seconds
Started Jul 29 04:56:12 PM PDT 24
Finished Jul 29 05:41:18 PM PDT 24
Peak memory 2456388 kb
Host smart-62ac730f-1cc2-446f-8f90-eb302c824be8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2787238394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.2787238394 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_512.937580664
Short name T948
Test name
Test status
Simulation time 42004935788 ps
CPU time 1349.54 seconds
Started Jul 29 04:56:10 PM PDT 24
Finished Jul 29 05:18:40 PM PDT 24
Peak memory 721940 kb
Host smart-b6292ec1-79d6-46c7-815b-dcaad955b364
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=937580664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.937580664 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/14.kmac_alert_test.1059712878
Short name T777
Test name
Test status
Simulation time 22179466 ps
CPU time 0.8 seconds
Started Jul 29 04:56:21 PM PDT 24
Finished Jul 29 04:56:22 PM PDT 24
Peak memory 218476 kb
Host smart-2c3bf16b-b39b-49ce-b860-5d594c844b14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059712878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.1059712878 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_alert_test/latest

Test location /workspace/coverage/default/14.kmac_burst_write.197211610
Short name T932
Test name
Test status
Simulation time 384508563746 ps
CPU time 1066.84 seconds
Started Jul 29 04:56:21 PM PDT 24
Finished Jul 29 05:14:08 PM PDT 24
Peak memory 257948 kb
Host smart-5f6796e0-5ca5-47d9-9a18-3a2b1500395c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197211610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.197211610
+enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest

Test location /workspace/coverage/default/14.kmac_edn_timeout_error.3043033282
Short name T465
Test name
Test status
Simulation time 78616712 ps
CPU time 1.23 seconds
Started Jul 29 04:56:16 PM PDT 24
Finished Jul 29 04:56:17 PM PDT 24
Peak memory 218592 kb
Host smart-58928121-faf9-445c-b228-3f7783f19fa5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3043033282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.3043033282 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_mode_error.94655459
Short name T885
Test name
Test status
Simulation time 31386015 ps
CPU time 1.18 seconds
Started Jul 29 04:56:15 PM PDT 24
Finished Jul 29 04:56:17 PM PDT 24
Peak memory 222632 kb
Host smart-5ead2527-7c6a-47a5-b8af-921a4c84f63c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=94655459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.94655459 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_refresh.4154023088
Short name T917
Test name
Test status
Simulation time 9021869571 ps
CPU time 281.05 seconds
Started Jul 29 04:56:21 PM PDT 24
Finished Jul 29 05:01:02 PM PDT 24
Peak memory 303920 kb
Host smart-f4a01ed1-3451-4098-92a9-550e4c009f4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154023088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.4
154023088 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/14.kmac_error.1952715819
Short name T2
Test name
Test status
Simulation time 662468384 ps
CPU time 62.2 seconds
Started Jul 29 04:56:11 PM PDT 24
Finished Jul 29 04:57:14 PM PDT 24
Peak memory 244312 kb
Host smart-94bdaf45-cf88-428d-9259-bbc08ad314cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952715819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.1952715819 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest

Test location /workspace/coverage/default/14.kmac_key_error.3206989580
Short name T413
Test name
Test status
Simulation time 404977131 ps
CPU time 2.34 seconds
Started Jul 29 04:56:17 PM PDT 24
Finished Jul 29 04:56:20 PM PDT 24
Peak memory 226388 kb
Host smart-2837cc49-51d6-44d6-b4ca-d98446e2fd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206989580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.3206989580 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest

Test location /workspace/coverage/default/14.kmac_lc_escalation.3473901952
Short name T76
Test name
Test status
Simulation time 146826191 ps
CPU time 1.29 seconds
Started Jul 29 04:56:05 PM PDT 24
Finished Jul 29 04:56:07 PM PDT 24
Peak memory 226820 kb
Host smart-4ad54510-ddad-4323-a06c-2a8ef095d137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473901952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.3473901952 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/14.kmac_lc_escalation/latest

Test location /workspace/coverage/default/14.kmac_long_msg_and_output.3117615214
Short name T370
Test name
Test status
Simulation time 264615691067 ps
CPU time 1120.99 seconds
Started Jul 29 04:56:11 PM PDT 24
Finished Jul 29 05:14:52 PM PDT 24
Peak memory 1258376 kb
Host smart-9852dab5-3ef2-4ce9-a888-85538ae7f6b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117615214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_a
nd_output.3117615214 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/14.kmac_sideload.1257278482
Short name T452
Test name
Test status
Simulation time 58295474717 ps
CPU time 403.45 seconds
Started Jul 29 04:56:23 PM PDT 24
Finished Jul 29 05:03:06 PM PDT 24
Peak memory 524236 kb
Host smart-7ba9a8ec-f75c-4af8-8dd6-32471528eaa3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257278482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.1257278482 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest

Test location /workspace/coverage/default/14.kmac_smoke.3403588766
Short name T606
Test name
Test status
Simulation time 2952375321 ps
CPU time 53.92 seconds
Started Jul 29 04:56:17 PM PDT 24
Finished Jul 29 04:57:11 PM PDT 24
Peak memory 226920 kb
Host smart-e66bba12-5a1d-4303-8238-ee61b0591114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403588766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.3403588766 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest

Test location /workspace/coverage/default/14.kmac_stress_all.1935724035
Short name T718
Test name
Test status
Simulation time 193128151208 ps
CPU time 1532.08 seconds
Started Jul 29 04:56:11 PM PDT 24
Finished Jul 29 05:21:43 PM PDT 24
Peak memory 976496 kb
Host smart-f342b479-98a7-4b98-9171-06a09a4bc095
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1935724035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.1935724035 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac.1435025352
Short name T276
Test name
Test status
Simulation time 527048053 ps
CPU time 5.8 seconds
Started Jul 29 04:56:16 PM PDT 24
Finished Jul 29 04:56:22 PM PDT 24
Peak memory 218796 kb
Host smart-a417eff7-00b9-44ce-a521-474d50d917aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435025352 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.kmac_test_vectors_kmac.1435025352 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac_xof.504200089
Short name T563
Test name
Test status
Simulation time 388230732 ps
CPU time 6.28 seconds
Started Jul 29 04:56:08 PM PDT 24
Finished Jul 29 04:56:14 PM PDT 24
Peak memory 219660 kb
Host smart-7077665f-341f-4715-85b8-1635c98f0de2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504200089 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.kmac_test_vectors_kmac_xof.504200089 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_224.916228575
Short name T409
Test name
Test status
Simulation time 20770497047 ps
CPU time 2376.04 seconds
Started Jul 29 04:56:22 PM PDT 24
Finished Jul 29 05:35:58 PM PDT 24
Peak memory 1222432 kb
Host smart-5735c0a7-287b-4a50-8266-51bf04515364
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=916228575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.916228575 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_256.3102398222
Short name T792
Test name
Test status
Simulation time 19799015824 ps
CPU time 2107.84 seconds
Started Jul 29 04:55:57 PM PDT 24
Finished Jul 29 05:31:05 PM PDT 24
Peak memory 1144036 kb
Host smart-90d2828a-3944-4324-b286-b8518697171d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3102398222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.3102398222 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_384.3545294093
Short name T282
Test name
Test status
Simulation time 205163883690 ps
CPU time 2290.3 seconds
Started Jul 29 04:56:19 PM PDT 24
Finished Jul 29 05:34:30 PM PDT 24
Peak memory 2360052 kb
Host smart-ac07d071-c6dd-420e-8dce-819fd76161f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3545294093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.3545294093 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_512.3930694361
Short name T511
Test name
Test status
Simulation time 43437839949 ps
CPU time 1288.08 seconds
Started Jul 29 04:56:14 PM PDT 24
Finished Jul 29 05:17:42 PM PDT 24
Peak memory 698944 kb
Host smart-9638b0e2-632c-4a1b-b2a7-fb436eff9fd2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3930694361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.3930694361 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/15.kmac_alert_test.3479164098
Short name T631
Test name
Test status
Simulation time 120900945 ps
CPU time 0.81 seconds
Started Jul 29 04:56:21 PM PDT 24
Finished Jul 29 04:56:22 PM PDT 24
Peak memory 218432 kb
Host smart-1fd48631-6df4-4e9c-82bd-13ad0c6f6752
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479164098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.3479164098 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest

Test location /workspace/coverage/default/15.kmac_app.1954011563
Short name T981
Test name
Test status
Simulation time 2924291073 ps
CPU time 152.44 seconds
Started Jul 29 04:56:19 PM PDT 24
Finished Jul 29 04:58:52 PM PDT 24
Peak memory 278320 kb
Host smart-7df042fe-0b9a-492a-a30c-a9f37c7c8b5a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954011563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.1954011563 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/15.kmac_app/latest

Test location /workspace/coverage/default/15.kmac_burst_write.1347326465
Short name T714
Test name
Test status
Simulation time 79876549173 ps
CPU time 1018.48 seconds
Started Jul 29 04:56:11 PM PDT 24
Finished Jul 29 05:13:10 PM PDT 24
Peak memory 254600 kb
Host smart-1d91baa5-df7a-40a8-916c-5da63dfea37a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347326465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.134732646
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest

Test location /workspace/coverage/default/15.kmac_edn_timeout_error.2087011084
Short name T312
Test name
Test status
Simulation time 806415222 ps
CPU time 5.97 seconds
Started Jul 29 04:56:18 PM PDT 24
Finished Jul 29 04:56:24 PM PDT 24
Peak memory 223140 kb
Host smart-791981d6-f4ff-418d-a75b-92d537cf41b8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2087011084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.2087011084 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_mode_error.2827492758
Short name T864
Test name
Test status
Simulation time 134591151 ps
CPU time 1.27 seconds
Started Jul 29 04:56:29 PM PDT 24
Finished Jul 29 04:56:30 PM PDT 24
Peak memory 222332 kb
Host smart-b3c69e62-1e73-4fee-ba4a-70081bf29813
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2827492758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.2827492758 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_refresh.2767639013
Short name T715
Test name
Test status
Simulation time 6682407051 ps
CPU time 142.76 seconds
Started Jul 29 04:56:26 PM PDT 24
Finished Jul 29 04:58:49 PM PDT 24
Peak memory 322772 kb
Host smart-15771cdf-a5d5-4480-bd51-fcb56964acfa
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767639013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.2
767639013 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/15.kmac_error.773306373
Short name T910
Test name
Test status
Simulation time 37192601168 ps
CPU time 313.29 seconds
Started Jul 29 04:56:14 PM PDT 24
Finished Jul 29 05:01:27 PM PDT 24
Peak memory 460304 kb
Host smart-f0228184-2f8d-4798-836b-89de9138d1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773306373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.773306373 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_error/latest

Test location /workspace/coverage/default/15.kmac_lc_escalation.2362617453
Short name T25
Test name
Test status
Simulation time 90165395 ps
CPU time 1.37 seconds
Started Jul 29 04:56:19 PM PDT 24
Finished Jul 29 04:56:20 PM PDT 24
Peak memory 226872 kb
Host smart-ca2db233-fe34-4e85-a7bb-8c2d8ab59082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362617453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.2362617453 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/15.kmac_lc_escalation/latest

Test location /workspace/coverage/default/15.kmac_long_msg_and_output.2973409479
Short name T519
Test name
Test status
Simulation time 50681563052 ps
CPU time 2829.7 seconds
Started Jul 29 04:56:20 PM PDT 24
Finished Jul 29 05:43:30 PM PDT 24
Peak memory 2418332 kb
Host smart-d20c27dc-01f7-49c4-a9e7-9decdb4249cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973409479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_a
nd_output.2973409479 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/15.kmac_sideload.986041002
Short name T137
Test name
Test status
Simulation time 34470269420 ps
CPU time 623.54 seconds
Started Jul 29 04:56:18 PM PDT 24
Finished Jul 29 05:06:41 PM PDT 24
Peak memory 630800 kb
Host smart-986deeb6-2abf-4c5e-ab03-bc0a10daef72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986041002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.986041002 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest

Test location /workspace/coverage/default/15.kmac_smoke.1709204660
Short name T894
Test name
Test status
Simulation time 14429125142 ps
CPU time 80.63 seconds
Started Jul 29 04:56:06 PM PDT 24
Finished Jul 29 04:57:27 PM PDT 24
Peak memory 227532 kb
Host smart-a528d097-3b90-4901-8ef2-5163ca9ab9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709204660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.1709204660 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest

Test location /workspace/coverage/default/15.kmac_stress_all.3414828506
Short name T742
Test name
Test status
Simulation time 15562354834 ps
CPU time 1471.82 seconds
Started Jul 29 04:56:31 PM PDT 24
Finished Jul 29 05:21:03 PM PDT 24
Peak memory 571652 kb
Host smart-ccfd9c8e-b8aa-47d3-b054-be6a00b9bbc8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3414828506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.3414828506 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac.1405803732
Short name T759
Test name
Test status
Simulation time 289725393 ps
CPU time 6.61 seconds
Started Jul 29 04:56:24 PM PDT 24
Finished Jul 29 04:56:31 PM PDT 24
Peak memory 219668 kb
Host smart-4d13dc20-8057-4f24-ac58-253f26157346
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405803732 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.kmac_test_vectors_kmac.1405803732 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac_xof.1434940354
Short name T945
Test name
Test status
Simulation time 336295901 ps
CPU time 6.79 seconds
Started Jul 29 04:56:15 PM PDT 24
Finished Jul 29 04:56:22 PM PDT 24
Peak memory 219732 kb
Host smart-20a35d9d-6cbe-4320-ad30-6a97564fdf40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434940354 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.kmac_test_vectors_kmac_xof.1434940354 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_224.853189955
Short name T648
Test name
Test status
Simulation time 25359980141 ps
CPU time 2268.17 seconds
Started Jul 29 04:56:14 PM PDT 24
Finished Jul 29 05:34:02 PM PDT 24
Peak memory 1197244 kb
Host smart-d30f6569-c0cb-41c8-b111-a8e4d4ac2e13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=853189955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.853189955 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_256.1899487969
Short name T676
Test name
Test status
Simulation time 61231893203 ps
CPU time 2164.99 seconds
Started Jul 29 04:56:06 PM PDT 24
Finished Jul 29 05:32:11 PM PDT 24
Peak memory 1127624 kb
Host smart-33c31d04-2996-4011-968a-54792593f8db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1899487969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.1899487969 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_384.2352452695
Short name T347
Test name
Test status
Simulation time 1380073045684 ps
CPU time 2603.89 seconds
Started Jul 29 04:56:14 PM PDT 24
Finished Jul 29 05:39:44 PM PDT 24
Peak memory 2347540 kb
Host smart-26e115f5-277a-4fde-ae13-b86dd6850ff9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2352452695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.2352452695 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_512.4209012450
Short name T770
Test name
Test status
Simulation time 133740146810 ps
CPU time 1590.31 seconds
Started Jul 29 04:56:13 PM PDT 24
Finished Jul 29 05:22:44 PM PDT 24
Peak memory 1722792 kb
Host smart-6af24f9e-b807-44bf-a5db-1e4eeb45a94e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4209012450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.4209012450 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_128.3429855745
Short name T222
Test name
Test status
Simulation time 133884971920 ps
CPU time 6590.77 seconds
Started Jul 29 04:56:17 PM PDT 24
Finished Jul 29 06:46:09 PM PDT 24
Peak memory 2656852 kb
Host smart-b9965789-5159-4b9b-838d-db0c6448dc40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3429855745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.3429855745 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/16.kmac_alert_test.2460607975
Short name T803
Test name
Test status
Simulation time 34914596 ps
CPU time 0.75 seconds
Started Jul 29 04:56:04 PM PDT 24
Finished Jul 29 04:56:05 PM PDT 24
Peak memory 218404 kb
Host smart-ebf46951-10f0-44e6-b728-101cb6c3c208
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460607975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.2460607975 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest

Test location /workspace/coverage/default/16.kmac_app.2070323543
Short name T587
Test name
Test status
Simulation time 7728674170 ps
CPU time 214.98 seconds
Started Jul 29 04:56:38 PM PDT 24
Finished Jul 29 05:00:13 PM PDT 24
Peak memory 357012 kb
Host smart-f1d02d8f-0f3e-4fec-b6cc-005d9fff96aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070323543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.2070323543 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest

Test location /workspace/coverage/default/16.kmac_burst_write.773535665
Short name T338
Test name
Test status
Simulation time 1852036953 ps
CPU time 73.6 seconds
Started Jul 29 04:56:16 PM PDT 24
Finished Jul 29 04:57:30 PM PDT 24
Peak memory 224904 kb
Host smart-5664bd07-b966-432c-a005-4b07bd59c2ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773535665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.773535665
+enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_burst_write/latest

Test location /workspace/coverage/default/16.kmac_edn_timeout_error.1368467763
Short name T300
Test name
Test status
Simulation time 106030710 ps
CPU time 5.05 seconds
Started Jul 29 04:56:14 PM PDT 24
Finished Jul 29 04:56:19 PM PDT 24
Peak memory 225728 kb
Host smart-ca6023da-9305-4f7f-8ca2-855658d691d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1368467763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.1368467763 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_mode_error.634284670
Short name T747
Test name
Test status
Simulation time 101548774 ps
CPU time 1.02 seconds
Started Jul 29 04:56:28 PM PDT 24
Finished Jul 29 04:56:29 PM PDT 24
Peak memory 218332 kb
Host smart-3810060f-fecd-4743-ab02-7c10da983c1e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=634284670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.634284670 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_refresh.2769601547
Short name T607
Test name
Test status
Simulation time 36772529237 ps
CPU time 270.49 seconds
Started Jul 29 04:56:17 PM PDT 24
Finished Jul 29 05:00:47 PM PDT 24
Peak memory 403396 kb
Host smart-80ba9f68-e137-4341-b338-41be13305ccb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769601547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.2
769601547 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/16.kmac_error.131125137
Short name T619
Test name
Test status
Simulation time 10635618654 ps
CPU time 434.38 seconds
Started Jul 29 04:56:31 PM PDT 24
Finished Jul 29 05:03:46 PM PDT 24
Peak memory 384488 kb
Host smart-0f285f63-e5a9-4ea9-a5bb-5212e45fcc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131125137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.131125137 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_error/latest

Test location /workspace/coverage/default/16.kmac_key_error.967532368
Short name T97
Test name
Test status
Simulation time 2632424809 ps
CPU time 9.01 seconds
Started Jul 29 04:56:24 PM PDT 24
Finished Jul 29 04:56:33 PM PDT 24
Peak memory 226716 kb
Host smart-293ffe37-8b47-4e91-9da9-1408407825e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967532368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.967532368 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest

Test location /workspace/coverage/default/16.kmac_sideload.2263827034
Short name T782
Test name
Test status
Simulation time 14003655201 ps
CPU time 252.53 seconds
Started Jul 29 04:56:34 PM PDT 24
Finished Jul 29 05:00:46 PM PDT 24
Peak memory 407208 kb
Host smart-463b12de-68ca-46b3-9e1d-8276abbf7ad4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263827034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.2263827034 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest

Test location /workspace/coverage/default/16.kmac_smoke.1978745957
Short name T441
Test name
Test status
Simulation time 2359282387 ps
CPU time 43.17 seconds
Started Jul 29 04:56:23 PM PDT 24
Finished Jul 29 04:57:06 PM PDT 24
Peak memory 226892 kb
Host smart-5fac9745-111c-46d9-827b-5464b011ad6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978745957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.1978745957 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest

Test location /workspace/coverage/default/16.kmac_stress_all.4268104216
Short name T614
Test name
Test status
Simulation time 38117977157 ps
CPU time 706.93 seconds
Started Jul 29 04:56:41 PM PDT 24
Finished Jul 29 05:08:28 PM PDT 24
Peak memory 341672 kb
Host smart-c18140df-bc66-4a99-a745-15da0a724d81
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4268104216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.4268104216 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac.2192048643
Short name T712
Test name
Test status
Simulation time 203549850 ps
CPU time 6.26 seconds
Started Jul 29 04:56:12 PM PDT 24
Finished Jul 29 04:56:18 PM PDT 24
Peak memory 219736 kb
Host smart-d7948f31-ea0a-4b10-9e35-293a148067d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192048643 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.kmac_test_vectors_kmac.2192048643 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac_xof.1938808114
Short name T584
Test name
Test status
Simulation time 113703715 ps
CPU time 6.1 seconds
Started Jul 29 04:56:36 PM PDT 24
Finished Jul 29 04:56:42 PM PDT 24
Peak memory 218780 kb
Host smart-53508431-e221-49ca-bb0b-4af47c321991
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938808114 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.kmac_test_vectors_kmac_xof.1938808114 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_224.3684448373
Short name T208
Test name
Test status
Simulation time 116390928929 ps
CPU time 3346.57 seconds
Started Jul 29 04:56:08 PM PDT 24
Finished Jul 29 05:51:55 PM PDT 24
Peak memory 3221728 kb
Host smart-0e4a7004-c6ed-4d0f-8702-763f531b3e8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3684448373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.3684448373 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_384.4064344892
Short name T302
Test name
Test status
Simulation time 59780621664 ps
CPU time 2268.73 seconds
Started Jul 29 04:56:19 PM PDT 24
Finished Jul 29 05:34:08 PM PDT 24
Peak memory 2408844 kb
Host smart-40a7ae1a-ba39-425e-a6ca-bf1dfe74db1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4064344892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.4064344892 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_512.4132629048
Short name T140
Test name
Test status
Simulation time 44285279975 ps
CPU time 1564.31 seconds
Started Jul 29 04:56:24 PM PDT 24
Finished Jul 29 05:22:29 PM PDT 24
Peak memory 1740040 kb
Host smart-dcdb13a2-04e1-441d-95ef-c70afd999ab5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4132629048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.4132629048 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_128.736213228
Short name T224
Test name
Test status
Simulation time 157805823750 ps
CPU time 6875.93 seconds
Started Jul 29 04:56:15 PM PDT 24
Finished Jul 29 06:50:52 PM PDT 24
Peak memory 2712168 kb
Host smart-083c9e16-615d-45bf-96be-77db9e8e836e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=736213228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_128.736213228 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/17.kmac_alert_test.596469382
Short name T335
Test name
Test status
Simulation time 40628160 ps
CPU time 0.82 seconds
Started Jul 29 04:56:29 PM PDT 24
Finished Jul 29 04:56:30 PM PDT 24
Peak memory 218376 kb
Host smart-9c4529a3-a7b7-43cd-b7a9-21af77b6c773
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596469382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.596469382 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/17.kmac_alert_test/latest

Test location /workspace/coverage/default/17.kmac_app.229948996
Short name T733
Test name
Test status
Simulation time 18875505991 ps
CPU time 346.95 seconds
Started Jul 29 04:56:23 PM PDT 24
Finished Jul 29 05:02:10 PM PDT 24
Peak memory 441044 kb
Host smart-ace987dd-65c2-4112-a0d3-6de277eb5be6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229948996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.229948996 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/17.kmac_app/latest

Test location /workspace/coverage/default/17.kmac_burst_write.1994904260
Short name T684
Test name
Test status
Simulation time 10799659699 ps
CPU time 629.13 seconds
Started Jul 29 04:56:12 PM PDT 24
Finished Jul 29 05:06:41 PM PDT 24
Peak memory 238040 kb
Host smart-cdc0ee46-8caf-44f0-98fd-05fcf58de324
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994904260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.199490426
0 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_burst_write/latest

Test location /workspace/coverage/default/17.kmac_edn_timeout_error.3077636768
Short name T873
Test name
Test status
Simulation time 3184472802 ps
CPU time 21.5 seconds
Started Jul 29 04:56:32 PM PDT 24
Finished Jul 29 04:56:53 PM PDT 24
Peak memory 222176 kb
Host smart-26c70bf3-250d-4bd3-8a36-41060a0af3b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3077636768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.3077636768 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_mode_error.1910934650
Short name T70
Test name
Test status
Simulation time 76521576 ps
CPU time 1.01 seconds
Started Jul 29 04:56:33 PM PDT 24
Finished Jul 29 04:56:35 PM PDT 24
Peak memory 218584 kb
Host smart-07aa930a-2ed6-40d5-9df2-385659d43a30
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1910934650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.1910934650 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_refresh.852688816
Short name T528
Test name
Test status
Simulation time 13944058609 ps
CPU time 402.58 seconds
Started Jul 29 04:56:19 PM PDT 24
Finished Jul 29 05:03:02 PM PDT 24
Peak memory 451696 kb
Host smart-15e27e79-3fcf-41fc-afa1-12452bffa02f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852688816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.85
2688816 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/17.kmac_error.1698153391
Short name T650
Test name
Test status
Simulation time 6453989999 ps
CPU time 115.06 seconds
Started Jul 29 04:56:30 PM PDT 24
Finished Jul 29 04:58:25 PM PDT 24
Peak memory 272880 kb
Host smart-3b6198ef-e71e-4cbc-a978-0989fc430ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698153391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.1698153391 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest

Test location /workspace/coverage/default/17.kmac_key_error.3976339834
Short name T595
Test name
Test status
Simulation time 1456219717 ps
CPU time 11.19 seconds
Started Jul 29 04:56:21 PM PDT 24
Finished Jul 29 04:56:33 PM PDT 24
Peak memory 226656 kb
Host smart-693f0015-1409-424e-a40f-df2d85a0486a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976339834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.3976339834 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_key_error/latest

Test location /workspace/coverage/default/17.kmac_long_msg_and_output.3621010823
Short name T206
Test name
Test status
Simulation time 11754913814 ps
CPU time 191.66 seconds
Started Jul 29 04:56:20 PM PDT 24
Finished Jul 29 04:59:32 PM PDT 24
Peak memory 310688 kb
Host smart-93a9c406-931c-44a2-846f-8a06897d1a7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621010823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_a
nd_output.3621010823 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/17.kmac_sideload.3411365988
Short name T565
Test name
Test status
Simulation time 662992934 ps
CPU time 16.17 seconds
Started Jul 29 04:56:22 PM PDT 24
Finished Jul 29 04:56:38 PM PDT 24
Peak memory 239040 kb
Host smart-f5acc728-f629-445c-b297-b88703bcf49b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411365988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.3411365988 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest

Test location /workspace/coverage/default/17.kmac_smoke.4217213828
Short name T779
Test name
Test status
Simulation time 241927967 ps
CPU time 3.84 seconds
Started Jul 29 04:56:11 PM PDT 24
Finished Jul 29 04:56:15 PM PDT 24
Peak memory 222644 kb
Host smart-2396133d-d639-4262-8929-8a2819f4fb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217213828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.4217213828 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_smoke/latest

Test location /workspace/coverage/default/17.kmac_stress_all.2081958487
Short name T569
Test name
Test status
Simulation time 4301742171 ps
CPU time 124.13 seconds
Started Jul 29 04:56:13 PM PDT 24
Finished Jul 29 04:58:18 PM PDT 24
Peak memory 276164 kb
Host smart-3b8480ac-b06a-4408-9923-616fe59f27b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2081958487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.2081958487 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac.3775590482
Short name T728
Test name
Test status
Simulation time 109052303 ps
CPU time 6.18 seconds
Started Jul 29 04:56:15 PM PDT 24
Finished Jul 29 04:56:22 PM PDT 24
Peak memory 219680 kb
Host smart-e61edced-078d-4903-97e4-8e2fd20058f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775590482 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.kmac_test_vectors_kmac.3775590482 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac_xof.3272179470
Short name T360
Test name
Test status
Simulation time 609215825 ps
CPU time 5.47 seconds
Started Jul 29 04:56:32 PM PDT 24
Finished Jul 29 04:56:38 PM PDT 24
Peak memory 218836 kb
Host smart-b43e96a8-c8fc-43f3-8134-7009fedcd9a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272179470 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.kmac_test_vectors_kmac_xof.3272179470 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_224.84428921
Short name T632
Test name
Test status
Simulation time 714706328111 ps
CPU time 3338.08 seconds
Started Jul 29 04:56:17 PM PDT 24
Finished Jul 29 05:51:55 PM PDT 24
Peak memory 3174284 kb
Host smart-ce234caf-742e-42f8-8488-9a4d77e3f7fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=84428921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.84428921 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_256.3228715963
Short name T273
Test name
Test status
Simulation time 37649035894 ps
CPU time 2224.15 seconds
Started Jul 29 04:56:30 PM PDT 24
Finished Jul 29 05:33:34 PM PDT 24
Peak memory 1113784 kb
Host smart-e1926491-db4a-430e-847e-9f43fec1e413
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3228715963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.3228715963 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_384.1269317374
Short name T869
Test name
Test status
Simulation time 69134361476 ps
CPU time 1498.57 seconds
Started Jul 29 04:56:25 PM PDT 24
Finished Jul 29 05:21:24 PM PDT 24
Peak memory 938764 kb
Host smart-08c2fbd9-8d42-4d6e-bc46-369d5cc7b2f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1269317374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.1269317374 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_512.2740186214
Short name T616
Test name
Test status
Simulation time 46392186306 ps
CPU time 1267.49 seconds
Started Jul 29 04:56:28 PM PDT 24
Finished Jul 29 05:17:36 PM PDT 24
Peak memory 697620 kb
Host smart-8b3e7614-88fc-4b61-8513-e49b8c151bab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2740186214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.2740186214 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_128.1335048572
Short name T854
Test name
Test status
Simulation time 262739160868 ps
CPU time 6411.63 seconds
Started Jul 29 04:56:37 PM PDT 24
Finished Jul 29 06:43:30 PM PDT 24
Peak memory 2693824 kb
Host smart-9e3a51fa-1e3d-4249-afb4-87dc54b569e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1335048572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.1335048572 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/18.kmac_alert_test.1309295217
Short name T205
Test name
Test status
Simulation time 73008235 ps
CPU time 0.85 seconds
Started Jul 29 04:56:36 PM PDT 24
Finished Jul 29 04:56:37 PM PDT 24
Peak memory 218412 kb
Host smart-2c1ee858-a626-4e7b-a4a3-daad9e32e39f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309295217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.1309295217 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_alert_test/latest

Test location /workspace/coverage/default/18.kmac_app.191316151
Short name T878
Test name
Test status
Simulation time 9004575199 ps
CPU time 291.36 seconds
Started Jul 29 04:56:41 PM PDT 24
Finished Jul 29 05:01:33 PM PDT 24
Peak memory 418052 kb
Host smart-d0c04f85-762a-4aa4-b435-6c0031a4e5b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191316151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.191316151 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest

Test location /workspace/coverage/default/18.kmac_burst_write.3310868588
Short name T252
Test name
Test status
Simulation time 4211232305 ps
CPU time 118.52 seconds
Started Jul 29 04:56:24 PM PDT 24
Finished Jul 29 04:58:23 PM PDT 24
Peak memory 226928 kb
Host smart-fb2f2c8f-da49-49ba-b40b-ffafe021c1cf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310868588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.331086858
8 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest

Test location /workspace/coverage/default/18.kmac_edn_timeout_error.4108470470
Short name T270
Test name
Test status
Simulation time 3053608091 ps
CPU time 53.78 seconds
Started Jul 29 04:56:42 PM PDT 24
Finished Jul 29 04:57:36 PM PDT 24
Peak memory 243080 kb
Host smart-69b6e5c4-9a7d-404c-ada4-d6c1f4bce99f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4108470470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.4108470470 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_mode_error.4068614714
Short name T665
Test name
Test status
Simulation time 45019403 ps
CPU time 1.2 seconds
Started Jul 29 04:56:29 PM PDT 24
Finished Jul 29 04:56:30 PM PDT 24
Peak memory 222044 kb
Host smart-df211693-e0eb-40fd-aaa1-50bef2443115
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4068614714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.4068614714 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_refresh.1500244131
Short name T941
Test name
Test status
Simulation time 10479154625 ps
CPU time 210.79 seconds
Started Jul 29 04:56:23 PM PDT 24
Finished Jul 29 04:59:54 PM PDT 24
Peak memory 375188 kb
Host smart-bde54a1b-1642-46c1-b53c-4610e03f5b5f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500244131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.1
500244131 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/18.kmac_error.1890603064
Short name T467
Test name
Test status
Simulation time 17465549493 ps
CPU time 312.04 seconds
Started Jul 29 04:56:23 PM PDT 24
Finished Jul 29 05:01:35 PM PDT 24
Peak memory 457296 kb
Host smart-d4bf75dc-fe35-4565-a15d-e50ec289f7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890603064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.1890603064 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest

Test location /workspace/coverage/default/18.kmac_key_error.4198087686
Short name T100
Test name
Test status
Simulation time 722857854 ps
CPU time 5.01 seconds
Started Jul 29 04:56:28 PM PDT 24
Finished Jul 29 04:56:33 PM PDT 24
Peak memory 226556 kb
Host smart-76ed1426-2e9d-4f3b-877b-73488cbc9b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198087686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.4198087686 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_key_error/latest

Test location /workspace/coverage/default/18.kmac_lc_escalation.1401210743
Short name T13
Test name
Test status
Simulation time 161107695 ps
CPU time 1.86 seconds
Started Jul 29 04:56:31 PM PDT 24
Finished Jul 29 04:56:33 PM PDT 24
Peak memory 226804 kb
Host smart-23fc9fde-e6d0-49aa-b49e-78ebd19efea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401210743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.1401210743 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/18.kmac_lc_escalation/latest

Test location /workspace/coverage/default/18.kmac_long_msg_and_output.158093638
Short name T210
Test name
Test status
Simulation time 8615630572 ps
CPU time 171.02 seconds
Started Jul 29 04:56:32 PM PDT 24
Finished Jul 29 04:59:23 PM PDT 24
Peak memory 311196 kb
Host smart-1d482eb3-dc29-48eb-a7eb-df3352066c78
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158093638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_an
d_output.158093638 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/18.kmac_sideload.74239946
Short name T298
Test name
Test status
Simulation time 10618429963 ps
CPU time 74.43 seconds
Started Jul 29 04:56:32 PM PDT 24
Finished Jul 29 04:57:47 PM PDT 24
Peak memory 283552 kb
Host smart-37e6c0a9-8f15-4334-94f5-0eb07fc8435b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74239946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.74239946 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest

Test location /workspace/coverage/default/18.kmac_smoke.2934708050
Short name T385
Test name
Test status
Simulation time 3367350901 ps
CPU time 65.98 seconds
Started Jul 29 04:56:16 PM PDT 24
Finished Jul 29 04:57:22 PM PDT 24
Peak memory 226920 kb
Host smart-2c1947ab-fc1b-40ee-9df1-617206dec0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934708050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.2934708050 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac.155092168
Short name T916
Test name
Test status
Simulation time 216952877 ps
CPU time 5.58 seconds
Started Jul 29 04:56:21 PM PDT 24
Finished Jul 29 04:56:27 PM PDT 24
Peak memory 219656 kb
Host smart-caf18bf4-cda6-482e-8f0e-558e96e62797
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155092168 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.kmac_test_vectors_kmac.155092168 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac_xof.2775258788
Short name T588
Test name
Test status
Simulation time 1240831278 ps
CPU time 6.94 seconds
Started Jul 29 04:56:24 PM PDT 24
Finished Jul 29 04:56:31 PM PDT 24
Peak memory 220020 kb
Host smart-c2f83179-aada-48e7-a98f-9ae2425ceb61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775258788 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.kmac_test_vectors_kmac_xof.2775258788 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_384.3605308949
Short name T727
Test name
Test status
Simulation time 100509909279 ps
CPU time 2570.9 seconds
Started Jul 29 04:56:20 PM PDT 24
Finished Jul 29 05:39:11 PM PDT 24
Peak memory 2418316 kb
Host smart-5db2899d-bfbc-432a-862a-cc92a4bfb484
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3605308949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.3605308949 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_512.2486309164
Short name T772
Test name
Test status
Simulation time 10602649694 ps
CPU time 1186.38 seconds
Started Jul 29 04:56:23 PM PDT 24
Finished Jul 29 05:16:10 PM PDT 24
Peak memory 701884 kb
Host smart-96451d2b-fddb-4cfc-a000-a2601bdcebea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2486309164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.2486309164 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_256.1902740206
Short name T515
Test name
Test status
Simulation time 55046318298 ps
CPU time 5147.02 seconds
Started Jul 29 04:56:22 PM PDT 24
Finished Jul 29 06:22:09 PM PDT 24
Peak memory 2215664 kb
Host smart-4a74631c-9d49-474a-90e0-6c28af9ddaa2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1902740206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.1902740206 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/19.kmac_alert_test.1265172240
Short name T429
Test name
Test status
Simulation time 99330431 ps
CPU time 0.79 seconds
Started Jul 29 04:56:38 PM PDT 24
Finished Jul 29 04:56:39 PM PDT 24
Peak memory 218344 kb
Host smart-b28bc94b-9044-400e-932a-23b4c05c0c38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265172240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.1265172240 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_alert_test/latest

Test location /workspace/coverage/default/19.kmac_app.2402974969
Short name T536
Test name
Test status
Simulation time 15169671902 ps
CPU time 174.5 seconds
Started Jul 29 04:56:31 PM PDT 24
Finished Jul 29 04:59:26 PM PDT 24
Peak memory 277704 kb
Host smart-b933c6e1-27ac-4501-8aca-d61fd0d55190
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402974969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.2402974969 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/19.kmac_app/latest

Test location /workspace/coverage/default/19.kmac_burst_write.1577788160
Short name T791
Test name
Test status
Simulation time 4958100419 ps
CPU time 487.68 seconds
Started Jul 29 04:56:22 PM PDT 24
Finished Jul 29 05:04:30 PM PDT 24
Peak memory 243284 kb
Host smart-af4d4308-8134-4f22-b77c-fb1b232359ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577788160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.157778816
0 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_burst_write/latest

Test location /workspace/coverage/default/19.kmac_edn_timeout_error.5698186
Short name T886
Test name
Test status
Simulation time 36153963 ps
CPU time 1.12 seconds
Started Jul 29 04:56:42 PM PDT 24
Finished Jul 29 04:56:43 PM PDT 24
Peak memory 218548 kb
Host smart-ee3a4092-9532-4081-a732-5569309d3a78
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=5698186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.5698186 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/19.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_mode_error.2637427123
Short name T797
Test name
Test status
Simulation time 13587968 ps
CPU time 0.8 seconds
Started Jul 29 04:56:28 PM PDT 24
Finished Jul 29 04:56:29 PM PDT 24
Peak memory 220360 kb
Host smart-005795cb-884e-4c32-900b-07e21e0e6ece
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2637427123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.2637427123 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_refresh.531910695
Short name T495
Test name
Test status
Simulation time 224232776 ps
CPU time 6.34 seconds
Started Jul 29 04:56:25 PM PDT 24
Finished Jul 29 04:56:31 PM PDT 24
Peak memory 238472 kb
Host smart-133b3e5b-5b8a-49cb-a25f-62d409f1af0f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531910695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.53
1910695 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/19.kmac_error.578731118
Short name T319
Test name
Test status
Simulation time 3509681132 ps
CPU time 28.78 seconds
Started Jul 29 04:56:39 PM PDT 24
Finished Jul 29 04:57:08 PM PDT 24
Peak memory 254516 kb
Host smart-77e0e0c1-4f7c-4ab5-92bd-b75b1d9bd4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578731118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.578731118 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_error/latest

Test location /workspace/coverage/default/19.kmac_key_error.1250084955
Short name T251
Test name
Test status
Simulation time 1829501236 ps
CPU time 3.93 seconds
Started Jul 29 04:56:23 PM PDT 24
Finished Jul 29 04:56:27 PM PDT 24
Peak memory 226524 kb
Host smart-398c2690-df63-4b1b-8571-87b92117777d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250084955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.1250084955 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest

Test location /workspace/coverage/default/19.kmac_lc_escalation.2722154261
Short name T106
Test name
Test status
Simulation time 41113571 ps
CPU time 1.26 seconds
Started Jul 29 04:56:21 PM PDT 24
Finished Jul 29 04:56:23 PM PDT 24
Peak memory 226728 kb
Host smart-2c939b6d-dacf-4d81-910b-07bfdb59ad07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722154261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.2722154261 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/19.kmac_lc_escalation/latest

Test location /workspace/coverage/default/19.kmac_long_msg_and_output.4183377984
Short name T265
Test name
Test status
Simulation time 56100452673 ps
CPU time 2316.73 seconds
Started Jul 29 04:56:21 PM PDT 24
Finished Jul 29 05:34:58 PM PDT 24
Peak memory 2212516 kb
Host smart-269dc961-b396-4be9-a7ed-c533ea177364
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183377984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a
nd_output.4183377984 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/19.kmac_sideload.2786426603
Short name T768
Test name
Test status
Simulation time 4548061188 ps
CPU time 24.51 seconds
Started Jul 29 04:56:28 PM PDT 24
Finished Jul 29 04:56:53 PM PDT 24
Peak memory 226944 kb
Host smart-2bf32a57-da54-4bef-9926-436abd244575
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786426603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.2786426603 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest

Test location /workspace/coverage/default/19.kmac_smoke.109348842
Short name T433
Test name
Test status
Simulation time 13155785345 ps
CPU time 56.29 seconds
Started Jul 29 04:56:35 PM PDT 24
Finished Jul 29 04:57:32 PM PDT 24
Peak memory 226952 kb
Host smart-bebe627d-a1c1-43ec-921f-fff132d4bad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109348842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.109348842 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest

Test location /workspace/coverage/default/19.kmac_stress_all.311252925
Short name T825
Test name
Test status
Simulation time 10521823500 ps
CPU time 37.14 seconds
Started Jul 29 04:56:25 PM PDT 24
Finished Jul 29 04:57:02 PM PDT 24
Peak memory 249728 kb
Host smart-481498dc-97bf-4e8f-81ef-b901ec29de84
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=311252925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.311252925 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac.2349565800
Short name T544
Test name
Test status
Simulation time 583954266 ps
CPU time 6.8 seconds
Started Jul 29 04:56:27 PM PDT 24
Finished Jul 29 04:56:33 PM PDT 24
Peak memory 219692 kb
Host smart-30ebcfba-785f-4d91-b93c-a0e62cf40c96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349565800 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.kmac_test_vectors_kmac.2349565800 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac_xof.2409431616
Short name T635
Test name
Test status
Simulation time 1738448762 ps
CPU time 6.3 seconds
Started Jul 29 04:56:31 PM PDT 24
Finished Jul 29 04:56:38 PM PDT 24
Peak memory 219720 kb
Host smart-2660df05-2d48-42d8-9f89-41a067964a45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409431616 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.kmac_test_vectors_kmac_xof.2409431616 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_224.4234367914
Short name T914
Test name
Test status
Simulation time 65760369049 ps
CPU time 3307.68 seconds
Started Jul 29 04:56:36 PM PDT 24
Finished Jul 29 05:51:44 PM PDT 24
Peak memory 3211312 kb
Host smart-0ec2b167-e26f-439d-96f4-e53837a71326
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4234367914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.4234367914 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_256.2439225047
Short name T972
Test name
Test status
Simulation time 83851589011 ps
CPU time 2227.25 seconds
Started Jul 29 04:56:29 PM PDT 24
Finished Jul 29 05:33:37 PM PDT 24
Peak memory 1143160 kb
Host smart-c23f2c9d-8e81-4157-a376-5cf2b22b09bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2439225047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.2439225047 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_384.3178301534
Short name T432
Test name
Test status
Simulation time 798278939080 ps
CPU time 2462.41 seconds
Started Jul 29 04:56:36 PM PDT 24
Finished Jul 29 05:37:39 PM PDT 24
Peak memory 2399012 kb
Host smart-32d7325a-a5ef-42f4-ac17-f17b50f9a68a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3178301534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.3178301534 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_512.3889599855
Short name T592
Test name
Test status
Simulation time 14588294886 ps
CPU time 1153.59 seconds
Started Jul 29 04:56:34 PM PDT 24
Finished Jul 29 05:15:48 PM PDT 24
Peak memory 703136 kb
Host smart-58166591-22d5-4ed2-a761-dd34a1e9d6b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3889599855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.3889599855 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/2.kmac_alert_test.1065670214
Short name T350
Test name
Test status
Simulation time 26836714 ps
CPU time 0.8 seconds
Started Jul 29 04:55:59 PM PDT 24
Finished Jul 29 04:56:00 PM PDT 24
Peak memory 218408 kb
Host smart-4b7f5d3c-26a9-4a9a-8b0d-6fda55b9ab79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065670214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.1065670214 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_alert_test/latest

Test location /workspace/coverage/default/2.kmac_app.731340869
Short name T234
Test name
Test status
Simulation time 23396458142 ps
CPU time 414.02 seconds
Started Jul 29 04:55:44 PM PDT 24
Finished Jul 29 05:02:38 PM PDT 24
Peak memory 521228 kb
Host smart-d6ab9c6b-495d-4209-9afe-bbb750615ab2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731340869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.731340869 +enable_masking=1
+sw_key_masked=0
Directory /workspace/2.kmac_app/latest

Test location /workspace/coverage/default/2.kmac_app_with_partial_data.2812173529
Short name T272
Test name
Test status
Simulation time 64130827700 ps
CPU time 367.59 seconds
Started Jul 29 04:55:50 PM PDT 24
Finished Jul 29 05:01:58 PM PDT 24
Peak memory 507424 kb
Host smart-c2f8c520-2117-4840-9f81-d4c19e36d9bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812173529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_par
tial_data.2812173529 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/2.kmac_burst_write.2224440423
Short name T802
Test name
Test status
Simulation time 5619189633 ps
CPU time 261.66 seconds
Started Jul 29 04:55:39 PM PDT 24
Finished Jul 29 05:00:01 PM PDT 24
Peak memory 241852 kb
Host smart-7482a5cf-8bbd-4270-be6f-fd17f89d86ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224440423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.2224440423
+enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest

Test location /workspace/coverage/default/2.kmac_edn_timeout_error.1579999686
Short name T233
Test name
Test status
Simulation time 1297387579 ps
CPU time 24.9 seconds
Started Jul 29 04:55:40 PM PDT 24
Finished Jul 29 04:56:05 PM PDT 24
Peak memory 224872 kb
Host smart-6d32d8d8-65e0-4ce9-a379-591c7afbf41a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1579999686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.1579999686 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_mode_error.168650263
Short name T438
Test name
Test status
Simulation time 30258154 ps
CPU time 1 seconds
Started Jul 29 04:55:49 PM PDT 24
Finished Jul 29 04:55:50 PM PDT 24
Peak memory 221688 kb
Host smart-2c62ea58-fa29-4b19-aec2-9df1f581600b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=168650263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.168650263 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_refresh.2355487406
Short name T517
Test name
Test status
Simulation time 19494393245 ps
CPU time 225.25 seconds
Started Jul 29 04:55:45 PM PDT 24
Finished Jul 29 04:59:31 PM PDT 24
Peak memory 385188 kb
Host smart-33932f50-43ad-47d9-9f62-6a896c9a2c5e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355487406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.23
55487406 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/2.kmac_error.3718934156
Short name T966
Test name
Test status
Simulation time 5750088740 ps
CPU time 259.39 seconds
Started Jul 29 04:55:30 PM PDT 24
Finished Jul 29 04:59:50 PM PDT 24
Peak memory 316800 kb
Host smart-315a987f-5bc1-4cbd-840e-741283896830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718934156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.3718934156 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_error/latest

Test location /workspace/coverage/default/2.kmac_key_error.2435594416
Short name T842
Test name
Test status
Simulation time 858266241 ps
CPU time 8.37 seconds
Started Jul 29 04:55:36 PM PDT 24
Finished Jul 29 04:55:45 PM PDT 24
Peak memory 226596 kb
Host smart-94b2b0da-f486-48eb-8db6-2e209730c447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435594416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.2435594416 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest

Test location /workspace/coverage/default/2.kmac_lc_escalation.1155056995
Short name T686
Test name
Test status
Simulation time 59587119 ps
CPU time 1.26 seconds
Started Jul 29 04:55:46 PM PDT 24
Finished Jul 29 04:55:48 PM PDT 24
Peak memory 226800 kb
Host smart-3a779a0a-c8c9-48c4-b6b0-274e56527348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155056995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.1155056995 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/2.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_long_msg_and_output.4184290127
Short name T138
Test name
Test status
Simulation time 7546989342 ps
CPU time 337.04 seconds
Started Jul 29 04:55:49 PM PDT 24
Finished Jul 29 05:01:26 PM PDT 24
Peak memory 563796 kb
Host smart-ebd794fe-a019-4e58-968d-1f38d00f564a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184290127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_an
d_output.4184290127 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/2.kmac_mubi.1255853336
Short name T751
Test name
Test status
Simulation time 1267905609 ps
CPU time 81.14 seconds
Started Jul 29 04:56:12 PM PDT 24
Finished Jul 29 04:57:33 PM PDT 24
Peak memory 246332 kb
Host smart-6b1d9be4-600e-410c-b685-c3b32c849eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255853336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.1255853336 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mubi/latest

Test location /workspace/coverage/default/2.kmac_sec_cm.14359868
Short name T27
Test name
Test status
Simulation time 2213901761 ps
CPU time 37.7 seconds
Started Jul 29 04:55:43 PM PDT 24
Finished Jul 29 04:56:21 PM PDT 24
Peak memory 256300 kb
Host smart-5b6637f5-ea99-4209-a3b6-8ff204dfad16
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14359868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.14359868 +enable_masking=1
+sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest

Test location /workspace/coverage/default/2.kmac_sideload.1875545920
Short name T868
Test name
Test status
Simulation time 22490046372 ps
CPU time 114.78 seconds
Started Jul 29 04:55:38 PM PDT 24
Finished Jul 29 04:57:33 PM PDT 24
Peak memory 266660 kb
Host smart-6da960b7-1143-4592-afaf-d3b146c9faa6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875545920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.1875545920 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest

Test location /workspace/coverage/default/2.kmac_smoke.2515290724
Short name T478
Test name
Test status
Simulation time 1301685850 ps
CPU time 31.88 seconds
Started Jul 29 04:55:40 PM PDT 24
Finished Jul 29 04:56:12 PM PDT 24
Peak memory 226848 kb
Host smart-db0c35ff-d675-414f-9310-4922410e350d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515290724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.2515290724 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest

Test location /workspace/coverage/default/2.kmac_stress_all.2128650866
Short name T796
Test name
Test status
Simulation time 83183373573 ps
CPU time 1376.5 seconds
Started Jul 29 04:55:48 PM PDT 24
Finished Jul 29 05:18:50 PM PDT 24
Peak memory 1153912 kb
Host smart-855e6012-c43d-45ab-9500-a2e30cc03f77
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2128650866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.2128650866 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.280617473
Short name T139
Test name
Test status
Simulation time 281229632 ps
CPU time 5.87 seconds
Started Jul 29 04:55:40 PM PDT 24
Finished Jul 29 04:55:46 PM PDT 24
Peak memory 219684 kb
Host smart-e75ef05b-32c0-4b8a-a9bf-0a5db746d557
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280617473 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.kmac_test_vectors_kmac.280617473 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.822379550
Short name T491
Test name
Test status
Simulation time 279355551 ps
CPU time 6.43 seconds
Started Jul 29 04:55:29 PM PDT 24
Finished Jul 29 04:55:36 PM PDT 24
Peak memory 219660 kb
Host smart-3ae7110c-ed53-4159-9cac-3db5a8717fa3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822379550 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.kmac_test_vectors_kmac_xof.822379550 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.3064118779
Short name T585
Test name
Test status
Simulation time 65301773603 ps
CPU time 3310.99 seconds
Started Jul 29 04:55:51 PM PDT 24
Finished Jul 29 05:51:03 PM PDT 24
Peak memory 3215872 kb
Host smart-08866ebd-d7fd-4b35-9475-7e9661f1f884
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3064118779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.3064118779 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.271770936
Short name T680
Test name
Test status
Simulation time 234439058681 ps
CPU time 3216.06 seconds
Started Jul 29 04:55:55 PM PDT 24
Finished Jul 29 05:49:32 PM PDT 24
Peak memory 3012828 kb
Host smart-ac769184-7b43-4f70-b183-b71cc79496c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=271770936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.271770936 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_384.3628894647
Short name T610
Test name
Test status
Simulation time 31672848821 ps
CPU time 1822.04 seconds
Started Jul 29 04:55:49 PM PDT 24
Finished Jul 29 05:26:12 PM PDT 24
Peak memory 947472 kb
Host smart-2b0d70d0-be70-4bc3-a199-a2957b5fb16d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3628894647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.3628894647 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.2132704400
Short name T30
Test name
Test status
Simulation time 10547831268 ps
CPU time 1304.89 seconds
Started Jul 29 04:55:46 PM PDT 24
Finished Jul 29 05:17:34 PM PDT 24
Peak memory 713928 kb
Host smart-bf19d631-b805-433f-bb99-c2a1a6c4850c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2132704400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.2132704400 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.2616148480
Short name T980
Test name
Test status
Simulation time 73421474156 ps
CPU time 5466.15 seconds
Started Jul 29 04:55:52 PM PDT 24
Finished Jul 29 06:26:59 PM PDT 24
Peak memory 2226408 kb
Host smart-e4f0908a-c46f-47f0-a20b-faba597b93ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2616148480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.2616148480 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/20.kmac_alert_test.1785202350
Short name T867
Test name
Test status
Simulation time 13409066 ps
CPU time 0.82 seconds
Started Jul 29 04:56:30 PM PDT 24
Finished Jul 29 04:56:31 PM PDT 24
Peak memory 218400 kb
Host smart-9feeb8fb-8cc3-4d0a-8016-30669efce2ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785202350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.1785202350 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest

Test location /workspace/coverage/default/20.kmac_app.638553218
Short name T935
Test name
Test status
Simulation time 20365198952 ps
CPU time 349.93 seconds
Started Jul 29 04:56:31 PM PDT 24
Finished Jul 29 05:02:21 PM PDT 24
Peak memory 314968 kb
Host smart-ca990c4e-6cff-4deb-a958-e057b91a0701
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638553218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.638553218 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest

Test location /workspace/coverage/default/20.kmac_burst_write.323571005
Short name T713
Test name
Test status
Simulation time 49834247220 ps
CPU time 1309.1 seconds
Started Jul 29 04:56:30 PM PDT 24
Finished Jul 29 05:18:20 PM PDT 24
Peak memory 245024 kb
Host smart-5526d799-3129-49f4-a5ba-1e3381cdd64f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323571005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.323571005
+enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_burst_write/latest

Test location /workspace/coverage/default/20.kmac_entropy_refresh.390103412
Short name T451
Test name
Test status
Simulation time 3690986478 ps
CPU time 73.08 seconds
Started Jul 29 04:56:22 PM PDT 24
Finished Jul 29 04:57:35 PM PDT 24
Peak memory 269160 kb
Host smart-53488dd7-5c87-4dc4-8eec-4357f86d94ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390103412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.39
0103412 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/20.kmac_error.2936239004
Short name T440
Test name
Test status
Simulation time 32275521283 ps
CPU time 282.24 seconds
Started Jul 29 04:56:29 PM PDT 24
Finished Jul 29 05:01:11 PM PDT 24
Peak memory 456796 kb
Host smart-c698a096-a097-4e5a-ba27-16edae9cc264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936239004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.2936239004 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_error/latest

Test location /workspace/coverage/default/20.kmac_key_error.400171852
Short name T774
Test name
Test status
Simulation time 2064610987 ps
CPU time 7.77 seconds
Started Jul 29 04:56:35 PM PDT 24
Finished Jul 29 04:56:43 PM PDT 24
Peak memory 226516 kb
Host smart-fbbe7506-7db1-49cf-8e32-5a35f0e91e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400171852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.400171852 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest

Test location /workspace/coverage/default/20.kmac_lc_escalation.222026334
Short name T613
Test name
Test status
Simulation time 50293712 ps
CPU time 1.33 seconds
Started Jul 29 04:56:29 PM PDT 24
Finished Jul 29 04:56:31 PM PDT 24
Peak memory 226708 kb
Host smart-f9803607-5abf-419d-baaa-1e17ab9c469b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222026334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.222026334 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/20.kmac_lc_escalation/latest

Test location /workspace/coverage/default/20.kmac_sideload.2100056635
Short name T524
Test name
Test status
Simulation time 1741327411 ps
CPU time 38.39 seconds
Started Jul 29 04:56:27 PM PDT 24
Finished Jul 29 04:57:05 PM PDT 24
Peak memory 235752 kb
Host smart-21d4665d-60fb-4159-bbac-c2cd43f046e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100056635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.2100056635 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest

Test location /workspace/coverage/default/20.kmac_smoke.3351806872
Short name T352
Test name
Test status
Simulation time 297476320 ps
CPU time 9.75 seconds
Started Jul 29 04:56:26 PM PDT 24
Finished Jul 29 04:56:36 PM PDT 24
Peak memory 226856 kb
Host smart-1e4aa253-6ef1-4f9a-8b2b-3a4e49ade469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351806872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.3351806872 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest

Test location /workspace/coverage/default/20.kmac_stress_all.423820164
Short name T800
Test name
Test status
Simulation time 262675505 ps
CPU time 6.11 seconds
Started Jul 29 04:56:38 PM PDT 24
Finished Jul 29 04:56:44 PM PDT 24
Peak memory 219672 kb
Host smart-1501648f-d2c5-487b-9957-1eaab1aef83f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=423820164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.423820164 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac.399263185
Short name T225
Test name
Test status
Simulation time 1961172097 ps
CPU time 6.11 seconds
Started Jul 29 04:56:29 PM PDT 24
Finished Jul 29 04:56:36 PM PDT 24
Peak memory 218776 kb
Host smart-8760f3b0-63bd-4ad2-b7af-42dc91e4c560
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399263185 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.kmac_test_vectors_kmac.399263185 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac_xof.3971856679
Short name T230
Test name
Test status
Simulation time 971544391 ps
CPU time 6.5 seconds
Started Jul 29 04:56:20 PM PDT 24
Finished Jul 29 04:56:27 PM PDT 24
Peak memory 219720 kb
Host smart-f4010b9a-bd89-4d8e-8d9b-0a488b434009
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971856679 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.kmac_test_vectors_kmac_xof.3971856679 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_256.1848196096
Short name T775
Test name
Test status
Simulation time 267961369037 ps
CPU time 3050.91 seconds
Started Jul 29 04:56:35 PM PDT 24
Finished Jul 29 05:47:27 PM PDT 24
Peak memory 3059068 kb
Host smart-a2b1cb9f-9ba6-46ed-8e3a-1baa0a921ec7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1848196096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.1848196096 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_384.3690027216
Short name T965
Test name
Test status
Simulation time 63776413491 ps
CPU time 1735.11 seconds
Started Jul 29 04:56:34 PM PDT 24
Finished Jul 29 05:25:30 PM PDT 24
Peak memory 910236 kb
Host smart-f085d0d0-924f-4165-a486-c261d9ccd780
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3690027216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.3690027216 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_512.1701222710
Short name T924
Test name
Test status
Simulation time 33108290173 ps
CPU time 1291.53 seconds
Started Jul 29 04:56:40 PM PDT 24
Finished Jul 29 05:18:11 PM PDT 24
Peak memory 702416 kb
Host smart-fca289c4-d7e5-4568-b0f6-37a1bb19c23c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1701222710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.1701222710 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/21.kmac_alert_test.1645703508
Short name T951
Test name
Test status
Simulation time 15321511 ps
CPU time 0.76 seconds
Started Jul 29 04:56:32 PM PDT 24
Finished Jul 29 04:56:33 PM PDT 24
Peak memory 218372 kb
Host smart-f876726f-ef9a-4865-86c3-ed2da382dd30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645703508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.1645703508 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest

Test location /workspace/coverage/default/21.kmac_app.2122706167
Short name T639
Test name
Test status
Simulation time 3608402244 ps
CPU time 222.45 seconds
Started Jul 29 04:56:38 PM PDT 24
Finished Jul 29 05:00:21 PM PDT 24
Peak memory 297280 kb
Host smart-363ca459-aa0a-48de-a43f-bff8646d0b08
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122706167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.2122706167 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/21.kmac_app/latest

Test location /workspace/coverage/default/21.kmac_burst_write.1272221111
Short name T283
Test name
Test status
Simulation time 36531958202 ps
CPU time 1148.7 seconds
Started Jul 29 04:56:26 PM PDT 24
Finished Jul 29 05:15:34 PM PDT 24
Peak memory 254948 kb
Host smart-a565fd40-7071-4e41-9269-c1fc1d937bb2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272221111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.127222111
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest

Test location /workspace/coverage/default/21.kmac_entropy_refresh.4146371824
Short name T58
Test name
Test status
Simulation time 57368461846 ps
CPU time 165.05 seconds
Started Jul 29 04:56:36 PM PDT 24
Finished Jul 29 04:59:21 PM PDT 24
Peak memory 277424 kb
Host smart-b07a299b-47cd-4635-aa3f-8226185487b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146371824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.4
146371824 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/21.kmac_error.2196904293
Short name T570
Test name
Test status
Simulation time 36121775576 ps
CPU time 237.51 seconds
Started Jul 29 04:56:38 PM PDT 24
Finished Jul 29 05:00:36 PM PDT 24
Peak memory 440328 kb
Host smart-d53c7d82-936b-4d64-a291-265ac4e211cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196904293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.2196904293 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest

Test location /workspace/coverage/default/21.kmac_key_error.3994969518
Short name T474
Test name
Test status
Simulation time 2367904608 ps
CPU time 6.34 seconds
Started Jul 29 04:56:32 PM PDT 24
Finished Jul 29 04:56:38 PM PDT 24
Peak memory 218556 kb
Host smart-8ea34958-7e94-4302-8f44-abd6b6af4a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994969518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.3994969518 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest

Test location /workspace/coverage/default/21.kmac_lc_escalation.41360892
Short name T133
Test name
Test status
Simulation time 79307903 ps
CPU time 1.47 seconds
Started Jul 29 04:56:46 PM PDT 24
Finished Jul 29 04:56:47 PM PDT 24
Peak memory 226920 kb
Host smart-624caff9-542a-411e-b955-50e524ae6c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41360892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.41360892 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_lc_escalation/latest

Test location /workspace/coverage/default/21.kmac_long_msg_and_output.2342949082
Short name T589
Test name
Test status
Simulation time 95078926749 ps
CPU time 3180.41 seconds
Started Jul 29 04:56:34 PM PDT 24
Finished Jul 29 05:49:34 PM PDT 24
Peak memory 1635004 kb
Host smart-4709fcc2-6ef5-4ee4-b969-3e0b78e83ce1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342949082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_a
nd_output.2342949082 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/21.kmac_sideload.3386698131
Short name T341
Test name
Test status
Simulation time 18880187801 ps
CPU time 173.21 seconds
Started Jul 29 04:56:34 PM PDT 24
Finished Jul 29 04:59:28 PM PDT 24
Peak memory 355016 kb
Host smart-912de912-ba8a-4aab-8bea-65c05a6dd512
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386698131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.3386698131 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest

Test location /workspace/coverage/default/21.kmac_smoke.148967657
Short name T456
Test name
Test status
Simulation time 14105336200 ps
CPU time 80.43 seconds
Started Jul 29 04:56:26 PM PDT 24
Finished Jul 29 04:57:47 PM PDT 24
Peak memory 227364 kb
Host smart-f916926d-2823-4e3a-80cc-5a738c35d37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148967657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.148967657 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_smoke/latest

Test location /workspace/coverage/default/21.kmac_stress_all.788750457
Short name T462
Test name
Test status
Simulation time 1546827851 ps
CPU time 94.95 seconds
Started Jul 29 04:56:23 PM PDT 24
Finished Jul 29 04:57:58 PM PDT 24
Peak memory 261960 kb
Host smart-e37b6bee-141d-4fc2-a85e-91fad97dbd43
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=788750457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.788750457 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac.3664454096
Short name T513
Test name
Test status
Simulation time 882666136 ps
CPU time 6.11 seconds
Started Jul 29 04:56:39 PM PDT 24
Finished Jul 29 04:56:46 PM PDT 24
Peak memory 218840 kb
Host smart-5a7fe9c6-ae0b-45c6-98cf-23f29aba6046
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664454096 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.kmac_test_vectors_kmac.3664454096 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac_xof.323594603
Short name T215
Test name
Test status
Simulation time 860262731 ps
CPU time 7.34 seconds
Started Jul 29 04:56:30 PM PDT 24
Finished Jul 29 04:56:38 PM PDT 24
Peak memory 219772 kb
Host smart-d8144407-c707-4815-89ef-531303761400
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323594603 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.kmac_test_vectors_kmac_xof.323594603 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_224.572596954
Short name T649
Test name
Test status
Simulation time 651387098226 ps
CPU time 3306.22 seconds
Started Jul 29 04:56:23 PM PDT 24
Finished Jul 29 05:51:29 PM PDT 24
Peak memory 3221844 kb
Host smart-f1affe54-7263-4b4d-acb8-c05afbdc8584
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=572596954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.572596954 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_256.2507680200
Short name T577
Test name
Test status
Simulation time 630169058356 ps
CPU time 3089.2 seconds
Started Jul 29 04:56:48 PM PDT 24
Finished Jul 29 05:48:17 PM PDT 24
Peak memory 3103452 kb
Host smart-2eab716a-914e-41b4-95cb-1033f96867ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2507680200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.2507680200 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_384.2030491221
Short name T475
Test name
Test status
Simulation time 140678599125 ps
CPU time 2493.24 seconds
Started Jul 29 04:56:48 PM PDT 24
Finished Jul 29 05:38:22 PM PDT 24
Peak memory 2328880 kb
Host smart-8dc54af6-8210-45d9-b7b6-f30538cb9ec4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2030491221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.2030491221 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_512.775656554
Short name T402
Test name
Test status
Simulation time 40901895465 ps
CPU time 1297.25 seconds
Started Jul 29 04:56:31 PM PDT 24
Finished Jul 29 05:18:09 PM PDT 24
Peak memory 709792 kb
Host smart-e25d9f6f-dda4-487c-8015-6bc8c4e8b9fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=775656554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.775656554 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_256.3587809811
Short name T412
Test name
Test status
Simulation time 106006396309 ps
CPU time 5603.29 seconds
Started Jul 29 04:56:34 PM PDT 24
Finished Jul 29 06:29:58 PM PDT 24
Peak memory 2272396 kb
Host smart-d6b56595-cbe4-4638-8dd8-92fdf406f2ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3587809811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.3587809811 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/22.kmac_alert_test.4112274901
Short name T679
Test name
Test status
Simulation time 37630457 ps
CPU time 0.77 seconds
Started Jul 29 04:56:37 PM PDT 24
Finished Jul 29 04:56:38 PM PDT 24
Peak memory 218396 kb
Host smart-56816737-7be9-47df-b0c2-c3952df2ba36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112274901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.4112274901 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest

Test location /workspace/coverage/default/22.kmac_app.3749463465
Short name T32
Test name
Test status
Simulation time 34460805499 ps
CPU time 437.13 seconds
Started Jul 29 04:56:48 PM PDT 24
Finished Jul 29 05:04:05 PM PDT 24
Peak memory 506776 kb
Host smart-36eda100-b38b-4f42-b6f7-825b777c7410
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749463465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.3749463465 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/22.kmac_app/latest

Test location /workspace/coverage/default/22.kmac_burst_write.2930328515
Short name T435
Test name
Test status
Simulation time 30920972486 ps
CPU time 1363.54 seconds
Started Jul 29 04:56:35 PM PDT 24
Finished Jul 29 05:19:19 PM PDT 24
Peak memory 261868 kb
Host smart-52a8c500-6f45-4fc0-b9eb-1ac1f68bd7b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930328515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.293032851
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest

Test location /workspace/coverage/default/22.kmac_entropy_refresh.1155302989
Short name T496
Test name
Test status
Simulation time 1876453941 ps
CPU time 48.42 seconds
Started Jul 29 04:56:35 PM PDT 24
Finished Jul 29 04:57:24 PM PDT 24
Peak memory 255076 kb
Host smart-155dc56c-cb54-46e9-81a5-ea153a041004
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155302989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.1
155302989 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/22.kmac_error.2756966919
Short name T697
Test name
Test status
Simulation time 11973349415 ps
CPU time 484.4 seconds
Started Jul 29 04:56:36 PM PDT 24
Finished Jul 29 05:04:41 PM PDT 24
Peak memory 397740 kb
Host smart-0fa950e2-4811-4690-b406-5f83996bbb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756966919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.2756966919 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_key_error.1298287123
Short name T947
Test name
Test status
Simulation time 259733428 ps
CPU time 1.66 seconds
Started Jul 29 04:56:34 PM PDT 24
Finished Jul 29 04:56:36 PM PDT 24
Peak memory 226284 kb
Host smart-37f69bdc-6c8c-495c-9da7-2c099c93d44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298287123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.1298287123 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest

Test location /workspace/coverage/default/22.kmac_lc_escalation.3966876117
Short name T477
Test name
Test status
Simulation time 38653292 ps
CPU time 1.83 seconds
Started Jul 29 04:56:28 PM PDT 24
Finished Jul 29 04:56:30 PM PDT 24
Peak memory 226748 kb
Host smart-afa515ff-20e4-4761-b21e-f474666b73da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966876117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.3966876117 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/22.kmac_lc_escalation/latest

Test location /workspace/coverage/default/22.kmac_long_msg_and_output.248160444
Short name T813
Test name
Test status
Simulation time 489647517075 ps
CPU time 3336.74 seconds
Started Jul 29 04:56:35 PM PDT 24
Finished Jul 29 05:52:12 PM PDT 24
Peak memory 2724448 kb
Host smart-11147927-3afc-488a-a4bf-1e33f3c65592
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248160444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_an
d_output.248160444 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/22.kmac_sideload.1730446105
Short name T497
Test name
Test status
Simulation time 252323193605 ps
CPU time 458.18 seconds
Started Jul 29 04:56:41 PM PDT 24
Finished Jul 29 05:04:19 PM PDT 24
Peak memory 550768 kb
Host smart-2222476f-4447-4e53-8c22-2b2b27ca01a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730446105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.1730446105 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_sideload/latest

Test location /workspace/coverage/default/22.kmac_smoke.1254826361
Short name T190
Test name
Test status
Simulation time 29922348212 ps
CPU time 76.53 seconds
Started Jul 29 04:56:39 PM PDT 24
Finished Jul 29 04:57:56 PM PDT 24
Peak memory 227064 kb
Host smart-e1a44a2e-3a77-445d-a076-49a44e209d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254826361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.1254826361 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest

Test location /workspace/coverage/default/22.kmac_stress_all.3164098472
Short name T755
Test name
Test status
Simulation time 92318385804 ps
CPU time 3588.34 seconds
Started Jul 29 04:56:51 PM PDT 24
Finished Jul 29 05:56:40 PM PDT 24
Peak memory 2031596 kb
Host smart-411150e4-41e6-4c3f-b7ec-72ba9fea0bcc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3164098472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.3164098472 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac.3411082158
Short name T763
Test name
Test status
Simulation time 1727633748 ps
CPU time 6.85 seconds
Started Jul 29 04:56:31 PM PDT 24
Finished Jul 29 04:56:38 PM PDT 24
Peak memory 218904 kb
Host smart-a0eb7e6b-142a-49a1-9a83-32a969d839d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411082158 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.kmac_test_vectors_kmac.3411082158 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac_xof.3330512355
Short name T448
Test name
Test status
Simulation time 4440920524 ps
CPU time 7.13 seconds
Started Jul 29 04:56:42 PM PDT 24
Finished Jul 29 04:56:49 PM PDT 24
Peak memory 219856 kb
Host smart-957f75f9-b63b-460c-8a1c-0e0417264cc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330512355 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.kmac_test_vectors_kmac_xof.3330512355 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_224.1501689755
Short name T212
Test name
Test status
Simulation time 123323033571 ps
CPU time 2431.26 seconds
Started Jul 29 04:56:32 PM PDT 24
Finished Jul 29 05:37:04 PM PDT 24
Peak memory 1233144 kb
Host smart-ca712a43-c0ee-4ffd-a355-1a107c1e1d95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1501689755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.1501689755 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_256.3061356644
Short name T946
Test name
Test status
Simulation time 501396165359 ps
CPU time 3427.5 seconds
Started Jul 29 04:56:32 PM PDT 24
Finished Jul 29 05:53:40 PM PDT 24
Peak memory 3014592 kb
Host smart-85997dcd-5f1b-4745-9ad9-1a1eccdd7e5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3061356644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.3061356644 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_384.1408402933
Short name T823
Test name
Test status
Simulation time 59725608277 ps
CPU time 1772.26 seconds
Started Jul 29 04:56:33 PM PDT 24
Finished Jul 29 05:26:06 PM PDT 24
Peak memory 916640 kb
Host smart-933ac72b-7c2e-4ee1-9692-02a11bfc03d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1408402933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.1408402933 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_512.3548290311
Short name T938
Test name
Test status
Simulation time 281262384128 ps
CPU time 1703.6 seconds
Started Jul 29 04:56:36 PM PDT 24
Finished Jul 29 05:25:00 PM PDT 24
Peak memory 1755280 kb
Host smart-a4c5d70f-a95e-4987-9303-bac81a8079f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3548290311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.3548290311 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/23.kmac_alert_test.966651613
Short name T580
Test name
Test status
Simulation time 69280581 ps
CPU time 0.85 seconds
Started Jul 29 04:56:34 PM PDT 24
Finished Jul 29 04:56:36 PM PDT 24
Peak memory 218404 kb
Host smart-0d3093b5-a41c-419c-852d-cd4a3bf10738
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966651613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.966651613 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest

Test location /workspace/coverage/default/23.kmac_app.81112749
Short name T760
Test name
Test status
Simulation time 1714592777 ps
CPU time 43.33 seconds
Started Jul 29 04:56:43 PM PDT 24
Finished Jul 29 04:57:27 PM PDT 24
Peak memory 247404 kb
Host smart-484f1ff3-db9a-417d-aa3d-d745871dbd1a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81112749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.81112749 +enable_masking=1
+sw_key_masked=0
Directory /workspace/23.kmac_app/latest

Test location /workspace/coverage/default/23.kmac_burst_write.2022945964
Short name T840
Test name
Test status
Simulation time 72782604653 ps
CPU time 1653.26 seconds
Started Jul 29 04:56:37 PM PDT 24
Finished Jul 29 05:24:11 PM PDT 24
Peak memory 264404 kb
Host smart-f0b0bce8-31c2-47bd-8577-cb7722999f61
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022945964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.202294596
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_burst_write/latest

Test location /workspace/coverage/default/23.kmac_entropy_refresh.891317063
Short name T66
Test name
Test status
Simulation time 8029494195 ps
CPU time 332.09 seconds
Started Jul 29 04:56:34 PM PDT 24
Finished Jul 29 05:02:06 PM PDT 24
Peak memory 337104 kb
Host smart-e9b7c5f2-2639-4209-96f5-d3a20ddc6d1f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891317063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.89
1317063 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/23.kmac_error.414499968
Short name T488
Test name
Test status
Simulation time 13799057947 ps
CPU time 305.1 seconds
Started Jul 29 04:56:37 PM PDT 24
Finished Jul 29 05:01:43 PM PDT 24
Peak memory 324988 kb
Host smart-a53a5b7b-4a99-48c7-afcb-56fda85f3a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414499968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.414499968 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest

Test location /workspace/coverage/default/23.kmac_key_error.2634173435
Short name T242
Test name
Test status
Simulation time 236995681 ps
CPU time 2.46 seconds
Started Jul 29 04:56:30 PM PDT 24
Finished Jul 29 04:56:32 PM PDT 24
Peak memory 226564 kb
Host smart-f5a24692-4956-434f-bb4b-05694ad05371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634173435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.2634173435 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_key_error/latest

Test location /workspace/coverage/default/23.kmac_lc_escalation.2281419801
Short name T790
Test name
Test status
Simulation time 191514088 ps
CPU time 1.47 seconds
Started Jul 29 04:56:33 PM PDT 24
Finished Jul 29 04:56:35 PM PDT 24
Peak memory 226832 kb
Host smart-7d870da2-783c-4a00-aeea-538074098e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281419801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.2281419801 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/23.kmac_lc_escalation/latest

Test location /workspace/coverage/default/23.kmac_sideload.280359515
Short name T199
Test name
Test status
Simulation time 1763008287 ps
CPU time 73.98 seconds
Started Jul 29 04:56:33 PM PDT 24
Finished Jul 29 04:57:47 PM PDT 24
Peak memory 250564 kb
Host smart-0ff21def-0b77-41d2-860a-55d4114859db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280359515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.280359515 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest

Test location /workspace/coverage/default/23.kmac_smoke.3556676449
Short name T758
Test name
Test status
Simulation time 1613140107 ps
CPU time 9.81 seconds
Started Jul 29 04:56:36 PM PDT 24
Finished Jul 29 04:56:46 PM PDT 24
Peak memory 222592 kb
Host smart-c0a2f428-241b-4904-b4fb-716e9cb936d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556676449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.3556676449 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest

Test location /workspace/coverage/default/23.kmac_stress_all.1700306637
Short name T397
Test name
Test status
Simulation time 70572358519 ps
CPU time 2162.58 seconds
Started Jul 29 04:56:41 PM PDT 24
Finished Jul 29 05:32:44 PM PDT 24
Peak memory 1122140 kb
Host smart-cefd8ba6-9f6a-49fb-909a-43eff26238ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1700306637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.1700306637 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac.3986457934
Short name T237
Test name
Test status
Simulation time 109026040 ps
CPU time 5.95 seconds
Started Jul 29 04:56:45 PM PDT 24
Finished Jul 29 04:56:51 PM PDT 24
Peak memory 219684 kb
Host smart-1a36990a-cc71-488c-9c0d-6464a42d0e86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986457934 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.kmac_test_vectors_kmac.3986457934 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac_xof.3532415580
Short name T281
Test name
Test status
Simulation time 1521339753 ps
CPU time 6.44 seconds
Started Jul 29 04:56:40 PM PDT 24
Finished Jul 29 04:56:47 PM PDT 24
Peak memory 218720 kb
Host smart-0ebfb7f0-fa76-494e-a414-dccba819e0bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532415580 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.kmac_test_vectors_kmac_xof.3532415580 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_224.544977312
Short name T306
Test name
Test status
Simulation time 42164333282 ps
CPU time 2344.16 seconds
Started Jul 29 04:56:37 PM PDT 24
Finished Jul 29 05:35:42 PM PDT 24
Peak memory 1170064 kb
Host smart-a8e5e9a2-1852-4ef9-a87e-f956025eba95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=544977312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.544977312 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_256.4212543083
Short name T875
Test name
Test status
Simulation time 31672089761 ps
CPU time 2152.95 seconds
Started Jul 29 04:56:32 PM PDT 24
Finished Jul 29 05:32:25 PM PDT 24
Peak memory 1153408 kb
Host smart-0c034f16-9808-442e-844e-325e6290faf8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4212543083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.4212543083 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_384.316746819
Short name T675
Test name
Test status
Simulation time 292012386025 ps
CPU time 2632.32 seconds
Started Jul 29 04:56:37 PM PDT 24
Finished Jul 29 05:40:29 PM PDT 24
Peak memory 2380480 kb
Host smart-0f07e0a5-2016-4c86-bda5-b5649086d082
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=316746819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.316746819 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_512.45831748
Short name T851
Test name
Test status
Simulation time 33450732730 ps
CPU time 1508.97 seconds
Started Jul 29 04:56:36 PM PDT 24
Finished Jul 29 05:21:45 PM PDT 24
Peak memory 1722004 kb
Host smart-7ec14e79-b531-4dde-9f5b-c29bd089f871
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=45831748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.45831748 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_256.4010868990
Short name T702
Test name
Test status
Simulation time 71965285346 ps
CPU time 5604.38 seconds
Started Jul 29 04:56:27 PM PDT 24
Finished Jul 29 06:29:53 PM PDT 24
Peak memory 2236304 kb
Host smart-574ef248-2792-4bd5-9c0a-9c10bb038fa0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4010868990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.4010868990 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/24.kmac_alert_test.1854034519
Short name T958
Test name
Test status
Simulation time 15797668 ps
CPU time 0.86 seconds
Started Jul 29 04:56:51 PM PDT 24
Finished Jul 29 04:56:52 PM PDT 24
Peak memory 218376 kb
Host smart-107696c1-8504-4abc-bab9-a76cbf6f8e02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854034519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.1854034519 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_alert_test/latest

Test location /workspace/coverage/default/24.kmac_app.1400701481
Short name T375
Test name
Test status
Simulation time 572756512 ps
CPU time 14.92 seconds
Started Jul 29 04:56:35 PM PDT 24
Finished Jul 29 04:56:50 PM PDT 24
Peak memory 239208 kb
Host smart-45b8644d-c555-4c1a-a145-ad7f6663ecab
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400701481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.1400701481 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/24.kmac_app/latest

Test location /workspace/coverage/default/24.kmac_burst_write.2804651365
Short name T271
Test name
Test status
Simulation time 36574189576 ps
CPU time 960.38 seconds
Started Jul 29 04:56:32 PM PDT 24
Finished Jul 29 05:12:32 PM PDT 24
Peak memory 252628 kb
Host smart-cea0b49d-d820-4ad6-a87d-61f087455c4a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804651365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.280465136
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_burst_write/latest

Test location /workspace/coverage/default/24.kmac_entropy_refresh.3651924536
Short name T852
Test name
Test status
Simulation time 1260338341 ps
CPU time 34.32 seconds
Started Jul 29 04:56:40 PM PDT 24
Finished Jul 29 04:57:15 PM PDT 24
Peak memory 232800 kb
Host smart-6839ec28-050d-42c5-a2e1-507e15bdf0ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651924536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.3
651924536 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/24.kmac_error.1136104895
Short name T804
Test name
Test status
Simulation time 35162462884 ps
CPU time 484.23 seconds
Started Jul 29 04:56:39 PM PDT 24
Finished Jul 29 05:04:43 PM PDT 24
Peak memory 574920 kb
Host smart-ebfb6f12-1ebb-4c8f-bb72-54200d8b7b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136104895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.1136104895 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest

Test location /workspace/coverage/default/24.kmac_key_error.654142364
Short name T642
Test name
Test status
Simulation time 1598401857 ps
CPU time 6.39 seconds
Started Jul 29 04:56:41 PM PDT 24
Finished Jul 29 04:56:47 PM PDT 24
Peak memory 218628 kb
Host smart-b803073f-0cac-4d86-94ed-a3ce19b1896d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654142364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.654142364 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest

Test location /workspace/coverage/default/24.kmac_lc_escalation.3220603625
Short name T455
Test name
Test status
Simulation time 5060186337 ps
CPU time 19.62 seconds
Started Jul 29 04:56:44 PM PDT 24
Finished Jul 29 04:57:03 PM PDT 24
Peak memory 241668 kb
Host smart-962eb126-48f5-4e24-89d4-6b94876ec865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220603625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.3220603625 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/24.kmac_lc_escalation/latest

Test location /workspace/coverage/default/24.kmac_long_msg_and_output.1479046166
Short name T664
Test name
Test status
Simulation time 50286972792 ps
CPU time 2053.73 seconds
Started Jul 29 04:56:35 PM PDT 24
Finished Jul 29 05:30:49 PM PDT 24
Peak memory 2011560 kb
Host smart-e6153640-5514-403d-982c-a94042798e85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479046166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_a
nd_output.1479046166 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/24.kmac_sideload.2021358360
Short name T901
Test name
Test status
Simulation time 24603299976 ps
CPU time 364.74 seconds
Started Jul 29 04:56:53 PM PDT 24
Finished Jul 29 05:02:58 PM PDT 24
Peak memory 477604 kb
Host smart-07e573d7-647e-47f5-a792-8d5422176358
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021358360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.2021358360 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest

Test location /workspace/coverage/default/24.kmac_smoke.664686311
Short name T600
Test name
Test status
Simulation time 3695782368 ps
CPU time 51.46 seconds
Started Jul 29 04:56:48 PM PDT 24
Finished Jul 29 04:57:40 PM PDT 24
Peak memory 226884 kb
Host smart-ac227d16-de6d-4855-a220-d98075ccaa8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664686311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.664686311 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest

Test location /workspace/coverage/default/24.kmac_stress_all.1956849974
Short name T766
Test name
Test status
Simulation time 229561260481 ps
CPU time 1995.86 seconds
Started Jul 29 04:56:37 PM PDT 24
Finished Jul 29 05:29:53 PM PDT 24
Peak memory 1323372 kb
Host smart-2c7142b8-2379-4bd9-812c-3586da4abab3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1956849974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.1956849974 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac.2027608387
Short name T311
Test name
Test status
Simulation time 233658821 ps
CPU time 7.01 seconds
Started Jul 29 04:56:47 PM PDT 24
Finished Jul 29 04:56:54 PM PDT 24
Peak memory 219792 kb
Host smart-6043d735-c0d6-4778-96c9-26cc396f8a6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027608387 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.kmac_test_vectors_kmac.2027608387 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac_xof.551121383
Short name T356
Test name
Test status
Simulation time 883978781 ps
CPU time 7.67 seconds
Started Jul 29 04:56:43 PM PDT 24
Finished Jul 29 04:56:51 PM PDT 24
Peak memory 218928 kb
Host smart-7442e560-61dd-456e-b0df-11291cf3f597
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551121383 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.kmac_test_vectors_kmac_xof.551121383 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_256.2971589837
Short name T683
Test name
Test status
Simulation time 136804606346 ps
CPU time 2229.49 seconds
Started Jul 29 04:56:41 PM PDT 24
Finished Jul 29 05:33:51 PM PDT 24
Peak memory 1151928 kb
Host smart-d22d1a57-b092-4477-8ebf-3258f183f53e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2971589837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.2971589837 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_384.3648783709
Short name T654
Test name
Test status
Simulation time 124259612014 ps
CPU time 1886.11 seconds
Started Jul 29 04:56:42 PM PDT 24
Finished Jul 29 05:28:09 PM PDT 24
Peak memory 931196 kb
Host smart-b6f210bc-d814-42be-9451-e5f37b973ede
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3648783709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.3648783709 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_512.760439838
Short name T537
Test name
Test status
Simulation time 21874227087 ps
CPU time 1272.41 seconds
Started Jul 29 04:56:32 PM PDT 24
Finished Jul 29 05:17:45 PM PDT 24
Peak memory 705280 kb
Host smart-18fd1238-ec70-46a0-9e6f-1c80e4b17695
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=760439838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.760439838 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/25.kmac_alert_test.3273585234
Short name T92
Test name
Test status
Simulation time 16664209 ps
CPU time 0.84 seconds
Started Jul 29 04:56:48 PM PDT 24
Finished Jul 29 04:56:49 PM PDT 24
Peak memory 218424 kb
Host smart-3aa45030-22e5-4c65-8935-e97d9cd1c9bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273585234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.3273585234 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_alert_test/latest

Test location /workspace/coverage/default/25.kmac_app.1292527179
Short name T919
Test name
Test status
Simulation time 825122972 ps
CPU time 28.29 seconds
Started Jul 29 04:56:49 PM PDT 24
Finished Jul 29 04:57:17 PM PDT 24
Peak memory 229560 kb
Host smart-6fdc37f3-ad8a-43c6-858d-021b0e7151c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292527179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.1292527179 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/25.kmac_app/latest

Test location /workspace/coverage/default/25.kmac_burst_write.2574759386
Short name T91
Test name
Test status
Simulation time 6296944598 ps
CPU time 751.1 seconds
Started Jul 29 04:56:49 PM PDT 24
Finished Jul 29 05:09:20 PM PDT 24
Peak memory 243300 kb
Host smart-76e38608-afa6-40cd-a218-51033bc69e0b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574759386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.257475938
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest

Test location /workspace/coverage/default/25.kmac_entropy_refresh.1898075978
Short name T135
Test name
Test status
Simulation time 110213288787 ps
CPU time 345.95 seconds
Started Jul 29 04:56:47 PM PDT 24
Finished Jul 29 05:02:33 PM PDT 24
Peak memory 317456 kb
Host smart-0aca8432-d39c-4cf2-9b59-1fc4f4aec95e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898075978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.1
898075978 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/25.kmac_error.3375585505
Short name T862
Test name
Test status
Simulation time 74511150132 ps
CPU time 584.09 seconds
Started Jul 29 04:56:37 PM PDT 24
Finished Jul 29 05:06:22 PM PDT 24
Peak memory 640476 kb
Host smart-bb625cef-fea2-46f3-9d3d-e8d946ad8440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375585505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.3375585505 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_error/latest

Test location /workspace/coverage/default/25.kmac_key_error.978917401
Short name T372
Test name
Test status
Simulation time 204960612 ps
CPU time 2.1 seconds
Started Jul 29 04:56:33 PM PDT 24
Finished Jul 29 04:56:35 PM PDT 24
Peak memory 226380 kb
Host smart-b3573689-61fc-45b1-8f61-2e8b2de02c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978917401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.978917401 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest

Test location /workspace/coverage/default/25.kmac_long_msg_and_output.88060288
Short name T637
Test name
Test status
Simulation time 147995826908 ps
CPU time 1479.66 seconds
Started Jul 29 04:56:48 PM PDT 24
Finished Jul 29 05:21:28 PM PDT 24
Peak memory 1580348 kb
Host smart-a0dc6f07-24a4-4e49-995a-e29eb07c0313
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88060288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_and
_output.88060288 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/25.kmac_sideload.2972008845
Short name T531
Test name
Test status
Simulation time 4766214713 ps
CPU time 391.68 seconds
Started Jul 29 04:56:39 PM PDT 24
Finished Jul 29 05:03:11 PM PDT 24
Peak memory 346796 kb
Host smart-34b90ce9-3949-4c2e-88a3-f9e397ed06d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972008845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.2972008845 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_sideload/latest

Test location /workspace/coverage/default/25.kmac_smoke.3941089508
Short name T539
Test name
Test status
Simulation time 4853046195 ps
CPU time 32.34 seconds
Started Jul 29 04:56:38 PM PDT 24
Finished Jul 29 04:57:11 PM PDT 24
Peak memory 226856 kb
Host smart-d17c6cea-227c-43ed-b9d3-9de2441ab486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941089508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.3941089508 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest

Test location /workspace/coverage/default/25.kmac_stress_all.4061050028
Short name T594
Test name
Test status
Simulation time 388769790993 ps
CPU time 4072.43 seconds
Started Jul 29 04:56:52 PM PDT 24
Finished Jul 29 06:04:45 PM PDT 24
Peak memory 1539276 kb
Host smart-6bf4faf4-72ff-4e1b-a661-37c381026559
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4061050028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.4061050028 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac.2351621015
Short name T692
Test name
Test status
Simulation time 238804299 ps
CPU time 6.28 seconds
Started Jul 29 04:56:53 PM PDT 24
Finished Jul 29 04:56:59 PM PDT 24
Peak memory 219724 kb
Host smart-deac2f05-2844-49a3-9be9-7a9fabf418da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351621015 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.kmac_test_vectors_kmac.2351621015 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac_xof.1289639280
Short name T633
Test name
Test status
Simulation time 184284528 ps
CPU time 6.31 seconds
Started Jul 29 04:56:42 PM PDT 24
Finished Jul 29 04:56:49 PM PDT 24
Peak memory 219672 kb
Host smart-83f97bf3-d2d7-474d-a398-d0a286702587
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289639280 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.kmac_test_vectors_kmac_xof.1289639280 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_256.915401546
Short name T101
Test name
Test status
Simulation time 63771246532 ps
CPU time 2987.31 seconds
Started Jul 29 04:56:49 PM PDT 24
Finished Jul 29 05:46:37 PM PDT 24
Peak memory 3012896 kb
Host smart-e2f79b86-9229-48fa-ab25-991adb259b90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=915401546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.915401546 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_384.400103444
Short name T241
Test name
Test status
Simulation time 69714652979 ps
CPU time 1785.52 seconds
Started Jul 29 04:56:40 PM PDT 24
Finished Jul 29 05:26:26 PM PDT 24
Peak memory 934064 kb
Host smart-91d99549-0820-4e51-8978-48c57ca92043
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=400103444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.400103444 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_512.1849071018
Short name T538
Test name
Test status
Simulation time 44012110711 ps
CPU time 1643.56 seconds
Started Jul 29 04:56:38 PM PDT 24
Finished Jul 29 05:24:02 PM PDT 24
Peak memory 1753784 kb
Host smart-e8da64e8-3045-4053-acfd-1381113aaba4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1849071018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.1849071018 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/26.kmac_alert_test.3579447574
Short name T757
Test name
Test status
Simulation time 12811778 ps
CPU time 0.82 seconds
Started Jul 29 04:56:40 PM PDT 24
Finished Jul 29 04:56:41 PM PDT 24
Peak memory 218448 kb
Host smart-6babd2e1-26b3-4c11-959d-965a780b4507
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579447574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.3579447574 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest

Test location /workspace/coverage/default/26.kmac_app.191882538
Short name T486
Test name
Test status
Simulation time 47957938266 ps
CPU time 268.66 seconds
Started Jul 29 04:56:43 PM PDT 24
Finished Jul 29 05:01:12 PM PDT 24
Peak memory 437600 kb
Host smart-271f8596-2f8c-453b-b023-80860bc46f75
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191882538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.191882538 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest

Test location /workspace/coverage/default/26.kmac_burst_write.3680817775
Short name T749
Test name
Test status
Simulation time 31896235574 ps
CPU time 1642.13 seconds
Started Jul 29 04:56:43 PM PDT 24
Finished Jul 29 05:24:05 PM PDT 24
Peak memory 250804 kb
Host smart-376697bb-2d71-4a67-bbe8-837b77d5175b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680817775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.368081777
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest

Test location /workspace/coverage/default/26.kmac_entropy_refresh.2631658818
Short name T355
Test name
Test status
Simulation time 19304347787 ps
CPU time 373.39 seconds
Started Jul 29 04:56:50 PM PDT 24
Finished Jul 29 05:03:03 PM PDT 24
Peak memory 339684 kb
Host smart-5ce6b94a-b8f3-41eb-8182-240b0d9f0c26
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631658818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.2
631658818 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/26.kmac_error.3530095289
Short name T21
Test name
Test status
Simulation time 7673555679 ps
CPU time 238.09 seconds
Started Jul 29 04:56:45 PM PDT 24
Finished Jul 29 05:00:44 PM PDT 24
Peak memory 308776 kb
Host smart-b207dd49-c0f6-4ec4-8dad-56a6c9db8243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530095289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.3530095289 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest

Test location /workspace/coverage/default/26.kmac_key_error.4043755425
Short name T888
Test name
Test status
Simulation time 7531609905 ps
CPU time 15.57 seconds
Started Jul 29 04:56:41 PM PDT 24
Finished Jul 29 04:56:56 PM PDT 24
Peak memory 226676 kb
Host smart-219af91b-f568-485f-9913-4d0a3df08499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043755425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.4043755425 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_key_error/latest

Test location /workspace/coverage/default/26.kmac_lc_escalation.153307126
Short name T42
Test name
Test status
Simulation time 71411493 ps
CPU time 1.3 seconds
Started Jul 29 04:56:48 PM PDT 24
Finished Jul 29 04:56:49 PM PDT 24
Peak memory 226800 kb
Host smart-975e3f1c-2d14-45a5-b12e-c29fcda527f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153307126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.153307126 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/26.kmac_lc_escalation/latest

Test location /workspace/coverage/default/26.kmac_long_msg_and_output.3995425315
Short name T219
Test name
Test status
Simulation time 96105228811 ps
CPU time 3055.05 seconds
Started Jul 29 04:56:38 PM PDT 24
Finished Jul 29 05:47:34 PM PDT 24
Peak memory 2723148 kb
Host smart-7c1ea184-1c8f-45af-955c-10458eae3850
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995425315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_a
nd_output.3995425315 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/26.kmac_sideload.2079241306
Short name T870
Test name
Test status
Simulation time 14427840840 ps
CPU time 201.75 seconds
Started Jul 29 04:56:43 PM PDT 24
Finished Jul 29 05:00:05 PM PDT 24
Peak memory 373920 kb
Host smart-fec97e1a-53a9-42f5-8b5f-2321a361be11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079241306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.2079241306 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest

Test location /workspace/coverage/default/26.kmac_smoke.3106510584
Short name T853
Test name
Test status
Simulation time 367483805 ps
CPU time 9.4 seconds
Started Jul 29 04:56:39 PM PDT 24
Finished Jul 29 04:56:48 PM PDT 24
Peak memory 226628 kb
Host smart-00439314-3605-4dcc-9522-c18290d49aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106510584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.3106510584 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_smoke/latest

Test location /workspace/coverage/default/26.kmac_stress_all.2261065326
Short name T504
Test name
Test status
Simulation time 14339212112 ps
CPU time 680.49 seconds
Started Jul 29 04:56:48 PM PDT 24
Finished Jul 29 05:08:09 PM PDT 24
Peak memory 640568 kb
Host smart-05e08547-7957-4a86-ac90-61cedb0a6593
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2261065326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.2261065326 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac.4274611859
Short name T36
Test name
Test status
Simulation time 252754163 ps
CPU time 6.62 seconds
Started Jul 29 04:56:42 PM PDT 24
Finished Jul 29 04:56:48 PM PDT 24
Peak memory 218664 kb
Host smart-127d33ba-e1e6-4ef2-bd3d-64ad8e3e9020
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274611859 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.kmac_test_vectors_kmac.4274611859 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac_xof.1361049836
Short name T708
Test name
Test status
Simulation time 2420276808 ps
CPU time 6.13 seconds
Started Jul 29 04:56:44 PM PDT 24
Finished Jul 29 04:56:50 PM PDT 24
Peak memory 219004 kb
Host smart-16185064-143e-4a9c-a239-498f457e1fe7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361049836 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.kmac_test_vectors_kmac_xof.1361049836 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_224.185057982
Short name T303
Test name
Test status
Simulation time 268647335329 ps
CPU time 3128.49 seconds
Started Jul 29 04:56:39 PM PDT 24
Finished Jul 29 05:48:48 PM PDT 24
Peak memory 3168120 kb
Host smart-ea474b08-70cd-420f-9c85-ec858ae33be2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=185057982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.185057982 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_256.2951896743
Short name T704
Test name
Test status
Simulation time 31898345605 ps
CPU time 2280.73 seconds
Started Jul 29 04:56:44 PM PDT 24
Finished Jul 29 05:34:45 PM PDT 24
Peak memory 1151784 kb
Host smart-ff304411-2097-4cd3-8591-5c8d5de75f01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2951896743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.2951896743 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_384.965835944
Short name T204
Test name
Test status
Simulation time 75177387856 ps
CPU time 2859.5 seconds
Started Jul 29 04:56:51 PM PDT 24
Finished Jul 29 05:44:31 PM PDT 24
Peak memory 2419652 kb
Host smart-8595d0bb-3ed2-4ffd-9692-fd4c9502fdb9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=965835944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.965835944 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_512.2913283558
Short name T294
Test name
Test status
Simulation time 221231421821 ps
CPU time 1652.76 seconds
Started Jul 29 04:56:44 PM PDT 24
Finished Jul 29 05:24:17 PM PDT 24
Peak memory 1720772 kb
Host smart-595d19dd-2a7f-49bf-a599-348da50ef133
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2913283558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.2913283558 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_128.895228525
Short name T502
Test name
Test status
Simulation time 211025263947 ps
CPU time 6492.26 seconds
Started Jul 29 04:56:37 PM PDT 24
Finished Jul 29 06:44:50 PM PDT 24
Peak memory 2618988 kb
Host smart-4ef47123-02c8-49c2-925a-fe3e647db374
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=895228525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.895228525 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/27.kmac_alert_test.1588027893
Short name T540
Test name
Test status
Simulation time 30706669 ps
CPU time 0.75 seconds
Started Jul 29 04:56:48 PM PDT 24
Finished Jul 29 04:56:49 PM PDT 24
Peak memory 218336 kb
Host smart-6e04c33a-bc70-497c-87de-bdc0eb2eb09f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588027893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.1588027893 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest

Test location /workspace/coverage/default/27.kmac_app.3349122136
Short name T720
Test name
Test status
Simulation time 10698960705 ps
CPU time 162.88 seconds
Started Jul 29 04:56:41 PM PDT 24
Finished Jul 29 04:59:24 PM PDT 24
Peak memory 274872 kb
Host smart-6884b00a-7873-4fa4-b451-51291eac04b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349122136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.3349122136 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/27.kmac_app/latest

Test location /workspace/coverage/default/27.kmac_burst_write.2214078037
Short name T364
Test name
Test status
Simulation time 72585483198 ps
CPU time 1168.46 seconds
Started Jul 29 04:56:48 PM PDT 24
Finished Jul 29 05:16:16 PM PDT 24
Peak memory 255024 kb
Host smart-d226ce5c-32a6-4a71-bab1-7d8f846ab71a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214078037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.221407803
7 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest

Test location /workspace/coverage/default/27.kmac_entropy_refresh.994311066
Short name T591
Test name
Test status
Simulation time 16466396240 ps
CPU time 89.88 seconds
Started Jul 29 04:56:45 PM PDT 24
Finished Jul 29 04:58:15 PM PDT 24
Peak memory 252560 kb
Host smart-93b4b520-d92d-4009-972c-c85231d5d410
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994311066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.99
4311066 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/27.kmac_error.2411625050
Short name T55
Test name
Test status
Simulation time 12364890883 ps
CPU time 380.88 seconds
Started Jul 29 04:56:41 PM PDT 24
Finished Jul 29 05:03:02 PM PDT 24
Peak memory 488264 kb
Host smart-cccfa475-5146-460b-ab05-8cc9c21ad878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411625050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.2411625050 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest

Test location /workspace/coverage/default/27.kmac_key_error.663018630
Short name T754
Test name
Test status
Simulation time 1051781339 ps
CPU time 4.36 seconds
Started Jul 29 04:56:47 PM PDT 24
Finished Jul 29 04:56:52 PM PDT 24
Peak memory 226540 kb
Host smart-458e8b99-4d31-44b7-b1e9-3d2dc4634ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663018630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.663018630 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest

Test location /workspace/coverage/default/27.kmac_lc_escalation.1137084831
Short name T898
Test name
Test status
Simulation time 40054817 ps
CPU time 1.5 seconds
Started Jul 29 04:56:52 PM PDT 24
Finished Jul 29 04:56:54 PM PDT 24
Peak memory 226772 kb
Host smart-3905f3f9-5dad-4d14-b09e-f4b18d0ad013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137084831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.1137084831 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/27.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_long_msg_and_output.4033516212
Short name T578
Test name
Test status
Simulation time 7100726831 ps
CPU time 321.25 seconds
Started Jul 29 04:56:46 PM PDT 24
Finished Jul 29 05:02:07 PM PDT 24
Peak memory 385240 kb
Host smart-c7efbf13-41b4-444e-8d48-13a29b41d329
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033516212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_a
nd_output.4033516212 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/27.kmac_sideload.1122116362
Short name T406
Test name
Test status
Simulation time 31136587680 ps
CPU time 535.37 seconds
Started Jul 29 04:56:39 PM PDT 24
Finished Jul 29 05:05:35 PM PDT 24
Peak memory 628172 kb
Host smart-d4209ff3-9eb6-4a26-a981-2f652340cee9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122116362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.1122116362 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest

Test location /workspace/coverage/default/27.kmac_smoke.2631343746
Short name T217
Test name
Test status
Simulation time 2100123278 ps
CPU time 72.24 seconds
Started Jul 29 04:56:42 PM PDT 24
Finished Jul 29 04:57:54 PM PDT 24
Peak memory 226848 kb
Host smart-c5a4f1c5-5441-4ed9-ad93-d38bbe7f6a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631343746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.2631343746 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest

Test location /workspace/coverage/default/27.kmac_stress_all.2273122266
Short name T844
Test name
Test status
Simulation time 23693178932 ps
CPU time 1595.11 seconds
Started Jul 29 04:56:51 PM PDT 24
Finished Jul 29 05:23:26 PM PDT 24
Peak memory 679664 kb
Host smart-86927ed8-50ce-406f-a700-9fdefad8d11e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2273122266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.2273122266 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac.1588649127
Short name T780
Test name
Test status
Simulation time 756654960 ps
CPU time 6.19 seconds
Started Jul 29 04:56:44 PM PDT 24
Finished Jul 29 04:56:51 PM PDT 24
Peak memory 219752 kb
Host smart-161c7413-5a5c-43cc-839c-88e0edafb206
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588649127 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.kmac_test_vectors_kmac.1588649127 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac_xof.4193892321
Short name T395
Test name
Test status
Simulation time 119759310 ps
CPU time 5.78 seconds
Started Jul 29 04:56:54 PM PDT 24
Finished Jul 29 04:57:00 PM PDT 24
Peak memory 218816 kb
Host smart-b1f227c2-73bd-41fb-b2c1-c1b70f3c76db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193892321 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.kmac_test_vectors_kmac_xof.4193892321 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_256.1782537828
Short name T672
Test name
Test status
Simulation time 20272508080 ps
CPU time 2096.43 seconds
Started Jul 29 04:56:38 PM PDT 24
Finished Jul 29 05:31:35 PM PDT 24
Peak memory 1124684 kb
Host smart-598d2eb7-b10b-4393-b302-89a91276d054
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1782537828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.1782537828 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_384.2992885470
Short name T928
Test name
Test status
Simulation time 120472682705 ps
CPU time 2468.24 seconds
Started Jul 29 04:56:52 PM PDT 24
Finished Jul 29 05:38:01 PM PDT 24
Peak memory 2355028 kb
Host smart-d1f41759-4453-402c-8c52-4b7cd28b20f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2992885470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.2992885470 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_512.2062784180
Short name T621
Test name
Test status
Simulation time 140780572679 ps
CPU time 1736.9 seconds
Started Jul 29 04:56:50 PM PDT 24
Finished Jul 29 05:25:47 PM PDT 24
Peak memory 1746220 kb
Host smart-3a6b33c4-2006-4ba8-ab91-99b186227c02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2062784180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.2062784180 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/28.kmac_alert_test.576240608
Short name T656
Test name
Test status
Simulation time 79455309 ps
CPU time 0.82 seconds
Started Jul 29 04:56:51 PM PDT 24
Finished Jul 29 04:56:52 PM PDT 24
Peak memory 218580 kb
Host smart-bee3803c-ad33-4b27-bdaa-dca8e5f25e83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576240608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.576240608 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest

Test location /workspace/coverage/default/28.kmac_app.3579789796
Short name T912
Test name
Test status
Simulation time 11235742095 ps
CPU time 328.65 seconds
Started Jul 29 04:56:47 PM PDT 24
Finished Jul 29 05:02:16 PM PDT 24
Peak memory 466492 kb
Host smart-677a48e0-617a-4b4f-a829-641569aee4d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579789796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.3579789796 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/28.kmac_app/latest

Test location /workspace/coverage/default/28.kmac_burst_write.3722314203
Short name T405
Test name
Test status
Simulation time 35857114766 ps
CPU time 1410.51 seconds
Started Jul 29 04:56:50 PM PDT 24
Finished Jul 29 05:20:21 PM PDT 24
Peak memory 263892 kb
Host smart-10aa13fc-e7d3-4c37-8fda-46b7ffd28c5b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722314203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.372231420
3 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_burst_write/latest

Test location /workspace/coverage/default/28.kmac_entropy_refresh.4277109633
Short name T748
Test name
Test status
Simulation time 22225533532 ps
CPU time 197.79 seconds
Started Jul 29 04:56:48 PM PDT 24
Finished Jul 29 05:00:06 PM PDT 24
Peak memory 286128 kb
Host smart-5f48dd29-bd14-4a8a-8bba-a1570f89bc0e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277109633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.4
277109633 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/28.kmac_error.2120040131
Short name T500
Test name
Test status
Simulation time 3705744135 ps
CPU time 137.42 seconds
Started Jul 29 04:56:52 PM PDT 24
Finished Jul 29 04:59:09 PM PDT 24
Peak memory 287556 kb
Host smart-e2670e9a-02f5-4cf4-b91d-5f2d17c539d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120040131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.2120040131 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest

Test location /workspace/coverage/default/28.kmac_key_error.1158665136
Short name T98
Test name
Test status
Simulation time 468211997 ps
CPU time 4.04 seconds
Started Jul 29 04:56:49 PM PDT 24
Finished Jul 29 04:56:53 PM PDT 24
Peak memory 226612 kb
Host smart-67a47b3b-1800-41ac-a7c7-6ea3e06fe55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158665136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.1158665136 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest

Test location /workspace/coverage/default/28.kmac_lc_escalation.45829582
Short name T404
Test name
Test status
Simulation time 26285353 ps
CPU time 1.39 seconds
Started Jul 29 04:56:49 PM PDT 24
Finished Jul 29 04:56:51 PM PDT 24
Peak memory 226736 kb
Host smart-83756331-3725-482d-8097-e1a515b3c049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45829582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.45829582 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_lc_escalation/latest

Test location /workspace/coverage/default/28.kmac_long_msg_and_output.1788027735
Short name T499
Test name
Test status
Simulation time 6903251879 ps
CPU time 102.47 seconds
Started Jul 29 04:56:49 PM PDT 24
Finished Jul 29 04:58:32 PM PDT 24
Peak memory 334536 kb
Host smart-74920840-1993-42b3-b7af-7654b4870104
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788027735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_a
nd_output.1788027735 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/28.kmac_sideload.1987881167
Short name T961
Test name
Test status
Simulation time 29931611762 ps
CPU time 544.37 seconds
Started Jul 29 04:56:43 PM PDT 24
Finished Jul 29 05:05:48 PM PDT 24
Peak memory 591912 kb
Host smart-5f18e586-2ff5-4cd6-aaf5-32c8a080910f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987881167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.1987881167 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest

Test location /workspace/coverage/default/28.kmac_smoke.3644860196
Short name T75
Test name
Test status
Simulation time 4439432714 ps
CPU time 39.91 seconds
Started Jul 29 04:56:50 PM PDT 24
Finished Jul 29 04:57:30 PM PDT 24
Peak memory 226900 kb
Host smart-0f208dab-9954-492a-ab0b-11cf753a3aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644860196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.3644860196 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest

Test location /workspace/coverage/default/28.kmac_stress_all.2426241689
Short name T109
Test name
Test status
Simulation time 72651409619 ps
CPU time 1240.17 seconds
Started Jul 29 04:56:48 PM PDT 24
Finished Jul 29 05:17:28 PM PDT 24
Peak memory 1311208 kb
Host smart-0cd07c01-ef34-46e7-a02e-80e70b6eb7b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2426241689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.2426241689 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac.3692883264
Short name T203
Test name
Test status
Simulation time 120578769 ps
CPU time 5.51 seconds
Started Jul 29 04:56:45 PM PDT 24
Finished Jul 29 04:56:50 PM PDT 24
Peak memory 218796 kb
Host smart-f21528a6-134f-49ef-aa3d-bd606edc00f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692883264 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.kmac_test_vectors_kmac.3692883264 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac_xof.4225108904
Short name T643
Test name
Test status
Simulation time 120623306 ps
CPU time 5.97 seconds
Started Jul 29 04:56:46 PM PDT 24
Finished Jul 29 04:56:52 PM PDT 24
Peak memory 219712 kb
Host smart-c72ca426-1097-45e5-9eaa-451ad5752b8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225108904 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.kmac_test_vectors_kmac_xof.4225108904 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_224.1582579644
Short name T442
Test name
Test status
Simulation time 97701276142 ps
CPU time 3515 seconds
Started Jul 29 04:56:52 PM PDT 24
Finished Jul 29 05:55:27 PM PDT 24
Peak memory 3127624 kb
Host smart-0b0f0671-ecfe-4779-8b1f-ae29d167e8dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1582579644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.1582579644 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_256.3268880879
Short name T221
Test name
Test status
Simulation time 196075449867 ps
CPU time 2294.92 seconds
Started Jul 29 04:56:55 PM PDT 24
Finished Jul 29 05:35:10 PM PDT 24
Peak memory 1165452 kb
Host smart-953814ce-737e-44f8-a7e8-f0fc50c2344d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3268880879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.3268880879 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_384.3933675114
Short name T316
Test name
Test status
Simulation time 107626154703 ps
CPU time 2802.77 seconds
Started Jul 29 04:56:50 PM PDT 24
Finished Jul 29 05:43:33 PM PDT 24
Peak memory 2362556 kb
Host smart-d3cbe2cc-9081-4e20-a19e-7eec324b67c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3933675114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.3933675114 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_512.2211055488
Short name T295
Test name
Test status
Simulation time 50320675201 ps
CPU time 1787.84 seconds
Started Jul 29 04:56:45 PM PDT 24
Finished Jul 29 05:26:33 PM PDT 24
Peak memory 1714184 kb
Host smart-d05f09e3-63c0-4be4-ab27-bdeb95206a47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2211055488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.2211055488 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_256.3703709790
Short name T860
Test name
Test status
Simulation time 109977747152 ps
CPU time 5280.22 seconds
Started Jul 29 04:56:42 PM PDT 24
Finished Jul 29 06:24:43 PM PDT 24
Peak memory 2221572 kb
Host smart-0f8b4c6e-a10a-4041-bc43-c0314332e411
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3703709790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.3703709790 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/29.kmac_alert_test.3488458748
Short name T969
Test name
Test status
Simulation time 17443266 ps
CPU time 0.81 seconds
Started Jul 29 04:57:00 PM PDT 24
Finished Jul 29 04:57:01 PM PDT 24
Peak memory 218336 kb
Host smart-59067129-cbc8-4ed0-93b0-28286dd37eb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488458748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.3488458748 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_alert_test/latest

Test location /workspace/coverage/default/29.kmac_app.263534464
Short name T425
Test name
Test status
Simulation time 6207418661 ps
CPU time 156.08 seconds
Started Jul 29 04:56:57 PM PDT 24
Finished Jul 29 04:59:33 PM PDT 24
Peak memory 342948 kb
Host smart-fa921f5f-46a3-4ddc-bc77-894422820125
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263534464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.263534464 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/29.kmac_app/latest

Test location /workspace/coverage/default/29.kmac_burst_write.3159512480
Short name T151
Test name
Test status
Simulation time 8889903478 ps
CPU time 988.53 seconds
Started Jul 29 04:56:50 PM PDT 24
Finished Jul 29 05:13:19 PM PDT 24
Peak memory 242524 kb
Host smart-f9d7151b-8667-4db1-a1dd-a23de509f7d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159512480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.315951248
0 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_burst_write/latest

Test location /workspace/coverage/default/29.kmac_entropy_refresh.2878088267
Short name T61
Test name
Test status
Simulation time 6292743777 ps
CPU time 128.64 seconds
Started Jul 29 04:56:51 PM PDT 24
Finished Jul 29 04:59:00 PM PDT 24
Peak memory 268032 kb
Host smart-dba16150-2efb-4b7b-9ad7-97a438255523
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878088267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.2
878088267 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/29.kmac_error.279480491
Short name T159
Test name
Test status
Simulation time 57899220172 ps
CPU time 485.7 seconds
Started Jul 29 04:56:55 PM PDT 24
Finished Jul 29 05:05:01 PM PDT 24
Peak memory 574136 kb
Host smart-bec2d5ec-add7-46e6-890d-dc36b68dfd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279480491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.279480491 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_error/latest

Test location /workspace/coverage/default/29.kmac_key_error.512669561
Short name T626
Test name
Test status
Simulation time 1931362510 ps
CPU time 13.39 seconds
Started Jul 29 04:56:56 PM PDT 24
Finished Jul 29 04:57:09 PM PDT 24
Peak memory 226584 kb
Host smart-64ed886e-629a-4f28-a8b3-7b96ec972ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512669561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.512669561 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_key_error/latest

Test location /workspace/coverage/default/29.kmac_lc_escalation.3894049840
Short name T73
Test name
Test status
Simulation time 42789926 ps
CPU time 1.48 seconds
Started Jul 29 04:56:58 PM PDT 24
Finished Jul 29 04:57:00 PM PDT 24
Peak memory 226680 kb
Host smart-c6219407-7164-4b4b-af6a-a2207c8b4a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894049840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.3894049840 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/29.kmac_lc_escalation/latest

Test location /workspace/coverage/default/29.kmac_long_msg_and_output.3494979655
Short name T798
Test name
Test status
Simulation time 18980110190 ps
CPU time 2406.91 seconds
Started Jul 29 04:56:45 PM PDT 24
Finished Jul 29 05:36:52 PM PDT 24
Peak memory 1327348 kb
Host smart-eacd5c39-cc3e-46b3-baea-669a9d5fdbdc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494979655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a
nd_output.3494979655 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/29.kmac_sideload.3682047487
Short name T826
Test name
Test status
Simulation time 7778787010 ps
CPU time 100.18 seconds
Started Jul 29 04:56:47 PM PDT 24
Finished Jul 29 04:58:27 PM PDT 24
Peak memory 301920 kb
Host smart-965d11d1-21b0-4520-87c5-ddd93983e4ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682047487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.3682047487 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest

Test location /workspace/coverage/default/29.kmac_smoke.1805775357
Short name T466
Test name
Test status
Simulation time 4241549098 ps
CPU time 79.4 seconds
Started Jul 29 04:56:51 PM PDT 24
Finished Jul 29 04:58:10 PM PDT 24
Peak memory 228592 kb
Host smart-9b0d8a85-4dea-4474-9ce7-a697406be902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805775357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.1805775357 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest

Test location /workspace/coverage/default/29.kmac_stress_all.1159398725
Short name T899
Test name
Test status
Simulation time 6091788769 ps
CPU time 45.74 seconds
Started Jul 29 04:56:55 PM PDT 24
Finished Jul 29 04:57:41 PM PDT 24
Peak memory 254132 kb
Host smart-450b8a51-7499-4933-9216-d66f27807d14
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1159398725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.1159398725 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac.829947995
Short name T508
Test name
Test status
Simulation time 1429567687 ps
CPU time 6.12 seconds
Started Jul 29 04:56:56 PM PDT 24
Finished Jul 29 04:57:02 PM PDT 24
Peak memory 218744 kb
Host smart-bdeb49ff-543b-4a27-82d9-b45ab192067f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829947995 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.kmac_test_vectors_kmac.829947995 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac_xof.3433091369
Short name T447
Test name
Test status
Simulation time 802074598 ps
CPU time 6.67 seconds
Started Jul 29 04:56:57 PM PDT 24
Finished Jul 29 04:57:03 PM PDT 24
Peak memory 219720 kb
Host smart-1d426046-0b29-4fc6-9013-553c5baebfb7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433091369 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.kmac_test_vectors_kmac_xof.3433091369 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_224.2976758432
Short name T532
Test name
Test status
Simulation time 253191742269 ps
CPU time 3163.83 seconds
Started Jul 29 04:56:46 PM PDT 24
Finished Jul 29 05:49:31 PM PDT 24
Peak memory 3165348 kb
Host smart-89ce736f-a5c4-4110-9e57-45ef7853feee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2976758432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.2976758432 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_384.1004474196
Short name T884
Test name
Test status
Simulation time 116778988844 ps
CPU time 2370.05 seconds
Started Jul 29 04:56:50 PM PDT 24
Finished Jul 29 05:36:21 PM PDT 24
Peak memory 2403764 kb
Host smart-8282b0b5-5914-4f41-ac01-3ba05a8e97ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1004474196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.1004474196 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_512.2147160179
Short name T209
Test name
Test status
Simulation time 22046691239 ps
CPU time 1253.67 seconds
Started Jul 29 04:56:53 PM PDT 24
Finished Jul 29 05:17:47 PM PDT 24
Peak memory 700480 kb
Host smart-f2437dd4-27ee-4e74-8211-3ccaaa0e4c34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2147160179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.2147160179 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_256.3773506120
Short name T855
Test name
Test status
Simulation time 127457406085 ps
CPU time 5531.83 seconds
Started Jul 29 04:56:59 PM PDT 24
Finished Jul 29 06:29:12 PM PDT 24
Peak memory 2241440 kb
Host smart-fa5a42dd-8474-4db5-9a95-e07e1b16d8ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3773506120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.3773506120 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/3.kmac_alert_test.818820354
Short name T337
Test name
Test status
Simulation time 17922167 ps
CPU time 0.84 seconds
Started Jul 29 04:55:39 PM PDT 24
Finished Jul 29 04:55:40 PM PDT 24
Peak memory 218408 kb
Host smart-641dec24-192f-4d75-adf4-f80df77646b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818820354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.818820354 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/3.kmac_alert_test/latest

Test location /workspace/coverage/default/3.kmac_app.1372842370
Short name T891
Test name
Test status
Simulation time 3321314074 ps
CPU time 109.43 seconds
Started Jul 29 04:55:49 PM PDT 24
Finished Jul 29 04:57:39 PM PDT 24
Peak memory 299976 kb
Host smart-0f650c1f-448b-41e6-a074-1e15a857923c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372842370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.1372842370 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/3.kmac_app/latest

Test location /workspace/coverage/default/3.kmac_app_with_partial_data.772636890
Short name T880
Test name
Test status
Simulation time 39450718245 ps
CPU time 376.5 seconds
Started Jul 29 04:55:55 PM PDT 24
Finished Jul 29 05:02:11 PM PDT 24
Peak memory 481628 kb
Host smart-23c9eacf-8a90-43b1-9f03-8a99aeea1c03
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772636890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_part
ial_data.772636890 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/3.kmac_burst_write.2103766603
Short name T142
Test name
Test status
Simulation time 58540865133 ps
CPU time 547.6 seconds
Started Jul 29 04:55:41 PM PDT 24
Finished Jul 29 05:04:49 PM PDT 24
Peak memory 241780 kb
Host smart-2e2f6585-5e25-47f5-985b-c9ddfd3a2237
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103766603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.2103766603
+enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest

Test location /workspace/coverage/default/3.kmac_edn_timeout_error.1272320267
Short name T59
Test name
Test status
Simulation time 100670356 ps
CPU time 1.07 seconds
Started Jul 29 04:55:45 PM PDT 24
Finished Jul 29 04:55:46 PM PDT 24
Peak memory 218556 kb
Host smart-9770726a-841c-4dd6-b782-142b5f06a988
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1272320267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.1272320267 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_mode_error.488505533
Short name T424
Test name
Test status
Simulation time 139678319 ps
CPU time 0.92 seconds
Started Jul 29 04:55:49 PM PDT 24
Finished Jul 29 04:55:50 PM PDT 24
Peak memory 220424 kb
Host smart-f0f9d216-02bb-4e74-bc3d-7c901873d9de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=488505533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.488505533 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_ready_error.608216544
Short name T661
Test name
Test status
Simulation time 15870654407 ps
CPU time 50.73 seconds
Started Jul 29 04:55:49 PM PDT 24
Finished Jul 29 04:56:40 PM PDT 24
Peak memory 224336 kb
Host smart-6c597e7e-c2ee-4a4d-9ba1-254df86828c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608216544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.608216544 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_refresh.1937474893
Short name T685
Test name
Test status
Simulation time 2679205672 ps
CPU time 48.3 seconds
Started Jul 29 04:55:47 PM PDT 24
Finished Jul 29 04:56:35 PM PDT 24
Peak memory 243188 kb
Host smart-ca41e6f0-3c91-44cf-9a08-9b9dce05de4c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937474893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.19
37474893 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/3.kmac_error.4148696806
Short name T858
Test name
Test status
Simulation time 4406346881 ps
CPU time 147.48 seconds
Started Jul 29 04:55:50 PM PDT 24
Finished Jul 29 04:58:18 PM PDT 24
Peak memory 357868 kb
Host smart-9ad93cc7-99bf-4c53-8d5b-eb97f890294d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148696806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.4148696806 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_error/latest

Test location /workspace/coverage/default/3.kmac_key_error.2445031930
Short name T590
Test name
Test status
Simulation time 957219648 ps
CPU time 7.69 seconds
Started Jul 29 04:55:38 PM PDT 24
Finished Jul 29 04:55:46 PM PDT 24
Peak memory 226556 kb
Host smart-3a28818e-6916-473c-b373-c3cb05612e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445031930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.2445031930 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_key_error/latest

Test location /workspace/coverage/default/3.kmac_mubi.2047680749
Short name T50
Test name
Test status
Simulation time 9034818101 ps
CPU time 211.75 seconds
Started Jul 29 04:55:50 PM PDT 24
Finished Jul 29 04:59:22 PM PDT 24
Peak memory 296632 kb
Host smart-985ddd0b-0175-4a0e-a354-9e7d82b20f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047680749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.2047680749 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mubi/latest

Test location /workspace/coverage/default/3.kmac_sec_cm.1949546644
Short name T29
Test name
Test status
Simulation time 5461637920 ps
CPU time 88.34 seconds
Started Jul 29 04:55:46 PM PDT 24
Finished Jul 29 04:57:14 PM PDT 24
Peak memory 275956 kb
Host smart-ea0273f1-4724-4c3d-95d7-bb111fbc1b9a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949546644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.1949546644 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest

Test location /workspace/coverage/default/3.kmac_sideload.3039013124
Short name T915
Test name
Test status
Simulation time 40710535727 ps
CPU time 458.31 seconds
Started Jul 29 04:55:40 PM PDT 24
Finished Jul 29 05:03:19 PM PDT 24
Peak memory 373896 kb
Host smart-057fa37c-ad2d-4c62-985d-429cfcd9a3b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039013124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.3039013124 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_smoke.3515055060
Short name T820
Test name
Test status
Simulation time 13231414937 ps
CPU time 46.53 seconds
Started Jul 29 04:55:52 PM PDT 24
Finished Jul 29 04:56:43 PM PDT 24
Peak memory 226924 kb
Host smart-6d07192e-e2ad-498e-8e83-a1adc4a96199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515055060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.3515055060 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_smoke/latest

Test location /workspace/coverage/default/3.kmac_stress_all.1074433927
Short name T778
Test name
Test status
Simulation time 63545292598 ps
CPU time 1091 seconds
Started Jul 29 04:55:44 PM PDT 24
Finished Jul 29 05:13:55 PM PDT 24
Peak memory 603048 kb
Host smart-d6d98049-4632-4f14-994d-ccaa3b2ccc6c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1074433927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.1074433927 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.191430592
Short name T359
Test name
Test status
Simulation time 3688189633 ps
CPU time 6.15 seconds
Started Jul 29 04:55:43 PM PDT 24
Finished Jul 29 04:55:50 PM PDT 24
Peak memory 219732 kb
Host smart-25336e12-6616-4b89-b8d0-8b378d41d24d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191430592 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.kmac_test_vectors_kmac.191430592 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.1700884522
Short name T428
Test name
Test status
Simulation time 330988178 ps
CPU time 6.5 seconds
Started Jul 29 04:56:00 PM PDT 24
Finished Jul 29 04:56:07 PM PDT 24
Peak memory 219664 kb
Host smart-72a4111e-413c-48cf-8430-e594a1f753d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700884522 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.kmac_test_vectors_kmac_xof.1700884522 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.1876478738
Short name T235
Test name
Test status
Simulation time 20720742085 ps
CPU time 2135.13 seconds
Started Jul 29 04:55:45 PM PDT 24
Finished Jul 29 05:31:20 PM PDT 24
Peak memory 1175864 kb
Host smart-b7305645-2038-454c-bf7d-ce001d805c75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1876478738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.1876478738 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.3041924572
Short name T953
Test name
Test status
Simulation time 88085087929 ps
CPU time 1561.15 seconds
Started Jul 29 04:56:05 PM PDT 24
Finished Jul 29 05:22:07 PM PDT 24
Peak memory 930040 kb
Host smart-46118ce4-874a-497e-b6f0-1c1e4e5131e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3041924572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.3041924572 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.1902189179
Short name T787
Test name
Test status
Simulation time 191146371379 ps
CPU time 1687.73 seconds
Started Jul 29 04:55:49 PM PDT 24
Finished Jul 29 05:23:58 PM PDT 24
Peak memory 1676484 kb
Host smart-f38d51b3-4b2f-4636-a308-eb2007f94c83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1902189179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.1902189179 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_256.3971102714
Short name T674
Test name
Test status
Simulation time 235714832381 ps
CPU time 5151.19 seconds
Started Jul 29 04:55:45 PM PDT 24
Finished Jul 29 06:21:37 PM PDT 24
Peak memory 2190752 kb
Host smart-d43815c8-371c-46f3-9e4c-3036b412de05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3971102714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.3971102714 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/30.kmac_alert_test.3044784565
Short name T327
Test name
Test status
Simulation time 68810518 ps
CPU time 0.82 seconds
Started Jul 29 04:56:56 PM PDT 24
Finished Jul 29 04:56:56 PM PDT 24
Peak memory 218372 kb
Host smart-028e8627-82ba-45d3-bfc0-f77e721db270
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044784565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.3044784565 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_alert_test/latest

Test location /workspace/coverage/default/30.kmac_app.3378278528
Short name T523
Test name
Test status
Simulation time 510220574 ps
CPU time 6.88 seconds
Started Jul 29 04:56:55 PM PDT 24
Finished Jul 29 04:57:02 PM PDT 24
Peak memory 226936 kb
Host smart-676d1726-3c2c-40a6-8819-9f056ee8b0e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378278528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.3378278528 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest

Test location /workspace/coverage/default/30.kmac_burst_write.205152926
Short name T786
Test name
Test status
Simulation time 105573184113 ps
CPU time 1456.94 seconds
Started Jul 29 04:56:56 PM PDT 24
Finished Jul 29 05:21:13 PM PDT 24
Peak memory 263972 kb
Host smart-1b567c24-6ac1-4cce-a4d1-050e48bf5e9c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205152926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.205152926
+enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_burst_write/latest

Test location /workspace/coverage/default/30.kmac_entropy_refresh.3766587240
Short name T848
Test name
Test status
Simulation time 109302895956 ps
CPU time 307.66 seconds
Started Jul 29 04:56:59 PM PDT 24
Finished Jul 29 05:02:07 PM PDT 24
Peak memory 434208 kb
Host smart-3d5ff1c7-2b42-4449-900f-23c13fd61e87
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766587240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.3
766587240 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/30.kmac_error.1021087040
Short name T374
Test name
Test status
Simulation time 1131897104 ps
CPU time 98.26 seconds
Started Jul 29 04:56:57 PM PDT 24
Finished Jul 29 04:58:35 PM PDT 24
Peak memory 258496 kb
Host smart-a458facf-5657-4190-bc37-0ea2142a1f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021087040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.1021087040 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_error/latest

Test location /workspace/coverage/default/30.kmac_key_error.2382717101
Short name T400
Test name
Test status
Simulation time 1388473610 ps
CPU time 11.93 seconds
Started Jul 29 04:56:58 PM PDT 24
Finished Jul 29 04:57:10 PM PDT 24
Peak memory 226536 kb
Host smart-40aa4ca4-ee7b-42bc-b4fa-78f26568c066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382717101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.2382717101 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest

Test location /workspace/coverage/default/30.kmac_lc_escalation.1434004821
Short name T883
Test name
Test status
Simulation time 6579810427 ps
CPU time 23.6 seconds
Started Jul 29 04:56:55 PM PDT 24
Finished Jul 29 04:57:19 PM PDT 24
Peak memory 247444 kb
Host smart-f88933dc-1ee8-4c4a-bc33-8b917b4076ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434004821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.1434004821 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/30.kmac_lc_escalation/latest

Test location /workspace/coverage/default/30.kmac_long_msg_and_output.2060524228
Short name T647
Test name
Test status
Simulation time 1393796179 ps
CPU time 145.97 seconds
Started Jul 29 04:56:54 PM PDT 24
Finished Jul 29 04:59:20 PM PDT 24
Peak memory 292152 kb
Host smart-def65099-d3a5-4a94-97bd-7ac4694c3d8d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060524228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_a
nd_output.2060524228 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/30.kmac_sideload.907101644
Short name T699
Test name
Test status
Simulation time 16798345212 ps
CPU time 339.52 seconds
Started Jul 29 04:56:56 PM PDT 24
Finished Jul 29 05:02:36 PM PDT 24
Peak memory 347028 kb
Host smart-f2034de3-1972-4cd2-bee7-d23017f07cc4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907101644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.907101644 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest

Test location /workspace/coverage/default/30.kmac_smoke.2165234660
Short name T861
Test name
Test status
Simulation time 551610297 ps
CPU time 15.28 seconds
Started Jul 29 04:56:55 PM PDT 24
Finished Jul 29 04:57:11 PM PDT 24
Peak memory 223496 kb
Host smart-666323ac-e736-4381-a7f0-ed58123b6ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165234660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.2165234660 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest

Test location /workspace/coverage/default/30.kmac_stress_all.853953826
Short name T921
Test name
Test status
Simulation time 182087748564 ps
CPU time 1811.61 seconds
Started Jul 29 04:56:54 PM PDT 24
Finished Jul 29 05:27:06 PM PDT 24
Peak memory 1275308 kb
Host smart-1510da47-689a-4e61-bf3f-de7f73377856
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=853953826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.853953826 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac.823899790
Short name T593
Test name
Test status
Simulation time 250004509 ps
CPU time 5.66 seconds
Started Jul 29 04:56:57 PM PDT 24
Finished Jul 29 04:57:03 PM PDT 24
Peak memory 218752 kb
Host smart-904700a0-e326-4f14-86b0-bd7c132fc85a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823899790 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.kmac_test_vectors_kmac.823899790 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac_xof.812018187
Short name T56
Test name
Test status
Simulation time 1047423246 ps
CPU time 6.85 seconds
Started Jul 29 04:56:55 PM PDT 24
Finished Jul 29 04:57:02 PM PDT 24
Peak memory 220012 kb
Host smart-72c0f2af-84ea-4704-a3a5-053d4779b484
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812018187 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.kmac_test_vectors_kmac_xof.812018187 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_224.25154435
Short name T645
Test name
Test status
Simulation time 75206259381 ps
CPU time 2407.81 seconds
Started Jul 29 04:56:55 PM PDT 24
Finished Jul 29 05:37:03 PM PDT 24
Peak memory 1186596 kb
Host smart-2e5620de-3680-496c-ae90-46b843c2c115
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=25154435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.25154435 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_256.3785843392
Short name T617
Test name
Test status
Simulation time 85819683147 ps
CPU time 2132.33 seconds
Started Jul 29 04:56:57 PM PDT 24
Finished Jul 29 05:32:30 PM PDT 24
Peak memory 1122904 kb
Host smart-18d2310c-fed1-4d3b-b542-0f0028b31e11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3785843392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.3785843392 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_384.4159003031
Short name T77
Test name
Test status
Simulation time 247701069244 ps
CPU time 2343.01 seconds
Started Jul 29 04:56:57 PM PDT 24
Finished Jul 29 05:36:00 PM PDT 24
Peak memory 2365388 kb
Host smart-29bb88a5-95ac-4633-a064-f8bda5255bab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4159003031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.4159003031 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_512.228951699
Short name T821
Test name
Test status
Simulation time 35552067692 ps
CPU time 1560.45 seconds
Started Jul 29 04:56:56 PM PDT 24
Finished Jul 29 05:22:57 PM PDT 24
Peak memory 1756308 kb
Host smart-ace26238-6835-45f2-a470-68d32034a186
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=228951699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.228951699 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/31.kmac_alert_test.3491914118
Short name T512
Test name
Test status
Simulation time 21802318 ps
CPU time 0.86 seconds
Started Jul 29 04:57:08 PM PDT 24
Finished Jul 29 04:57:09 PM PDT 24
Peak memory 218380 kb
Host smart-d500e63a-b0dd-4914-b064-a0957c9973f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491914118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.3491914118 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest

Test location /workspace/coverage/default/31.kmac_app.3414313917
Short name T450
Test name
Test status
Simulation time 6247263156 ps
CPU time 398.4 seconds
Started Jul 29 04:57:01 PM PDT 24
Finished Jul 29 05:03:39 PM PDT 24
Peak memory 356140 kb
Host smart-d6ae373e-34ee-4cc3-a6f0-228d9b422b15
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414313917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.3414313917 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/31.kmac_app/latest

Test location /workspace/coverage/default/31.kmac_burst_write.2563900533
Short name T670
Test name
Test status
Simulation time 51128152118 ps
CPU time 1410.63 seconds
Started Jul 29 04:57:03 PM PDT 24
Finished Jul 29 05:20:34 PM PDT 24
Peak memory 246088 kb
Host smart-c120518e-dbf6-4dc2-bcdb-ba55900fe5f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563900533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.256390053
3 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_burst_write/latest

Test location /workspace/coverage/default/31.kmac_error.2627952412
Short name T657
Test name
Test status
Simulation time 103454451 ps
CPU time 5.15 seconds
Started Jul 29 04:57:03 PM PDT 24
Finished Jul 29 04:57:08 PM PDT 24
Peak memory 225972 kb
Host smart-711f8b99-2c7a-4f39-bdc9-d3ba053b24eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627952412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.2627952412 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest

Test location /workspace/coverage/default/31.kmac_key_error.2839880716
Short name T872
Test name
Test status
Simulation time 751851463 ps
CPU time 5.59 seconds
Started Jul 29 04:57:01 PM PDT 24
Finished Jul 29 04:57:07 PM PDT 24
Peak memory 226540 kb
Host smart-784d6f8a-d64e-4670-816b-d9c5d38f6f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839880716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.2839880716 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest

Test location /workspace/coverage/default/31.kmac_lc_escalation.806418505
Short name T11
Test name
Test status
Simulation time 43757819 ps
CPU time 1.56 seconds
Started Jul 29 04:57:02 PM PDT 24
Finished Jul 29 04:57:03 PM PDT 24
Peak memory 226848 kb
Host smart-e4ba0ece-f093-4ffd-91b8-adf654e11969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806418505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.806418505 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/31.kmac_lc_escalation/latest

Test location /workspace/coverage/default/31.kmac_long_msg_and_output.72090257
Short name T548
Test name
Test status
Simulation time 3707373183 ps
CPU time 388.17 seconds
Started Jul 29 04:56:55 PM PDT 24
Finished Jul 29 05:03:23 PM PDT 24
Peak memory 451988 kb
Host smart-a390f022-7244-465d-93e8-fe7a51190d54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72090257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_and
_output.72090257 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/31.kmac_sideload.2650429979
Short name T677
Test name
Test status
Simulation time 19133305727 ps
CPU time 185.5 seconds
Started Jul 29 04:56:57 PM PDT 24
Finished Jul 29 05:00:02 PM PDT 24
Peak memory 281900 kb
Host smart-583dfacb-0b1a-4ba3-9618-113309dd775e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650429979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.2650429979 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_sideload/latest

Test location /workspace/coverage/default/31.kmac_smoke.3360208107
Short name T564
Test name
Test status
Simulation time 436423093 ps
CPU time 12.18 seconds
Started Jul 29 04:56:54 PM PDT 24
Finished Jul 29 04:57:06 PM PDT 24
Peak memory 226808 kb
Host smart-bc6d094a-4875-4ca3-9b4b-28d6e6849063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360208107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.3360208107 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_smoke/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac.192156859
Short name T246
Test name
Test status
Simulation time 393073759 ps
CPU time 6.68 seconds
Started Jul 29 04:57:01 PM PDT 24
Finished Jul 29 04:57:07 PM PDT 24
Peak memory 218864 kb
Host smart-a02aa929-0b7c-4a2d-b2e2-e3cae1c655b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192156859 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.kmac_test_vectors_kmac.192156859 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac_xof.1456657679
Short name T445
Test name
Test status
Simulation time 420333240 ps
CPU time 6.5 seconds
Started Jul 29 04:57:00 PM PDT 24
Finished Jul 29 04:57:07 PM PDT 24
Peak memory 219756 kb
Host smart-f32d84b3-0e7e-474c-935f-0675d3c629f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456657679 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.kmac_test_vectors_kmac_xof.1456657679 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_224.1733459492
Short name T809
Test name
Test status
Simulation time 81786420678 ps
CPU time 2233.03 seconds
Started Jul 29 04:57:01 PM PDT 24
Finished Jul 29 05:34:14 PM PDT 24
Peak memory 1212288 kb
Host smart-6cb08317-6980-44dd-80e9-f18dfe5beae2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1733459492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.1733459492 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_256.4186472258
Short name T373
Test name
Test status
Simulation time 81012840365 ps
CPU time 2301.33 seconds
Started Jul 29 04:57:02 PM PDT 24
Finished Jul 29 05:35:24 PM PDT 24
Peak memory 1159184 kb
Host smart-d5117f3f-b706-46bf-b2d2-a401b3ff36da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4186472258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.4186472258 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_384.2421055638
Short name T258
Test name
Test status
Simulation time 31169441542 ps
CPU time 1564.17 seconds
Started Jul 29 04:57:01 PM PDT 24
Finished Jul 29 05:23:05 PM PDT 24
Peak memory 923264 kb
Host smart-725765f6-0e4a-4e5a-a801-43ad74925562
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2421055638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.2421055638 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_512.4136103403
Short name T688
Test name
Test status
Simulation time 45895702758 ps
CPU time 1351.15 seconds
Started Jul 29 04:57:02 PM PDT 24
Finished Jul 29 05:19:33 PM PDT 24
Peak memory 707300 kb
Host smart-280d6d10-e150-43cb-be22-94400099f5d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4136103403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.4136103403 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/32.kmac_alert_test.3441161002
Short name T911
Test name
Test status
Simulation time 26822117 ps
CPU time 0.81 seconds
Started Jul 29 04:57:08 PM PDT 24
Finished Jul 29 04:57:09 PM PDT 24
Peak memory 218396 kb
Host smart-feabd1e6-cd21-4dc8-9ac0-3c2dbc19bbba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441161002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.3441161002 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest

Test location /workspace/coverage/default/32.kmac_app.2724564024
Short name T892
Test name
Test status
Simulation time 3260501771 ps
CPU time 188.4 seconds
Started Jul 29 04:57:08 PM PDT 24
Finished Jul 29 05:00:16 PM PDT 24
Peak memory 284364 kb
Host smart-658605c2-5879-4aff-8f3b-36a2201f60c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724564024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.2724564024 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/32.kmac_app/latest

Test location /workspace/coverage/default/32.kmac_burst_write.217364777
Short name T752
Test name
Test status
Simulation time 31929542771 ps
CPU time 814.33 seconds
Started Jul 29 04:57:08 PM PDT 24
Finished Jul 29 05:10:43 PM PDT 24
Peak memory 240052 kb
Host smart-142bf4b3-ce4b-41b8-805e-e3327148277c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217364777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.217364777
+enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest

Test location /workspace/coverage/default/32.kmac_entropy_refresh.1775317668
Short name T376
Test name
Test status
Simulation time 4681870735 ps
CPU time 210.84 seconds
Started Jul 29 04:57:07 PM PDT 24
Finished Jul 29 05:00:38 PM PDT 24
Peak memory 282044 kb
Host smart-afbfcc15-5c40-4aac-b89a-8736f9e9265f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775317668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.1
775317668 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/32.kmac_error.3946558625
Short name T262
Test name
Test status
Simulation time 9500133592 ps
CPU time 60.11 seconds
Started Jul 29 04:57:08 PM PDT 24
Finished Jul 29 04:58:09 PM PDT 24
Peak memory 270480 kb
Host smart-62a11f71-dd09-4ef3-a2d2-43770e4bb858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946558625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.3946558625 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest

Test location /workspace/coverage/default/32.kmac_key_error.1337683189
Short name T725
Test name
Test status
Simulation time 1624267909 ps
CPU time 12.43 seconds
Started Jul 29 04:57:11 PM PDT 24
Finished Jul 29 04:57:24 PM PDT 24
Peak memory 226696 kb
Host smart-fd5ba25b-056a-4ddc-8bbe-3af038e5140e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337683189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.1337683189 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest

Test location /workspace/coverage/default/32.kmac_lc_escalation.4155786146
Short name T43
Test name
Test status
Simulation time 464036644 ps
CPU time 11 seconds
Started Jul 29 04:57:06 PM PDT 24
Finished Jul 29 04:57:17 PM PDT 24
Peak memory 236480 kb
Host smart-3987a79c-9342-4974-b7d1-9feb4388c78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155786146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.4155786146 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/32.kmac_lc_escalation/latest

Test location /workspace/coverage/default/32.kmac_sideload.1895165356
Short name T407
Test name
Test status
Simulation time 12221476270 ps
CPU time 466.49 seconds
Started Jul 29 04:57:08 PM PDT 24
Finished Jul 29 05:04:55 PM PDT 24
Peak memory 547100 kb
Host smart-441b4770-05db-4908-9eb9-08644b658404
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895165356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.1895165356 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest

Test location /workspace/coverage/default/32.kmac_smoke.2198383193
Short name T660
Test name
Test status
Simulation time 3849417633 ps
CPU time 68.02 seconds
Started Jul 29 04:57:05 PM PDT 24
Finished Jul 29 04:58:13 PM PDT 24
Peak memory 227816 kb
Host smart-352a95f0-c805-442d-8d3d-56dd5e2fba41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198383193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.2198383193 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest

Test location /workspace/coverage/default/32.kmac_stress_all.1762280950
Short name T112
Test name
Test status
Simulation time 97471274885 ps
CPU time 1682.08 seconds
Started Jul 29 04:57:07 PM PDT 24
Finished Jul 29 05:25:09 PM PDT 24
Peak memory 919456 kb
Host smart-0eeb474d-99dc-4129-9e06-c0d242f887f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1762280950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.1762280950 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac.3347153845
Short name T731
Test name
Test status
Simulation time 557719357 ps
CPU time 7.24 seconds
Started Jul 29 04:57:08 PM PDT 24
Finished Jul 29 04:57:16 PM PDT 24
Peak memory 219916 kb
Host smart-49459bb0-ebcd-4a34-b2b4-83e9213eb6eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347153845 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.kmac_test_vectors_kmac.3347153845 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac_xof.4089156206
Short name T739
Test name
Test status
Simulation time 1709446258 ps
CPU time 6.97 seconds
Started Jul 29 04:57:07 PM PDT 24
Finished Jul 29 04:57:14 PM PDT 24
Peak memory 219960 kb
Host smart-39f83b87-6ce2-4664-a6cb-7bb31059bdd4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089156206 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.kmac_test_vectors_kmac_xof.4089156206 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_256.2049046089
Short name T469
Test name
Test status
Simulation time 88683344220 ps
CPU time 3254.81 seconds
Started Jul 29 04:57:09 PM PDT 24
Finished Jul 29 05:51:24 PM PDT 24
Peak memory 2990144 kb
Host smart-5a069cc5-5c71-47d4-b615-4265d076968a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2049046089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.2049046089 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_384.2415048717
Short name T667
Test name
Test status
Simulation time 74052933923 ps
CPU time 2752.62 seconds
Started Jul 29 04:57:07 PM PDT 24
Finished Jul 29 05:43:00 PM PDT 24
Peak memory 2382688 kb
Host smart-823f58a7-ae54-4dd8-b586-d96a0dbab127
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2415048717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.2415048717 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_512.1071559646
Short name T186
Test name
Test status
Simulation time 43088544025 ps
CPU time 1385.19 seconds
Started Jul 29 04:57:10 PM PDT 24
Finished Jul 29 05:20:15 PM PDT 24
Peak memory 716264 kb
Host smart-7c559e5d-683a-4306-b586-69c98d2ba050
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1071559646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.1071559646 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/33.kmac_alert_test.1031478124
Short name T843
Test name
Test status
Simulation time 65740961 ps
CPU time 0.81 seconds
Started Jul 29 04:57:13 PM PDT 24
Finished Jul 29 04:57:14 PM PDT 24
Peak memory 218420 kb
Host smart-d79e5822-e051-4d9b-94a1-bcc62413a755
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031478124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.1031478124 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest

Test location /workspace/coverage/default/33.kmac_app.3384809832
Short name T285
Test name
Test status
Simulation time 8257155606 ps
CPU time 145.93 seconds
Started Jul 29 04:57:12 PM PDT 24
Finished Jul 29 04:59:38 PM PDT 24
Peak memory 269244 kb
Host smart-14ff05ae-17b4-4aad-93e7-35878d9f1161
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384809832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.3384809832 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest

Test location /workspace/coverage/default/33.kmac_burst_write.2750243978
Short name T773
Test name
Test status
Simulation time 8391046640 ps
CPU time 843.93 seconds
Started Jul 29 04:57:11 PM PDT 24
Finished Jul 29 05:11:15 PM PDT 24
Peak memory 241692 kb
Host smart-e8508e94-7fdb-4294-ada0-045e3f9b2e33
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750243978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.275024397
8 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_burst_write/latest

Test location /workspace/coverage/default/33.kmac_entropy_refresh.1849454031
Short name T527
Test name
Test status
Simulation time 28887960088 ps
CPU time 134.91 seconds
Started Jul 29 04:57:14 PM PDT 24
Finished Jul 29 04:59:29 PM PDT 24
Peak memory 316828 kb
Host smart-f2ca54fb-865b-457b-a30b-f1660a9df242
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849454031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.1
849454031 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/33.kmac_error.3319527571
Short name T846
Test name
Test status
Simulation time 36738490803 ps
CPU time 552.2 seconds
Started Jul 29 04:57:11 PM PDT 24
Finished Jul 29 05:06:23 PM PDT 24
Peak memory 623452 kb
Host smart-24332a36-58e3-4d65-b771-c8b17b275c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319527571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.3319527571 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest

Test location /workspace/coverage/default/33.kmac_key_error.48629496
Short name T574
Test name
Test status
Simulation time 1297964840 ps
CPU time 5.79 seconds
Started Jul 29 04:57:13 PM PDT 24
Finished Jul 29 04:57:19 PM PDT 24
Peak memory 226608 kb
Host smart-b435dd8e-86d3-49fa-8437-ce5a5419ad1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48629496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.48629496 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_key_error/latest

Test location /workspace/coverage/default/33.kmac_lc_escalation.1185713152
Short name T824
Test name
Test status
Simulation time 38505753 ps
CPU time 1.25 seconds
Started Jul 29 04:57:12 PM PDT 24
Finished Jul 29 04:57:14 PM PDT 24
Peak memory 226924 kb
Host smart-cda06988-d08d-487d-906a-f577f92c6937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185713152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.1185713152 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/33.kmac_lc_escalation/latest

Test location /workspace/coverage/default/33.kmac_sideload.1683426923
Short name T286
Test name
Test status
Simulation time 11062194896 ps
CPU time 386.37 seconds
Started Jul 29 04:57:07 PM PDT 24
Finished Jul 29 05:03:34 PM PDT 24
Peak memory 512492 kb
Host smart-3a3789ef-6e89-4eb3-8717-1e6ea38b20e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683426923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.1683426923 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest

Test location /workspace/coverage/default/33.kmac_smoke.1712079639
Short name T343
Test name
Test status
Simulation time 79823076 ps
CPU time 3.8 seconds
Started Jul 29 04:57:11 PM PDT 24
Finished Jul 29 04:57:15 PM PDT 24
Peak memory 226888 kb
Host smart-4193fe89-1a79-4360-8506-530eb5a228a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712079639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.1712079639 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest

Test location /workspace/coverage/default/33.kmac_stress_all.3034177588
Short name T939
Test name
Test status
Simulation time 21198858385 ps
CPU time 2309.01 seconds
Started Jul 29 04:57:13 PM PDT 24
Finished Jul 29 05:35:42 PM PDT 24
Peak memory 799508 kb
Host smart-3e9a3113-7669-4d6f-91b9-870b6eb599a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3034177588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.3034177588 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac.1390552404
Short name T340
Test name
Test status
Simulation time 96134642 ps
CPU time 5.34 seconds
Started Jul 29 04:57:14 PM PDT 24
Finished Jul 29 04:57:19 PM PDT 24
Peak memory 219724 kb
Host smart-460c8a1d-2a1f-4d7b-8e76-ff2ee9ed804d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390552404 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.kmac_test_vectors_kmac.1390552404 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac_xof.3269479029
Short name T444
Test name
Test status
Simulation time 742696134 ps
CPU time 6.75 seconds
Started Jul 29 04:57:13 PM PDT 24
Finished Jul 29 04:57:19 PM PDT 24
Peak memory 218708 kb
Host smart-ccb861da-4989-4ddd-8a9d-19c7a5132c63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269479029 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.kmac_test_vectors_kmac_xof.3269479029 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_224.3849254955
Short name T979
Test name
Test status
Simulation time 82148895414 ps
CPU time 2388.89 seconds
Started Jul 29 04:57:09 PM PDT 24
Finished Jul 29 05:36:58 PM PDT 24
Peak memory 1209516 kb
Host smart-0fd387d3-0283-48e2-9e19-81cabd72e0d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3849254955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.3849254955 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_256.2439695831
Short name T321
Test name
Test status
Simulation time 19231587105 ps
CPU time 2094.62 seconds
Started Jul 29 04:57:12 PM PDT 24
Finished Jul 29 05:32:07 PM PDT 24
Peak memory 1142372 kb
Host smart-3feb59c2-2ac0-4d4f-a944-e3a32ff96bc8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2439695831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.2439695831 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_384.3290697744
Short name T907
Test name
Test status
Simulation time 998683079669 ps
CPU time 2771.29 seconds
Started Jul 29 04:57:12 PM PDT 24
Finished Jul 29 05:43:24 PM PDT 24
Peak memory 2374636 kb
Host smart-a54d9090-2c2f-432f-b292-f102d0045003
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3290697744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.3290697744 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_512.1173019856
Short name T700
Test name
Test status
Simulation time 10618278800 ps
CPU time 1157.16 seconds
Started Jul 29 04:57:10 PM PDT 24
Finished Jul 29 05:16:28 PM PDT 24
Peak memory 692156 kb
Host smart-93464285-13b4-4a85-b416-d6bdd1242d06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1173019856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.1173019856 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_128.3582412724
Short name T414
Test name
Test status
Simulation time 432102237225 ps
CPU time 6860.75 seconds
Started Jul 29 04:57:13 PM PDT 24
Finished Jul 29 06:51:35 PM PDT 24
Peak memory 2702236 kb
Host smart-a13fb45b-7b47-4bfa-93bb-30ce548f77e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3582412724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_128.3582412724 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/34.kmac_alert_test.1049191978
Short name T472
Test name
Test status
Simulation time 22607110 ps
CPU time 0.8 seconds
Started Jul 29 04:57:15 PM PDT 24
Finished Jul 29 04:57:16 PM PDT 24
Peak memory 218400 kb
Host smart-c7c5c233-96b4-4fe6-981e-f2d2711c3539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049191978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.1049191978 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_alert_test/latest

Test location /workspace/coverage/default/34.kmac_app.3998355060
Short name T555
Test name
Test status
Simulation time 142395702530 ps
CPU time 399.33 seconds
Started Jul 29 04:57:16 PM PDT 24
Finished Jul 29 05:03:56 PM PDT 24
Peak memory 507460 kb
Host smart-847bba98-eba0-439f-8bbe-798b89aa1ef9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998355060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.3998355060 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/34.kmac_app/latest

Test location /workspace/coverage/default/34.kmac_burst_write.1206832998
Short name T349
Test name
Test status
Simulation time 36884862353 ps
CPU time 1486.42 seconds
Started Jul 29 04:57:11 PM PDT 24
Finished Jul 29 05:21:58 PM PDT 24
Peak memory 249244 kb
Host smart-7d8eea5f-2e7e-43f7-9121-77bbb3585b2f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206832998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.120683299
8 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_burst_write/latest

Test location /workspace/coverage/default/34.kmac_entropy_refresh.3701120901
Short name T309
Test name
Test status
Simulation time 571080635 ps
CPU time 14.99 seconds
Started Jul 29 04:57:15 PM PDT 24
Finished Jul 29 04:57:30 PM PDT 24
Peak memory 227712 kb
Host smart-8dc9ab74-9b5b-4f8c-a0cc-f1f1b27edfe6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701120901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.3
701120901 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/34.kmac_error.2378213196
Short name T54
Test name
Test status
Simulation time 58064335185 ps
CPU time 626.85 seconds
Started Jul 29 04:57:22 PM PDT 24
Finished Jul 29 05:07:49 PM PDT 24
Peak memory 614208 kb
Host smart-265e423d-7624-4e55-9e8c-8ae9ca4a3ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378213196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.2378213196 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_key_error.3946060622
Short name T320
Test name
Test status
Simulation time 1357207299 ps
CPU time 8.6 seconds
Started Jul 29 04:57:17 PM PDT 24
Finished Jul 29 04:57:26 PM PDT 24
Peak memory 226592 kb
Host smart-29c50095-d77f-4238-bb52-893755dfbf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946060622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.3946060622 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest

Test location /workspace/coverage/default/34.kmac_long_msg_and_output.1238617975
Short name T482
Test name
Test status
Simulation time 18275648845 ps
CPU time 731.81 seconds
Started Jul 29 04:57:13 PM PDT 24
Finished Jul 29 05:09:25 PM PDT 24
Peak memory 963536 kb
Host smart-b6b4ea28-8307-49c4-8b50-5666698e3fdd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238617975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_a
nd_output.1238617975 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/34.kmac_sideload.1989088336
Short name T380
Test name
Test status
Simulation time 71293569719 ps
CPU time 420.82 seconds
Started Jul 29 04:57:12 PM PDT 24
Finished Jul 29 05:04:13 PM PDT 24
Peak memory 538484 kb
Host smart-3cb70bcc-224a-4cf6-902b-8aa732fc18f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989088336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.1989088336 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest

Test location /workspace/coverage/default/34.kmac_smoke.3653381490
Short name T581
Test name
Test status
Simulation time 1937395223 ps
CPU time 36.92 seconds
Started Jul 29 04:57:13 PM PDT 24
Finished Jul 29 04:57:50 PM PDT 24
Peak memory 226900 kb
Host smart-c87106e0-56df-4bf4-86d5-203721e0ac33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653381490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.3653381490 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest

Test location /workspace/coverage/default/34.kmac_stress_all.650646975
Short name T403
Test name
Test status
Simulation time 18977542998 ps
CPU time 361.57 seconds
Started Jul 29 04:57:17 PM PDT 24
Finished Jul 29 05:03:19 PM PDT 24
Peak memory 316448 kb
Host smart-0645c7bd-90bb-4548-bd39-1b13c29372f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=650646975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.650646975 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac.1517957531
Short name T388
Test name
Test status
Simulation time 384637974 ps
CPU time 5.3 seconds
Started Jul 29 04:57:18 PM PDT 24
Finished Jul 29 04:57:23 PM PDT 24
Peak memory 219776 kb
Host smart-66be8a96-f569-4948-9f13-3e4e691691f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517957531 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.kmac_test_vectors_kmac.1517957531 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac_xof.898832063
Short name T411
Test name
Test status
Simulation time 904664973 ps
CPU time 7.03 seconds
Started Jul 29 04:57:16 PM PDT 24
Finished Jul 29 04:57:23 PM PDT 24
Peak memory 219672 kb
Host smart-185924ee-cecf-4d6a-a413-2bb0dac44917
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898832063 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.kmac_test_vectors_kmac_xof.898832063 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_224.1786428457
Short name T831
Test name
Test status
Simulation time 20987644220 ps
CPU time 2340.94 seconds
Started Jul 29 04:57:13 PM PDT 24
Finished Jul 29 05:36:14 PM PDT 24
Peak memory 1205276 kb
Host smart-d503e42c-8c0a-43b3-bf06-1a4c2ee6768b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1786428457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.1786428457 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_256.3159161386
Short name T618
Test name
Test status
Simulation time 20091935071 ps
CPU time 2118.37 seconds
Started Jul 29 04:57:11 PM PDT 24
Finished Jul 29 05:32:30 PM PDT 24
Peak memory 1139524 kb
Host smart-080c5a97-8e3c-4a84-8e19-8bfb7a96069f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3159161386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.3159161386 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_384.998859418
Short name T348
Test name
Test status
Simulation time 62994351688 ps
CPU time 1804.7 seconds
Started Jul 29 04:57:11 PM PDT 24
Finished Jul 29 05:27:16 PM PDT 24
Peak memory 930024 kb
Host smart-16f3c21b-a4a0-4423-aa7b-4c72f7ee24ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=998859418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.998859418 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_512.2983011458
Short name T971
Test name
Test status
Simulation time 70045406764 ps
CPU time 1593.57 seconds
Started Jul 29 04:57:17 PM PDT 24
Finished Jul 29 05:23:51 PM PDT 24
Peak memory 1729264 kb
Host smart-b4432b15-f28e-4979-8e32-8ae54e8e59b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2983011458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.2983011458 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/35.kmac_alert_test.95312695
Short name T254
Test name
Test status
Simulation time 13590847 ps
CPU time 0.83 seconds
Started Jul 29 04:57:27 PM PDT 24
Finished Jul 29 04:57:28 PM PDT 24
Peak memory 218384 kb
Host smart-2c47142a-28e1-41e3-9b48-8150b0c54393
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95312695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.95312695 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest

Test location /workspace/coverage/default/35.kmac_app.4000625109
Short name T744
Test name
Test status
Simulation time 3461687176 ps
CPU time 206.41 seconds
Started Jul 29 04:57:22 PM PDT 24
Finished Jul 29 05:00:49 PM PDT 24
Peak memory 295756 kb
Host smart-4be4ead1-8fa3-463d-a263-a141804dca41
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000625109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.4000625109 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/35.kmac_app/latest

Test location /workspace/coverage/default/35.kmac_burst_write.3689063257
Short name T277
Test name
Test status
Simulation time 80975811026 ps
CPU time 1246.11 seconds
Started Jul 29 04:57:17 PM PDT 24
Finished Jul 29 05:18:04 PM PDT 24
Peak memory 256400 kb
Host smart-89c2fa0e-0ec8-4b9f-a436-73cf50010c52
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689063257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.368906325
7 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest

Test location /workspace/coverage/default/35.kmac_entropy_refresh.604215191
Short name T662
Test name
Test status
Simulation time 7156922363 ps
CPU time 255.77 seconds
Started Jul 29 04:57:22 PM PDT 24
Finished Jul 29 05:01:38 PM PDT 24
Peak memory 300616 kb
Host smart-6a4e896e-1f66-4afa-8572-e764a6cd9969
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604215191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.60
4215191 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/35.kmac_error.3701934097
Short name T415
Test name
Test status
Simulation time 492408944 ps
CPU time 28.41 seconds
Started Jul 29 04:57:21 PM PDT 24
Finished Jul 29 04:57:49 PM PDT 24
Peak memory 243268 kb
Host smart-b6fd1a95-6587-43fc-92b8-e4805124186b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701934097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.3701934097 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_key_error.2934717443
Short name T260
Test name
Test status
Simulation time 798227407 ps
CPU time 8.11 seconds
Started Jul 29 04:57:23 PM PDT 24
Finished Jul 29 04:57:32 PM PDT 24
Peak memory 226580 kb
Host smart-492cc61c-7936-45c2-8a3f-e51ecb8e4c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934717443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.2934717443 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest

Test location /workspace/coverage/default/35.kmac_long_msg_and_output.4128691016
Short name T931
Test name
Test status
Simulation time 18437387762 ps
CPU time 1010.43 seconds
Started Jul 29 04:57:16 PM PDT 24
Finished Jul 29 05:14:07 PM PDT 24
Peak memory 741340 kb
Host smart-23f70249-036d-47f8-adda-fb2dc6c53f87
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128691016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_a
nd_output.4128691016 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/35.kmac_sideload.3912091457
Short name T339
Test name
Test status
Simulation time 156941927112 ps
CPU time 417.15 seconds
Started Jul 29 04:57:16 PM PDT 24
Finished Jul 29 05:04:14 PM PDT 24
Peak memory 540120 kb
Host smart-f3f967e5-b216-41c1-95f5-5acee404a421
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912091457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.3912091457 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest

Test location /workspace/coverage/default/35.kmac_smoke.3500306512
Short name T719
Test name
Test status
Simulation time 4343734003 ps
CPU time 47.77 seconds
Started Jul 29 04:57:17 PM PDT 24
Finished Jul 29 04:58:04 PM PDT 24
Peak memory 223788 kb
Host smart-49cbe931-af94-401e-999f-4e62417d1b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500306512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.3500306512 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest

Test location /workspace/coverage/default/35.kmac_stress_all.3018384234
Short name T49
Test name
Test status
Simulation time 26488844730 ps
CPU time 1947.04 seconds
Started Jul 29 04:57:27 PM PDT 24
Finished Jul 29 05:29:55 PM PDT 24
Peak memory 451444 kb
Host smart-887fb53c-4d92-46f5-996a-263c21b8786b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3018384234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.3018384234 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac.3483960598
Short name T930
Test name
Test status
Simulation time 4035669244 ps
CPU time 6.68 seconds
Started Jul 29 04:57:21 PM PDT 24
Finished Jul 29 04:57:28 PM PDT 24
Peak memory 219724 kb
Host smart-d80580a2-d71c-448a-9c77-3ff37290d313
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483960598 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.kmac_test_vectors_kmac.3483960598 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac_xof.3984009288
Short name T313
Test name
Test status
Simulation time 194615013 ps
CPU time 6.29 seconds
Started Jul 29 04:57:21 PM PDT 24
Finished Jul 29 04:57:28 PM PDT 24
Peak memory 219748 kb
Host smart-f7e290d3-f592-438f-8c63-a930d3b31e2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984009288 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.kmac_test_vectors_kmac_xof.3984009288 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_224.1500940279
Short name T666
Test name
Test status
Simulation time 90120157288 ps
CPU time 2317.97 seconds
Started Jul 29 04:57:22 PM PDT 24
Finished Jul 29 05:36:01 PM PDT 24
Peak memory 1207292 kb
Host smart-1e3f209f-232d-4382-9bb7-de515ee86d26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1500940279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.1500940279 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_256.1407861169
Short name T390
Test name
Test status
Simulation time 19654094235 ps
CPU time 2221.63 seconds
Started Jul 29 04:57:23 PM PDT 24
Finished Jul 29 05:34:25 PM PDT 24
Peak memory 1124188 kb
Host smart-41869e1c-b3d8-4cd8-a661-679e1040b648
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1407861169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.1407861169 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_384.2141335901
Short name T421
Test name
Test status
Simulation time 94932194522 ps
CPU time 2271.29 seconds
Started Jul 29 04:57:24 PM PDT 24
Finished Jul 29 05:35:16 PM PDT 24
Peak memory 2364820 kb
Host smart-77e4b9ef-f396-479f-a726-6b2ce2ee2297
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2141335901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.2141335901 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_512.2291509227
Short name T198
Test name
Test status
Simulation time 50577961222 ps
CPU time 1890.06 seconds
Started Jul 29 04:57:24 PM PDT 24
Finished Jul 29 05:28:54 PM PDT 24
Peak memory 1778980 kb
Host smart-5f8c79b3-7bc2-43e6-8e0a-7bdaa43f275e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2291509227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.2291509227 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/36.kmac_alert_test.1620848212
Short name T3
Test name
Test status
Simulation time 18201344 ps
CPU time 0.86 seconds
Started Jul 29 04:57:28 PM PDT 24
Finished Jul 29 04:57:29 PM PDT 24
Peak memory 218384 kb
Host smart-c40286df-85ab-45e8-9324-5b7ebf09e340
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620848212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.1620848212 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest

Test location /workspace/coverage/default/36.kmac_app.3371381232
Short name T378
Test name
Test status
Simulation time 11829093077 ps
CPU time 66.5 seconds
Started Jul 29 04:57:28 PM PDT 24
Finished Jul 29 04:58:35 PM PDT 24
Peak memory 274784 kb
Host smart-cef053a6-14ca-44a3-8b7f-7a9cf677bd8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371381232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.3371381232 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/36.kmac_app/latest

Test location /workspace/coverage/default/36.kmac_burst_write.3659650637
Short name T149
Test name
Test status
Simulation time 16632004395 ps
CPU time 193.29 seconds
Started Jul 29 04:57:26 PM PDT 24
Finished Jul 29 05:00:40 PM PDT 24
Peak memory 243320 kb
Host smart-7fbb46f0-f77f-4ba2-9c9e-1bdbec1ef02c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659650637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.365965063
7 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_burst_write/latest

Test location /workspace/coverage/default/36.kmac_entropy_refresh.2030352806
Short name T623
Test name
Test status
Simulation time 9353969995 ps
CPU time 192.96 seconds
Started Jul 29 04:57:30 PM PDT 24
Finished Jul 29 05:00:43 PM PDT 24
Peak memory 351808 kb
Host smart-851a6124-e3ce-4432-91d2-1ea460c16258
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030352806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.2
030352806 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/36.kmac_error.2181764706
Short name T353
Test name
Test status
Simulation time 3519712832 ps
CPU time 130.51 seconds
Started Jul 29 04:57:26 PM PDT 24
Finished Jul 29 04:59:37 PM PDT 24
Peak memory 321076 kb
Host smart-d50f9eee-0460-4c9d-9019-6174886e6d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181764706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.2181764706 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest

Test location /workspace/coverage/default/36.kmac_key_error.3792301252
Short name T602
Test name
Test status
Simulation time 6147227521 ps
CPU time 12.98 seconds
Started Jul 29 04:57:30 PM PDT 24
Finished Jul 29 04:57:43 PM PDT 24
Peak memory 226700 kb
Host smart-61afff52-195f-47ee-8d31-d3681be8b000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792301252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.3792301252 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_lc_escalation.933882610
Short name T881
Test name
Test status
Simulation time 55584907 ps
CPU time 1.58 seconds
Started Jul 29 04:57:28 PM PDT 24
Finished Jul 29 04:57:30 PM PDT 24
Peak memory 226716 kb
Host smart-cbdbb0bf-28d1-4fae-84fb-1080b844cad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933882610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.933882610 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/36.kmac_lc_escalation/latest

Test location /workspace/coverage/default/36.kmac_sideload.1214190887
Short name T737
Test name
Test status
Simulation time 2717391977 ps
CPU time 109.74 seconds
Started Jul 29 04:57:27 PM PDT 24
Finished Jul 29 04:59:16 PM PDT 24
Peak memory 265428 kb
Host smart-0bc0232c-5dff-49ef-a7b1-d5262973b32a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214190887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.1214190887 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_sideload/latest

Test location /workspace/coverage/default/36.kmac_smoke.2782855863
Short name T827
Test name
Test status
Simulation time 235229259 ps
CPU time 3.16 seconds
Started Jul 29 04:57:27 PM PDT 24
Finished Jul 29 04:57:30 PM PDT 24
Peak memory 221428 kb
Host smart-192392e5-6587-4ead-ae50-bd7263b2d79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782855863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.2782855863 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_smoke/latest

Test location /workspace/coverage/default/36.kmac_stress_all.2257086599
Short name T460
Test name
Test status
Simulation time 64640996742 ps
CPU time 1101.78 seconds
Started Jul 29 04:57:27 PM PDT 24
Finished Jul 29 05:15:49 PM PDT 24
Peak memory 1280512 kb
Host smart-355f4d70-8af2-45f2-8a38-f3ec7c4d7649
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2257086599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.2257086599 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac.2811768730
Short name T336
Test name
Test status
Simulation time 107509843 ps
CPU time 6.92 seconds
Started Jul 29 04:57:27 PM PDT 24
Finished Jul 29 04:57:34 PM PDT 24
Peak memory 219684 kb
Host smart-84ef23a7-9138-4a89-8c3c-41f8c9fb5119
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811768730 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.kmac_test_vectors_kmac.2811768730 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac_xof.4118251948
Short name T232
Test name
Test status
Simulation time 423259015 ps
CPU time 6.2 seconds
Started Jul 29 04:57:30 PM PDT 24
Finished Jul 29 04:57:36 PM PDT 24
Peak memory 218860 kb
Host smart-15dc0af7-6801-477f-bba6-6401b081a5a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118251948 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.kmac_test_vectors_kmac_xof.4118251948 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_256.1003326519
Short name T134
Test name
Test status
Simulation time 80657378614 ps
CPU time 2241.89 seconds
Started Jul 29 04:57:27 PM PDT 24
Finished Jul 29 05:34:50 PM PDT 24
Peak memory 1153792 kb
Host smart-b198c7bc-1512-44b8-a1a5-07a15ede5972
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1003326519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.1003326519 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_384.3378186298
Short name T514
Test name
Test status
Simulation time 280388584393 ps
CPU time 2699.08 seconds
Started Jul 29 04:57:28 PM PDT 24
Finished Jul 29 05:42:28 PM PDT 24
Peak memory 2344872 kb
Host smart-fa92bf98-92fa-4a13-853d-01e300467dba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3378186298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.3378186298 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_512.1069882911
Short name T765
Test name
Test status
Simulation time 86017482640 ps
CPU time 1587.2 seconds
Started Jul 29 04:57:28 PM PDT 24
Finished Jul 29 05:23:56 PM PDT 24
Peak memory 1735596 kb
Host smart-22e07aa5-0896-471a-bee1-ce60eb1fca81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1069882911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.1069882911 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_256.1324317442
Short name T849
Test name
Test status
Simulation time 134754295820 ps
CPU time 5358.41 seconds
Started Jul 29 04:57:29 PM PDT 24
Finished Jul 29 06:26:47 PM PDT 24
Peak memory 2253656 kb
Host smart-1faa5e03-451d-43fe-82d4-0c858a7af4ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1324317442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.1324317442 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/37.kmac_alert_test.334426252
Short name T250
Test name
Test status
Simulation time 41140217 ps
CPU time 0.83 seconds
Started Jul 29 04:57:36 PM PDT 24
Finished Jul 29 04:57:36 PM PDT 24
Peak memory 218428 kb
Host smart-da22e52c-db26-4105-8c61-d916750f3fb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334426252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.334426252 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/37.kmac_alert_test/latest

Test location /workspace/coverage/default/37.kmac_app.2732581273
Short name T310
Test name
Test status
Simulation time 12136455055 ps
CPU time 167.31 seconds
Started Jul 29 04:57:38 PM PDT 24
Finished Jul 29 05:00:25 PM PDT 24
Peak memory 278952 kb
Host smart-12e929de-5a1a-4521-a99e-28fa5b458485
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732581273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.2732581273 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest

Test location /workspace/coverage/default/37.kmac_burst_write.1370126155
Short name T905
Test name
Test status
Simulation time 13044768005 ps
CPU time 1405.17 seconds
Started Jul 29 04:57:33 PM PDT 24
Finished Jul 29 05:20:59 PM PDT 24
Peak memory 246520 kb
Host smart-44303b60-879e-4f8a-a7bb-3c1b2868acf0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370126155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.137012615
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_burst_write/latest

Test location /workspace/coverage/default/37.kmac_entropy_refresh.1216064944
Short name T63
Test name
Test status
Simulation time 66263818523 ps
CPU time 296.92 seconds
Started Jul 29 04:57:37 PM PDT 24
Finished Jul 29 05:02:34 PM PDT 24
Peak memory 428140 kb
Host smart-096f189d-5a17-4168-a46b-6f833965b471
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216064944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.1
216064944 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/37.kmac_error.512999277
Short name T315
Test name
Test status
Simulation time 1043678614 ps
CPU time 72.92 seconds
Started Jul 29 04:57:39 PM PDT 24
Finished Jul 29 04:58:52 PM PDT 24
Peak memory 251872 kb
Host smart-faac5380-f6a2-467d-88d3-25132eacc6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512999277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.512999277 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest

Test location /workspace/coverage/default/37.kmac_key_error.739641035
Short name T695
Test name
Test status
Simulation time 1076881460 ps
CPU time 4.68 seconds
Started Jul 29 04:57:40 PM PDT 24
Finished Jul 29 04:57:44 PM PDT 24
Peak memory 226592 kb
Host smart-ad9ecd4a-82c8-4f1d-85a8-cc975dc9b20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739641035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.739641035 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest

Test location /workspace/coverage/default/37.kmac_lc_escalation.954881517
Short name T479
Test name
Test status
Simulation time 49101363 ps
CPU time 1.26 seconds
Started Jul 29 04:57:38 PM PDT 24
Finished Jul 29 04:57:40 PM PDT 24
Peak memory 226752 kb
Host smart-5fe27532-32f3-4145-b0f3-987402f25c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954881517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.954881517 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/37.kmac_lc_escalation/latest

Test location /workspace/coverage/default/37.kmac_long_msg_and_output.1202341085
Short name T810
Test name
Test status
Simulation time 24463005229 ps
CPU time 3256.52 seconds
Started Jul 29 04:57:32 PM PDT 24
Finished Jul 29 05:51:49 PM PDT 24
Peak memory 1691160 kb
Host smart-9de192d3-a7f4-4ada-abb6-bb1b2d6fd2d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202341085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_a
nd_output.1202341085 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/37.kmac_sideload.2358453354
Short name T434
Test name
Test status
Simulation time 41565938565 ps
CPU time 655.47 seconds
Started Jul 29 04:57:34 PM PDT 24
Finished Jul 29 05:08:29 PM PDT 24
Peak memory 649736 kb
Host smart-457e7a6e-36f9-49cd-9fe7-cee8fff1e013
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358453354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.2358453354 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest

Test location /workspace/coverage/default/37.kmac_smoke.3037366802
Short name T278
Test name
Test status
Simulation time 2575382621 ps
CPU time 39.48 seconds
Started Jul 29 04:57:31 PM PDT 24
Finished Jul 29 04:58:11 PM PDT 24
Peak memory 226880 kb
Host smart-7491ace7-e41c-4126-bf28-b2a4870a4c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037366802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.3037366802 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest

Test location /workspace/coverage/default/37.kmac_stress_all.2286681638
Short name T889
Test name
Test status
Simulation time 4034509697 ps
CPU time 324.31 seconds
Started Jul 29 04:57:38 PM PDT 24
Finished Jul 29 05:03:03 PM PDT 24
Peak memory 292184 kb
Host smart-234ebb78-574a-4fe6-a515-1d908262d9fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2286681638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.2286681638 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac.3433440194
Short name T646
Test name
Test status
Simulation time 515863903 ps
CPU time 6.94 seconds
Started Jul 29 04:57:37 PM PDT 24
Finished Jul 29 04:57:44 PM PDT 24
Peak memory 219680 kb
Host smart-ed5b37c6-94c9-446f-a3a3-53614e2dd30d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433440194 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.kmac_test_vectors_kmac.3433440194 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac_xof.3049983650
Short name T767
Test name
Test status
Simulation time 367339746 ps
CPU time 6.78 seconds
Started Jul 29 04:57:37 PM PDT 24
Finished Jul 29 04:57:43 PM PDT 24
Peak memory 218964 kb
Host smart-96174086-76c4-4b7c-adb0-ffa420d252c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049983650 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.kmac_test_vectors_kmac_xof.3049983650 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_224.1177944369
Short name T671
Test name
Test status
Simulation time 22825752482 ps
CPU time 2204.09 seconds
Started Jul 29 04:57:33 PM PDT 24
Finished Jul 29 05:34:17 PM PDT 24
Peak memory 1206648 kb
Host smart-223fd24a-dea8-4c0d-bc28-16597cf0ef84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1177944369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.1177944369 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_256.1686720093
Short name T944
Test name
Test status
Simulation time 434741342865 ps
CPU time 3382.96 seconds
Started Jul 29 04:57:34 PM PDT 24
Finished Jul 29 05:53:57 PM PDT 24
Peak memory 3007600 kb
Host smart-71155361-1590-42ca-9bd9-a70d77e77c8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1686720093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.1686720093 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_384.2957530438
Short name T240
Test name
Test status
Simulation time 14911520607 ps
CPU time 1627.65 seconds
Started Jul 29 04:57:33 PM PDT 24
Finished Jul 29 05:24:41 PM PDT 24
Peak memory 913076 kb
Host smart-5c0c1e9e-08b2-4669-b26e-a77a2251bb90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2957530438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.2957530438 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_512.4194607281
Short name T401
Test name
Test status
Simulation time 49895740149 ps
CPU time 1217.96 seconds
Started Jul 29 04:57:32 PM PDT 24
Finished Jul 29 05:17:51 PM PDT 24
Peak memory 714752 kb
Host smart-9ae0f619-491a-45d1-96e7-35edbcc88d61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4194607281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.4194607281 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/38.kmac_alert_test.36153858
Short name T735
Test name
Test status
Simulation time 15127584 ps
CPU time 0.84 seconds
Started Jul 29 04:57:46 PM PDT 24
Finished Jul 29 04:57:47 PM PDT 24
Peak memory 218440 kb
Host smart-1cfd7d10-4a20-405f-9737-af545c78cd02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36153858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.36153858 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest

Test location /workspace/coverage/default/38.kmac_app.2439174266
Short name T16
Test name
Test status
Simulation time 11440817800 ps
CPU time 172.43 seconds
Started Jul 29 04:57:41 PM PDT 24
Finished Jul 29 05:00:33 PM PDT 24
Peak memory 343564 kb
Host smart-c39f6623-9ab8-4c3e-b088-d28e3629bff9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439174266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.2439174266 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/38.kmac_app/latest

Test location /workspace/coverage/default/38.kmac_burst_write.1273410844
Short name T31
Test name
Test status
Simulation time 19959804670 ps
CPU time 1179.67 seconds
Started Jul 29 04:57:40 PM PDT 24
Finished Jul 29 05:17:20 PM PDT 24
Peak memory 255452 kb
Host smart-9fe7fe25-9976-4767-ae4f-59c4ffe0b5a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273410844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.127341084
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_burst_write/latest

Test location /workspace/coverage/default/38.kmac_entropy_refresh.1082656336
Short name T280
Test name
Test status
Simulation time 19397332668 ps
CPU time 251.62 seconds
Started Jul 29 04:57:41 PM PDT 24
Finished Jul 29 05:01:53 PM PDT 24
Peak memory 302660 kb
Host smart-039b3411-3966-4680-8213-6026afdf24d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082656336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.1
082656336 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/38.kmac_error.2929445955
Short name T333
Test name
Test status
Simulation time 24474466481 ps
CPU time 116.67 seconds
Started Jul 29 04:57:43 PM PDT 24
Finished Jul 29 04:59:40 PM PDT 24
Peak memory 284340 kb
Host smart-8828a3cd-76c9-4a72-9ea1-0ca3fc153206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929445955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.2929445955 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest

Test location /workspace/coverage/default/38.kmac_key_error.3147058219
Short name T652
Test name
Test status
Simulation time 546378741 ps
CPU time 2.98 seconds
Started Jul 29 04:57:41 PM PDT 24
Finished Jul 29 04:57:44 PM PDT 24
Peak memory 226644 kb
Host smart-9879c6b1-2331-432f-9ad4-9e72e0019a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147058219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.3147058219 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest

Test location /workspace/coverage/default/38.kmac_lc_escalation.600366368
Short name T71
Test name
Test status
Simulation time 43481793 ps
CPU time 1.72 seconds
Started Jul 29 04:57:40 PM PDT 24
Finished Jul 29 04:57:42 PM PDT 24
Peak memory 226692 kb
Host smart-aa433002-ad45-4776-8a8c-bf10672b92fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600366368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.600366368 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/38.kmac_lc_escalation/latest

Test location /workspace/coverage/default/38.kmac_sideload.3164433474
Short name T207
Test name
Test status
Simulation time 9994878435 ps
CPU time 211.66 seconds
Started Jul 29 04:57:39 PM PDT 24
Finished Jul 29 05:01:11 PM PDT 24
Peak memory 291252 kb
Host smart-72ccc1c8-416d-4e5e-b07d-94bdd39dce23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164433474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.3164433474 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_sideload/latest

Test location /workspace/coverage/default/38.kmac_smoke.1487878617
Short name T567
Test name
Test status
Simulation time 3050706600 ps
CPU time 79.23 seconds
Started Jul 29 04:57:36 PM PDT 24
Finished Jul 29 04:58:56 PM PDT 24
Peak memory 227264 kb
Host smart-6486540d-557b-45aa-a410-fbc52ea52545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487878617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.1487878617 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest

Test location /workspace/coverage/default/38.kmac_stress_all.588479928
Short name T173
Test name
Test status
Simulation time 2839128188 ps
CPU time 61.97 seconds
Started Jul 29 04:57:41 PM PDT 24
Finished Jul 29 04:58:43 PM PDT 24
Peak memory 254548 kb
Host smart-ec7d45a8-f30d-4669-9f34-9440a065a0d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=588479928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.588479928 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac.4077565853
Short name T481
Test name
Test status
Simulation time 944321267 ps
CPU time 6.39 seconds
Started Jul 29 04:57:41 PM PDT 24
Finished Jul 29 04:57:48 PM PDT 24
Peak memory 219860 kb
Host smart-08e9c751-41f4-453a-b14e-6383ac7f04fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077565853 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.kmac_test_vectors_kmac.4077565853 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac_xof.1322826894
Short name T764
Test name
Test status
Simulation time 1117601276 ps
CPU time 6.92 seconds
Started Jul 29 04:57:41 PM PDT 24
Finished Jul 29 04:57:48 PM PDT 24
Peak memory 218912 kb
Host smart-ae88c43c-52a1-477a-9129-3f1a033f3d47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322826894 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.kmac_test_vectors_kmac_xof.1322826894 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_256.1171332073
Short name T771
Test name
Test status
Simulation time 199548779610 ps
CPU time 3109.18 seconds
Started Jul 29 04:57:42 PM PDT 24
Finished Jul 29 05:49:32 PM PDT 24
Peak memory 3056864 kb
Host smart-107ec3a8-fdcd-484d-8d90-8fae803a2d11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1171332073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.1171332073 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_384.766609223
Short name T239
Test name
Test status
Simulation time 191460884346 ps
CPU time 2377.4 seconds
Started Jul 29 04:57:41 PM PDT 24
Finished Jul 29 05:37:19 PM PDT 24
Peak memory 2407520 kb
Host smart-ce88e198-281f-4ece-a417-79355cdb879c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=766609223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.766609223 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_512.1439906571
Short name T549
Test name
Test status
Simulation time 49013505458 ps
CPU time 1772.22 seconds
Started Jul 29 04:57:41 PM PDT 24
Finished Jul 29 05:27:13 PM PDT 24
Peak memory 1718668 kb
Host smart-91ae34a9-ad21-43eb-b997-763bd8de89ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1439906571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.1439906571 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/39.kmac_alert_test.1120730907
Short name T430
Test name
Test status
Simulation time 53614360 ps
CPU time 0.86 seconds
Started Jul 29 04:57:53 PM PDT 24
Finished Jul 29 04:57:54 PM PDT 24
Peak memory 218704 kb
Host smart-19c49ebf-0d2d-4d88-9ad2-608663834b85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120730907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.1120730907 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest

Test location /workspace/coverage/default/39.kmac_app.3447961973
Short name T542
Test name
Test status
Simulation time 7341757547 ps
CPU time 314.13 seconds
Started Jul 29 04:57:51 PM PDT 24
Finished Jul 29 05:03:05 PM PDT 24
Peak memory 313300 kb
Host smart-d2df5c76-3252-46ca-964b-19267153af26
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447961973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.3447961973 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest

Test location /workspace/coverage/default/39.kmac_burst_write.1618628632
Short name T150
Test name
Test status
Simulation time 20038285718 ps
CPU time 735.76 seconds
Started Jul 29 04:57:47 PM PDT 24
Finished Jul 29 05:10:03 PM PDT 24
Peak memory 238120 kb
Host smart-43757436-8c19-4441-bd4b-86206216f9fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618628632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.161862863
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_burst_write/latest

Test location /workspace/coverage/default/39.kmac_entropy_refresh.3235234584
Short name T788
Test name
Test status
Simulation time 16508800843 ps
CPU time 91.73 seconds
Started Jul 29 04:57:53 PM PDT 24
Finished Jul 29 04:59:25 PM PDT 24
Peak memory 300660 kb
Host smart-d388adfd-cdbe-44d5-a5cb-c6a5e7d4ebe6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235234584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.3
235234584 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/39.kmac_error.2852982091
Short name T573
Test name
Test status
Simulation time 57420494166 ps
CPU time 493.87 seconds
Started Jul 29 04:57:53 PM PDT 24
Finished Jul 29 05:06:08 PM PDT 24
Peak memory 593800 kb
Host smart-333b8ffb-d412-4112-b064-68b3b24b6fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852982091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.2852982091 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_error/latest

Test location /workspace/coverage/default/39.kmac_key_error.104816976
Short name T784
Test name
Test status
Simulation time 17230096524 ps
CPU time 9.21 seconds
Started Jul 29 04:57:53 PM PDT 24
Finished Jul 29 04:58:03 PM PDT 24
Peak memory 226668 kb
Host smart-7d6d2e5c-65c2-4a81-ab70-cd051b3f3608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104816976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.104816976 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest

Test location /workspace/coverage/default/39.kmac_long_msg_and_output.2054825618
Short name T330
Test name
Test status
Simulation time 8539233991 ps
CPU time 849.26 seconds
Started Jul 29 04:57:46 PM PDT 24
Finished Jul 29 05:11:56 PM PDT 24
Peak memory 641928 kb
Host smart-553e25a1-4a8b-40b6-8bb4-7305b18205ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054825618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_a
nd_output.2054825618 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/39.kmac_sideload.3754719121
Short name T379
Test name
Test status
Simulation time 75781235893 ps
CPU time 235.19 seconds
Started Jul 29 04:57:47 PM PDT 24
Finished Jul 29 05:01:42 PM PDT 24
Peak memory 381884 kb
Host smart-88bafbaf-53ac-4349-82b7-08903471b183
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754719121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.3754719121 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest

Test location /workspace/coverage/default/39.kmac_smoke.240258320
Short name T795
Test name
Test status
Simulation time 3507455988 ps
CPU time 87.1 seconds
Started Jul 29 04:57:48 PM PDT 24
Finished Jul 29 04:59:15 PM PDT 24
Peak memory 228292 kb
Host smart-0e96a18d-1681-4818-b160-7fac52fe68e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240258320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.240258320 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest

Test location /workspace/coverage/default/39.kmac_stress_all.4149328048
Short name T172
Test name
Test status
Simulation time 115497778455 ps
CPU time 1762.2 seconds
Started Jul 29 04:57:52 PM PDT 24
Finished Jul 29 05:27:14 PM PDT 24
Peak memory 1108828 kb
Host smart-fd9fe0af-dba3-43d2-8f76-77b95c3af0e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4149328048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.4149328048 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac.372785636
Short name T816
Test name
Test status
Simulation time 355839736 ps
CPU time 6.05 seconds
Started Jul 29 04:57:53 PM PDT 24
Finished Jul 29 04:58:00 PM PDT 24
Peak memory 219696 kb
Host smart-6a33c876-e8e3-4e14-8de0-df8015ad1b4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372785636 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.kmac_test_vectors_kmac.372785636 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac_xof.2173730524
Short name T423
Test name
Test status
Simulation time 949235900 ps
CPU time 6.29 seconds
Started Jul 29 04:57:53 PM PDT 24
Finished Jul 29 04:58:00 PM PDT 24
Peak memory 219692 kb
Host smart-bedfb306-00e9-4d37-8775-02d27b67ca58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173730524 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.kmac_test_vectors_kmac_xof.2173730524 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_224.1544348771
Short name T575
Test name
Test status
Simulation time 65359082042 ps
CPU time 3082.21 seconds
Started Jul 29 04:57:45 PM PDT 24
Finished Jul 29 05:49:08 PM PDT 24
Peak memory 3162000 kb
Host smart-f60dc8de-fb8c-4586-abc0-eb829def4349
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1544348771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.1544348771 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_256.2954472273
Short name T534
Test name
Test status
Simulation time 249363512397 ps
CPU time 3145.84 seconds
Started Jul 29 04:57:45 PM PDT 24
Finished Jul 29 05:50:11 PM PDT 24
Peak memory 2959004 kb
Host smart-4d2b084c-1ab7-4167-94cf-6822ef3c554f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2954472273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.2954472273 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_384.759966150
Short name T636
Test name
Test status
Simulation time 29591082594 ps
CPU time 1775.79 seconds
Started Jul 29 04:57:54 PM PDT 24
Finished Jul 29 05:27:31 PM PDT 24
Peak memory 917856 kb
Host smart-34a1bbec-987f-42d9-96e3-5e41515bdb7f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=759966150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.759966150 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_512.2636324472
Short name T399
Test name
Test status
Simulation time 34036772334 ps
CPU time 1622.95 seconds
Started Jul 29 04:57:52 PM PDT 24
Finished Jul 29 05:24:55 PM PDT 24
Peak memory 1716484 kb
Host smart-3d8e3319-487f-4d13-a7d9-61606573cd5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2636324472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.2636324472 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_128.4269333711
Short name T261
Test name
Test status
Simulation time 61841818358 ps
CPU time 6074.68 seconds
Started Jul 29 04:57:50 PM PDT 24
Finished Jul 29 06:39:06 PM PDT 24
Peak memory 2659536 kb
Host smart-28445465-f0a9-48b6-a005-2f2ba48f1488
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4269333711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_128.4269333711 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_256.806352042
Short name T292
Test name
Test status
Simulation time 105970600920 ps
CPU time 5092.24 seconds
Started Jul 29 04:57:51 PM PDT 24
Finished Jul 29 06:22:44 PM PDT 24
Peak memory 2227436 kb
Host smart-a220202a-6d3c-4537-a380-f2dcd355c1f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=806352042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.806352042 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/4.kmac_alert_test.533444698
Short name T925
Test name
Test status
Simulation time 47225201 ps
CPU time 0.8 seconds
Started Jul 29 04:55:49 PM PDT 24
Finished Jul 29 04:55:50 PM PDT 24
Peak memory 218392 kb
Host smart-8f071196-dfcc-47f2-a9e7-69adea795073
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533444698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.533444698 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/4.kmac_alert_test/latest

Test location /workspace/coverage/default/4.kmac_app.498006199
Short name T551
Test name
Test status
Simulation time 18300763947 ps
CPU time 300.57 seconds
Started Jul 29 04:55:55 PM PDT 24
Finished Jul 29 05:00:55 PM PDT 24
Peak memory 420020 kb
Host smart-db7cb24e-95a3-4156-94b1-769c3147a88d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498006199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.498006199 +enable_masking=1
+sw_key_masked=0
Directory /workspace/4.kmac_app/latest

Test location /workspace/coverage/default/4.kmac_app_with_partial_data.1330391985
Short name T345
Test name
Test status
Simulation time 5853643958 ps
CPU time 117.49 seconds
Started Jul 29 04:55:55 PM PDT 24
Finished Jul 29 04:57:57 PM PDT 24
Peak memory 303152 kb
Host smart-241645fe-3538-4fe4-a04e-eb578ad4e943
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330391985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_par
tial_data.1330391985 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/4.kmac_burst_write.3910846085
Short name T553
Test name
Test status
Simulation time 12385583385 ps
CPU time 801.6 seconds
Started Jul 29 04:55:51 PM PDT 24
Finished Jul 29 05:09:13 PM PDT 24
Peak memory 246460 kb
Host smart-11f49beb-ae6c-428e-99fc-41970e55d694
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910846085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.3910846085
+enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest

Test location /workspace/coverage/default/4.kmac_edn_timeout_error.3564292327
Short name T431
Test name
Test status
Simulation time 11050593130 ps
CPU time 50.34 seconds
Started Jul 29 04:55:45 PM PDT 24
Finished Jul 29 04:56:36 PM PDT 24
Peak memory 228480 kb
Host smart-b8c3ce41-d2ae-42ad-9fbe-76813f65ff21
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3564292327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.3564292327 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_mode_error.492715751
Short name T68
Test name
Test status
Simulation time 51178700 ps
CPU time 1.04 seconds
Started Jul 29 04:55:58 PM PDT 24
Finished Jul 29 04:55:59 PM PDT 24
Peak memory 218512 kb
Host smart-ccc5fdf3-bbc9-4818-9394-163b64d75019
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=492715751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.492715751 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_ready_error.658351247
Short name T893
Test name
Test status
Simulation time 708013812 ps
CPU time 14.25 seconds
Started Jul 29 04:55:42 PM PDT 24
Finished Jul 29 04:55:56 PM PDT 24
Peak memory 226812 kb
Host smart-79dc0502-44b1-4e8b-83f1-8f8658eef262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658351247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.658351247 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_refresh.1939378878
Short name T630
Test name
Test status
Simulation time 8142486828 ps
CPU time 116.12 seconds
Started Jul 29 04:55:48 PM PDT 24
Finished Jul 29 04:57:44 PM PDT 24
Peak memory 265108 kb
Host smart-b65082d3-cfa1-48ca-8ce3-2b9583d7ae0d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939378878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.19
39378878 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/4.kmac_error.2487556513
Short name T351
Test name
Test status
Simulation time 53533309487 ps
CPU time 390.88 seconds
Started Jul 29 04:56:05 PM PDT 24
Finished Jul 29 05:02:36 PM PDT 24
Peak memory 544016 kb
Host smart-5713d10c-cc4c-49d3-b702-2911bc2f2dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487556513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.2487556513 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_error/latest

Test location /workspace/coverage/default/4.kmac_key_error.2774867181
Short name T489
Test name
Test status
Simulation time 4856181904 ps
CPU time 9.94 seconds
Started Jul 29 04:55:46 PM PDT 24
Finished Jul 29 04:55:56 PM PDT 24
Peak memory 226648 kb
Host smart-4d9a27cd-719d-4add-85c1-8cbd5843a58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774867181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.2774867181 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_key_error/latest

Test location /workspace/coverage/default/4.kmac_lc_escalation.1626892246
Short name T615
Test name
Test status
Simulation time 135905131 ps
CPU time 1.32 seconds
Started Jul 29 04:55:43 PM PDT 24
Finished Jul 29 04:55:44 PM PDT 24
Peak memory 226724 kb
Host smart-f18c4196-35d4-45b0-a3d8-2e232d345265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626892246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.1626892246 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/4.kmac_lc_escalation/latest

Test location /workspace/coverage/default/4.kmac_long_msg_and_output.3583127444
Short name T933
Test name
Test status
Simulation time 2487985709 ps
CPU time 262.35 seconds
Started Jul 29 04:55:49 PM PDT 24
Finished Jul 29 05:00:12 PM PDT 24
Peak memory 373524 kb
Host smart-ef673db5-7562-4c2f-9b71-ff421350a00a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583127444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_an
d_output.3583127444 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/4.kmac_mubi.836841210
Short name T110
Test name
Test status
Simulation time 6532372326 ps
CPU time 122.75 seconds
Started Jul 29 04:55:48 PM PDT 24
Finished Jul 29 04:57:51 PM PDT 24
Peak memory 260132 kb
Host smart-8f85feba-7816-461e-aa3b-880b66aed509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836841210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.836841210 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mubi/latest

Test location /workspace/coverage/default/4.kmac_sec_cm.3837854760
Short name T103
Test name
Test status
Simulation time 8647167851 ps
CPU time 129.3 seconds
Started Jul 29 04:56:22 PM PDT 24
Finished Jul 29 04:58:32 PM PDT 24
Peak memory 307688 kb
Host smart-aa06abe0-6e4d-4a02-aae3-06caaebe3a04
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837854760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.3837854760 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest

Test location /workspace/coverage/default/4.kmac_sideload.912224358
Short name T506
Test name
Test status
Simulation time 861981641 ps
CPU time 70.65 seconds
Started Jul 29 04:55:37 PM PDT 24
Finished Jul 29 04:56:47 PM PDT 24
Peak memory 247232 kb
Host smart-12a337c0-7430-4186-b0c4-f816ff7b6475
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912224358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.912224358 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest

Test location /workspace/coverage/default/4.kmac_smoke.1099749965
Short name T815
Test name
Test status
Simulation time 1845852742 ps
CPU time 37.29 seconds
Started Jul 29 04:55:53 PM PDT 24
Finished Jul 29 04:56:30 PM PDT 24
Peak memory 226852 kb
Host smart-5a783513-d637-4303-97a7-538852978cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099749965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.1099749965 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest

Test location /workspace/coverage/default/4.kmac_stress_all.2428848712
Short name T734
Test name
Test status
Simulation time 10703350241 ps
CPU time 382.87 seconds
Started Jul 29 04:55:54 PM PDT 24
Finished Jul 29 05:02:17 PM PDT 24
Peak memory 598100 kb
Host smart-370ab944-54f0-4bbd-8435-99e4fe7d313a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2428848712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.2428848712 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac.2885662270
Short name T396
Test name
Test status
Simulation time 464971648 ps
CPU time 5.22 seconds
Started Jul 29 04:55:42 PM PDT 24
Finished Jul 29 04:55:47 PM PDT 24
Peak memory 218840 kb
Host smart-90165c30-49cb-4669-a659-18e104ceff32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885662270 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.kmac_test_vectors_kmac.2885662270 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.4157543748
Short name T543
Test name
Test status
Simulation time 935583962 ps
CPU time 6.66 seconds
Started Jul 29 04:55:58 PM PDT 24
Finished Jul 29 04:56:05 PM PDT 24
Peak memory 219664 kb
Host smart-2540214a-5d0e-421c-a7c9-8aa601986759
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157543748 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.kmac_test_vectors_kmac_xof.4157543748 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_256.2502054611
Short name T458
Test name
Test status
Simulation time 65356016089 ps
CPU time 3262.11 seconds
Started Jul 29 04:55:49 PM PDT 24
Finished Jul 29 05:50:12 PM PDT 24
Peak memory 3163996 kb
Host smart-f7bb06e9-26bc-4f56-8501-02c5b50dc106
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2502054611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.2502054611 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.2671479270
Short name T819
Test name
Test status
Simulation time 96456941465 ps
CPU time 2388.51 seconds
Started Jul 29 04:55:43 PM PDT 24
Finished Jul 29 05:35:32 PM PDT 24
Peak memory 2419852 kb
Host smart-9fdf0e48-bf9a-4722-87f9-36d3bb599db9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2671479270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.2671479270 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.2081714506
Short name T297
Test name
Test status
Simulation time 98456425530 ps
CPU time 1810.07 seconds
Started Jul 29 04:55:55 PM PDT 24
Finished Jul 29 05:26:06 PM PDT 24
Peak memory 1757532 kb
Host smart-592f159c-490a-42b0-a218-ae2025f7a804
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2081714506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.2081714506 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/40.kmac_alert_test.1808925581
Short name T247
Test name
Test status
Simulation time 23023079 ps
CPU time 0.82 seconds
Started Jul 29 04:58:02 PM PDT 24
Finished Jul 29 04:58:03 PM PDT 24
Peak memory 218404 kb
Host smart-7abfb5d0-016b-4909-bce5-531619acf08b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808925581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.1808925581 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest

Test location /workspace/coverage/default/40.kmac_app.1984672468
Short name T620
Test name
Test status
Simulation time 1998854682 ps
CPU time 151.09 seconds
Started Jul 29 04:57:56 PM PDT 24
Finished Jul 29 05:00:27 PM PDT 24
Peak memory 267612 kb
Host smart-e3dbe857-a5c7-4e60-b788-9fec3b99ee23
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984672468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.1984672468 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/40.kmac_app/latest

Test location /workspace/coverage/default/40.kmac_burst_write.3403351026
Short name T857
Test name
Test status
Simulation time 8240670281 ps
CPU time 390.98 seconds
Started Jul 29 04:57:54 PM PDT 24
Finished Jul 29 05:04:25 PM PDT 24
Peak memory 237856 kb
Host smart-d6a9fc02-c72f-4bf1-8ae8-9a662ced42a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403351026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.340335102
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest

Test location /workspace/coverage/default/40.kmac_entropy_refresh.1701083671
Short name T828
Test name
Test status
Simulation time 18890900474 ps
CPU time 279.3 seconds
Started Jul 29 04:57:59 PM PDT 24
Finished Jul 29 05:02:39 PM PDT 24
Peak memory 415068 kb
Host smart-7cd8f85a-fb08-466d-87c6-6e0571b29452
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701083671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.1
701083671 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/40.kmac_error.2145254947
Short name T841
Test name
Test status
Simulation time 40795730667 ps
CPU time 399.16 seconds
Started Jul 29 04:57:59 PM PDT 24
Finished Jul 29 05:04:39 PM PDT 24
Peak memory 362532 kb
Host smart-22d68ca0-f930-477e-991e-8ea13b6fcd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145254947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.2145254947 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest

Test location /workspace/coverage/default/40.kmac_key_error.4281750536
Short name T682
Test name
Test status
Simulation time 928668988 ps
CPU time 2.55 seconds
Started Jul 29 04:58:01 PM PDT 24
Finished Jul 29 04:58:03 PM PDT 24
Peak memory 226616 kb
Host smart-839f92cf-6085-4d2f-b7ab-e18a57a21395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281750536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.4281750536 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_key_error/latest

Test location /workspace/coverage/default/40.kmac_lc_escalation.3029852132
Short name T522
Test name
Test status
Simulation time 141048996 ps
CPU time 1.49 seconds
Started Jul 29 04:58:03 PM PDT 24
Finished Jul 29 04:58:04 PM PDT 24
Peak memory 226836 kb
Host smart-584c27f8-0761-4ab3-9472-af4326fef473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029852132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.3029852132 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/40.kmac_lc_escalation/latest

Test location /workspace/coverage/default/40.kmac_sideload.1025339002
Short name T723
Test name
Test status
Simulation time 6600678872 ps
CPU time 189.07 seconds
Started Jul 29 04:57:51 PM PDT 24
Finished Jul 29 05:01:00 PM PDT 24
Peak memory 359024 kb
Host smart-fd7bb6a0-fb15-4aa1-89a5-8facf37d6019
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025339002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.1025339002 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest

Test location /workspace/coverage/default/40.kmac_smoke.3329839079
Short name T913
Test name
Test status
Simulation time 1000076577 ps
CPU time 22.29 seconds
Started Jul 29 04:57:52 PM PDT 24
Finished Jul 29 04:58:15 PM PDT 24
Peak memory 226828 kb
Host smart-aadb341e-3025-45f8-b87c-17a6f40bba1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329839079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.3329839079 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest

Test location /workspace/coverage/default/40.kmac_stress_all.1826376951
Short name T558
Test name
Test status
Simulation time 2922083528 ps
CPU time 118.85 seconds
Started Jul 29 04:58:03 PM PDT 24
Finished Jul 29 05:00:02 PM PDT 24
Peak memory 269912 kb
Host smart-ee6d9717-a047-406a-9ab5-a94963bdcc27
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1826376951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.1826376951 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac.814961967
Short name T196
Test name
Test status
Simulation time 96757444 ps
CPU time 5.72 seconds
Started Jul 29 04:57:56 PM PDT 24
Finished Jul 29 04:58:02 PM PDT 24
Peak memory 218752 kb
Host smart-9720618e-29bc-4f12-9366-2a96eaf3bd53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814961967 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.kmac_test_vectors_kmac.814961967 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac_xof.1453842962
Short name T949
Test name
Test status
Simulation time 834885921 ps
CPU time 6.37 seconds
Started Jul 29 04:57:57 PM PDT 24
Finished Jul 29 04:58:04 PM PDT 24
Peak memory 219976 kb
Host smart-e817d186-4ebf-4aa4-80fa-92ca6448ac53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453842962 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.kmac_test_vectors_kmac_xof.1453842962 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_224.67779408
Short name T968
Test name
Test status
Simulation time 68570737672 ps
CPU time 3416.63 seconds
Started Jul 29 04:57:57 PM PDT 24
Finished Jul 29 05:54:54 PM PDT 24
Peak memory 3283216 kb
Host smart-c60dd8cc-37ea-4840-ba52-fcb8201e8776
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=67779408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.67779408 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_384.3843708359
Short name T291
Test name
Test status
Simulation time 301491446870 ps
CPU time 2724.2 seconds
Started Jul 29 04:57:55 PM PDT 24
Finished Jul 29 05:43:19 PM PDT 24
Peak memory 2457160 kb
Host smart-dac84915-b459-4b0e-84d1-50b8b8c6800f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3843708359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.3843708359 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_512.3900026044
Short name T818
Test name
Test status
Simulation time 77658438545 ps
CPU time 1318.2 seconds
Started Jul 29 04:57:56 PM PDT 24
Finished Jul 29 05:19:55 PM PDT 24
Peak memory 723368 kb
Host smart-91c1aac4-ea61-462d-a5ff-f6c59179c156
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3900026044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.3900026044 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_128.4220901903
Short name T833
Test name
Test status
Simulation time 139363537921 ps
CPU time 6524.37 seconds
Started Jul 29 04:57:56 PM PDT 24
Finished Jul 29 06:46:42 PM PDT 24
Peak memory 2643812 kb
Host smart-1919c1b3-786e-4384-a64c-c3bb52655421
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4220901903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.4220901903 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/41.kmac_alert_test.2473545124
Short name T304
Test name
Test status
Simulation time 16728564 ps
CPU time 0.87 seconds
Started Jul 29 04:58:09 PM PDT 24
Finished Jul 29 04:58:10 PM PDT 24
Peak memory 218412 kb
Host smart-a1010736-7843-4271-92d3-69ead2929aa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473545124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.2473545124 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest

Test location /workspace/coverage/default/41.kmac_app.2643160353
Short name T90
Test name
Test status
Simulation time 9196895733 ps
CPU time 298.64 seconds
Started Jul 29 04:58:05 PM PDT 24
Finished Jul 29 05:03:03 PM PDT 24
Peak memory 433648 kb
Host smart-c0ea6899-98dc-4917-a07c-328700c605e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643160353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.2643160353 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest

Test location /workspace/coverage/default/41.kmac_burst_write.2964006841
Short name T856
Test name
Test status
Simulation time 116450723855 ps
CPU time 1288.34 seconds
Started Jul 29 04:58:03 PM PDT 24
Finished Jul 29 05:19:32 PM PDT 24
Peak memory 258740 kb
Host smart-a67dcb84-22cf-42e1-8a94-e2e1e9fb9503
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964006841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.296400684
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest

Test location /workspace/coverage/default/41.kmac_entropy_refresh.3206142624
Short name T490
Test name
Test status
Simulation time 18931441977 ps
CPU time 198.13 seconds
Started Jul 29 04:58:05 PM PDT 24
Finished Jul 29 05:01:23 PM PDT 24
Peak memory 277232 kb
Host smart-979d77ad-461c-42db-b32b-da4e48bfbb36
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206142624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.3
206142624 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/41.kmac_error.3378751672
Short name T552
Test name
Test status
Simulation time 17254035891 ps
CPU time 268.55 seconds
Started Jul 29 04:58:10 PM PDT 24
Finished Jul 29 05:02:39 PM PDT 24
Peak memory 430712 kb
Host smart-7bf74369-29cd-4aeb-997e-50f0649b9822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378751672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.3378751672 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_error/latest

Test location /workspace/coverage/default/41.kmac_key_error.580598401
Short name T99
Test name
Test status
Simulation time 518308529 ps
CPU time 4.39 seconds
Started Jul 29 04:58:06 PM PDT 24
Finished Jul 29 04:58:11 PM PDT 24
Peak memory 226500 kb
Host smart-c225e7f3-a20d-4eb1-8fca-82fe642fa649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580598401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.580598401 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest

Test location /workspace/coverage/default/41.kmac_lc_escalation.886098857
Short name T323
Test name
Test status
Simulation time 80957889 ps
CPU time 1.47 seconds
Started Jul 29 04:58:06 PM PDT 24
Finished Jul 29 04:58:08 PM PDT 24
Peak memory 224332 kb
Host smart-3f3918cc-efa6-4d27-a7cc-d4d8e75637d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886098857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.886098857 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/41.kmac_lc_escalation/latest

Test location /workspace/coverage/default/41.kmac_sideload.2971620817
Short name T15
Test name
Test status
Simulation time 694923809 ps
CPU time 13.34 seconds
Started Jul 29 04:58:04 PM PDT 24
Finished Jul 29 04:58:17 PM PDT 24
Peak memory 224728 kb
Host smart-5c043cf7-def8-4d8c-8c32-7368ac16fef4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971620817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.2971620817 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest

Test location /workspace/coverage/default/41.kmac_smoke.1067208021
Short name T707
Test name
Test status
Simulation time 368926566 ps
CPU time 5.22 seconds
Started Jul 29 04:58:04 PM PDT 24
Finished Jul 29 04:58:09 PM PDT 24
Peak memory 221500 kb
Host smart-0a2c9137-3c01-4fcf-8bc3-94285ad393cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067208021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.1067208021 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest

Test location /workspace/coverage/default/41.kmac_stress_all.1387458417
Short name T64
Test name
Test status
Simulation time 184193553295 ps
CPU time 1706.07 seconds
Started Jul 29 04:58:07 PM PDT 24
Finished Jul 29 05:26:34 PM PDT 24
Peak memory 1366024 kb
Host smart-cf4dae62-068a-42a1-9594-597196e783ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1387458417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.1387458417 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac.106715781
Short name T653
Test name
Test status
Simulation time 4621659913 ps
CPU time 6.81 seconds
Started Jul 29 04:58:06 PM PDT 24
Finished Jul 29 04:58:13 PM PDT 24
Peak memory 218884 kb
Host smart-57bd9e91-1536-4850-9832-5d5e9f897a96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106715781 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.kmac_test_vectors_kmac.106715781 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac_xof.3799873234
Short name T243
Test name
Test status
Simulation time 514941449 ps
CPU time 6.89 seconds
Started Jul 29 04:58:07 PM PDT 24
Finished Jul 29 04:58:14 PM PDT 24
Peak memory 220152 kb
Host smart-2272f0bb-ac67-46b2-bb8d-d28cba5bc968
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799873234 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.kmac_test_vectors_kmac_xof.3799873234 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_256.2359617484
Short name T794
Test name
Test status
Simulation time 371788296588 ps
CPU time 3507.17 seconds
Started Jul 29 04:58:07 PM PDT 24
Finished Jul 29 05:56:35 PM PDT 24
Peak memory 2989140 kb
Host smart-9dd9beb1-1705-4093-b748-0310b95f33e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2359617484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.2359617484 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_384.2220165307
Short name T102
Test name
Test status
Simulation time 14982598060 ps
CPU time 1759.32 seconds
Started Jul 29 04:58:07 PM PDT 24
Finished Jul 29 05:27:27 PM PDT 24
Peak memory 932200 kb
Host smart-735a0508-d817-4564-9ec7-af923ff006dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2220165307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.2220165307 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_512.2341176447
Short name T557
Test name
Test status
Simulation time 68916242609 ps
CPU time 1574.81 seconds
Started Jul 29 04:58:07 PM PDT 24
Finished Jul 29 05:24:22 PM PDT 24
Peak memory 1715320 kb
Host smart-0e851566-a23b-4e2d-bfaa-ed952f5188a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2341176447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.2341176447 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_256.1655537422
Short name T943
Test name
Test status
Simulation time 56639025667 ps
CPU time 5320.89 seconds
Started Jul 29 04:58:05 PM PDT 24
Finished Jul 29 06:26:47 PM PDT 24
Peak memory 2213008 kb
Host smart-5eec9a00-0e3b-4a9f-8063-a59929069beb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1655537422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.1655537422 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/42.kmac_alert_test.1088649933
Short name T839
Test name
Test status
Simulation time 14245891 ps
CPU time 0.81 seconds
Started Jul 29 04:58:15 PM PDT 24
Finished Jul 29 04:58:16 PM PDT 24
Peak memory 218420 kb
Host smart-af430330-ea99-4deb-a622-9521c1bebb53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088649933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.1088649933 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest

Test location /workspace/coverage/default/42.kmac_app.1112047633
Short name T876
Test name
Test status
Simulation time 14012791916 ps
CPU time 211.03 seconds
Started Jul 29 04:58:09 PM PDT 24
Finished Jul 29 05:01:40 PM PDT 24
Peak memory 376580 kb
Host smart-7a6f7fad-61dc-4cea-b647-c7a759cf24d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112047633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.1112047633 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest

Test location /workspace/coverage/default/42.kmac_burst_write.1391175349
Short name T717
Test name
Test status
Simulation time 23603982501 ps
CPU time 602 seconds
Started Jul 29 04:58:10 PM PDT 24
Finished Jul 29 05:08:12 PM PDT 24
Peak memory 238520 kb
Host smart-671463b6-8995-4322-b427-deb534fb1a23
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391175349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.139117534
9 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_burst_write/latest

Test location /workspace/coverage/default/42.kmac_entropy_refresh.558608172
Short name T308
Test name
Test status
Simulation time 8280717297 ps
CPU time 175.27 seconds
Started Jul 29 04:58:13 PM PDT 24
Finished Jul 29 05:01:08 PM PDT 24
Peak memory 281648 kb
Host smart-0f91768b-d207-41d0-a572-50b13adb0c32
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558608172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.55
8608172 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/42.kmac_error.4247340946
Short name T709
Test name
Test status
Simulation time 11992432631 ps
CPU time 485.89 seconds
Started Jul 29 04:58:16 PM PDT 24
Finished Jul 29 05:06:22 PM PDT 24
Peak memory 397540 kb
Host smart-68377f8d-de62-46fc-be3b-9c7c4e909780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247340946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.4247340946 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest

Test location /workspace/coverage/default/42.kmac_key_error.1415555744
Short name T716
Test name
Test status
Simulation time 1363456198 ps
CPU time 10.33 seconds
Started Jul 29 04:58:15 PM PDT 24
Finished Jul 29 04:58:25 PM PDT 24
Peak memory 226696 kb
Host smart-b47ef98d-16a3-4862-a126-062c47fb9214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415555744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.1415555744 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_key_error/latest

Test location /workspace/coverage/default/42.kmac_lc_escalation.2169042124
Short name T51
Test name
Test status
Simulation time 60354083 ps
CPU time 1.58 seconds
Started Jul 29 04:58:15 PM PDT 24
Finished Jul 29 04:58:16 PM PDT 24
Peak memory 226832 kb
Host smart-6b709188-6e37-4105-a7ca-dbabe27305b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169042124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.2169042124 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/42.kmac_lc_escalation/latest

Test location /workspace/coverage/default/42.kmac_long_msg_and_output.3331150130
Short name T832
Test name
Test status
Simulation time 20745403007 ps
CPU time 990.42 seconds
Started Jul 29 04:58:07 PM PDT 24
Finished Jul 29 05:14:38 PM PDT 24
Peak memory 1143492 kb
Host smart-cab4884f-726a-4665-b09b-b947230c2231
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331150130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_a
nd_output.3331150130 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/42.kmac_sideload.2019283178
Short name T328
Test name
Test status
Simulation time 108542281 ps
CPU time 9.08 seconds
Started Jul 29 04:58:05 PM PDT 24
Finished Jul 29 04:58:14 PM PDT 24
Peak memory 226796 kb
Host smart-68c7af88-ebe2-47f8-b65a-a7cf3fcc4b57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019283178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.2019283178 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest

Test location /workspace/coverage/default/42.kmac_smoke.2865130566
Short name T611
Test name
Test status
Simulation time 16352635667 ps
CPU time 89.59 seconds
Started Jul 29 04:58:10 PM PDT 24
Finished Jul 29 04:59:39 PM PDT 24
Peak memory 226704 kb
Host smart-6ff703d2-928d-4307-93d4-f0ee9816d7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865130566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.2865130566 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest

Test location /workspace/coverage/default/42.kmac_stress_all.3276360336
Short name T314
Test name
Test status
Simulation time 4122380420 ps
CPU time 173.8 seconds
Started Jul 29 04:58:15 PM PDT 24
Finished Jul 29 05:01:09 PM PDT 24
Peak memory 287220 kb
Host smart-1c6c2038-176a-4e59-8cde-d3a32789a1c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3276360336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.3276360336 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac.3413879298
Short name T950
Test name
Test status
Simulation time 201458625 ps
CPU time 5.46 seconds
Started Jul 29 04:58:09 PM PDT 24
Finished Jul 29 04:58:15 PM PDT 24
Peak memory 218800 kb
Host smart-d1f9058e-8510-4f6d-adc9-084dd502aaad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413879298 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.kmac_test_vectors_kmac.3413879298 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac_xof.1202435365
Short name T317
Test name
Test status
Simulation time 201578920 ps
CPU time 6.84 seconds
Started Jul 29 04:58:10 PM PDT 24
Finished Jul 29 04:58:17 PM PDT 24
Peak memory 219720 kb
Host smart-02d32e8d-b527-4199-91ef-27c8123c0753
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202435365 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.kmac_test_vectors_kmac_xof.1202435365 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_224.2080181986
Short name T628
Test name
Test status
Simulation time 65856786030 ps
CPU time 3353.33 seconds
Started Jul 29 04:58:09 PM PDT 24
Finished Jul 29 05:54:03 PM PDT 24
Peak memory 3201768 kb
Host smart-f1861c15-3080-46a3-86e6-0c1f68a8d250
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2080181986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.2080181986 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_256.1587953551
Short name T202
Test name
Test status
Simulation time 873069507326 ps
CPU time 3232.74 seconds
Started Jul 29 04:58:09 PM PDT 24
Finished Jul 29 05:52:02 PM PDT 24
Peak memory 3029364 kb
Host smart-21fbb881-9104-493f-9c0e-602a176e8d8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1587953551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.1587953551 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_384.1551250750
Short name T761
Test name
Test status
Simulation time 449845166700 ps
CPU time 2616.24 seconds
Started Jul 29 04:58:11 PM PDT 24
Finished Jul 29 05:41:48 PM PDT 24
Peak memory 2378372 kb
Host smart-8870b16e-55f9-4bd3-9143-193e71579d06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1551250750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.1551250750 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_512.212526886
Short name T696
Test name
Test status
Simulation time 53308858965 ps
CPU time 1823.5 seconds
Started Jul 29 04:58:10 PM PDT 24
Finished Jul 29 05:28:34 PM PDT 24
Peak memory 1724380 kb
Host smart-9c667e2b-7c09-4fc5-a23b-1b10c13e29da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=212526886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.212526886 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_128.3797994173
Short name T371
Test name
Test status
Simulation time 123752613874 ps
CPU time 6764.6 seconds
Started Jul 29 04:58:09 PM PDT 24
Finished Jul 29 06:50:54 PM PDT 24
Peak memory 2682628 kb
Host smart-e8d198ba-404c-4b74-a4bd-b03104bebea1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3797994173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_128.3797994173 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_256.774814926
Short name T419
Test name
Test status
Simulation time 62832995344 ps
CPU time 4871.2 seconds
Started Jul 29 04:58:10 PM PDT 24
Finished Jul 29 06:19:22 PM PDT 24
Peak memory 2210136 kb
Host smart-b3aa8cd5-9216-44c8-bb63-2a9b92cdad34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=774814926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.774814926 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/43.kmac_alert_test.3249287356
Short name T687
Test name
Test status
Simulation time 15605418 ps
CPU time 0.82 seconds
Started Jul 29 04:58:24 PM PDT 24
Finished Jul 29 04:58:25 PM PDT 24
Peak memory 218416 kb
Host smart-2f53dfc2-dd7d-4de8-905b-9846ba68cbec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249287356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.3249287356 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest

Test location /workspace/coverage/default/43.kmac_app.2344952446
Short name T216
Test name
Test status
Simulation time 50286420414 ps
CPU time 291.35 seconds
Started Jul 29 04:58:24 PM PDT 24
Finished Jul 29 05:03:15 PM PDT 24
Peak memory 308556 kb
Host smart-a09fe409-5e6b-474b-9ced-cc6d8ca54358
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344952446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.2344952446 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/43.kmac_app/latest

Test location /workspace/coverage/default/43.kmac_burst_write.488463514
Short name T836
Test name
Test status
Simulation time 119891881773 ps
CPU time 1573.18 seconds
Started Jul 29 04:58:20 PM PDT 24
Finished Jul 29 05:24:34 PM PDT 24
Peak memory 247676 kb
Host smart-de859f24-328e-4b6a-bb1e-0cbaca7dd285
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488463514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.488463514
+enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest

Test location /workspace/coverage/default/43.kmac_entropy_refresh.555246702
Short name T384
Test name
Test status
Simulation time 23054847697 ps
CPU time 83.76 seconds
Started Jul 29 04:58:24 PM PDT 24
Finished Jul 29 04:59:48 PM PDT 24
Peak memory 249608 kb
Host smart-b42ee352-ec4e-4b4e-a6e2-9dbc8383b902
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555246702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.55
5246702 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/43.kmac_error.135657634
Short name T301
Test name
Test status
Simulation time 1010691995 ps
CPU time 82.36 seconds
Started Jul 29 04:58:24 PM PDT 24
Finished Jul 29 04:59:47 PM PDT 24
Peak memory 259772 kb
Host smart-8f55b8d5-545f-4ec4-b23b-895ff33386b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135657634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.135657634 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest

Test location /workspace/coverage/default/43.kmac_key_error.2497099007
Short name T96
Test name
Test status
Simulation time 1783141643 ps
CPU time 8.09 seconds
Started Jul 29 04:58:24 PM PDT 24
Finished Jul 29 04:58:33 PM PDT 24
Peak memory 226612 kb
Host smart-4b5d9a34-aae4-4c06-91f5-1550bc533242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497099007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.2497099007 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_key_error/latest

Test location /workspace/coverage/default/43.kmac_lc_escalation.1644229592
Short name T23
Test name
Test status
Simulation time 109057621 ps
CPU time 1.32 seconds
Started Jul 29 04:58:24 PM PDT 24
Finished Jul 29 04:58:26 PM PDT 24
Peak memory 226712 kb
Host smart-274b6c30-1e0d-40bc-91e4-0e5623458db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644229592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.1644229592 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/43.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_long_msg_and_output.11201370
Short name T132
Test name
Test status
Simulation time 11422693530 ps
CPU time 1323.19 seconds
Started Jul 29 04:58:20 PM PDT 24
Finished Jul 29 05:20:23 PM PDT 24
Peak memory 870496 kb
Host smart-4c508485-5041-48b7-a042-506b1f0cc1f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11201370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_and
_output.11201370 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/43.kmac_sideload.74358362
Short name T601
Test name
Test status
Simulation time 25930616129 ps
CPU time 374.87 seconds
Started Jul 29 04:58:19 PM PDT 24
Finished Jul 29 05:04:34 PM PDT 24
Peak memory 509112 kb
Host smart-f8206551-aec1-442c-a968-e93768a1f929
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74358362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.74358362 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest

Test location /workspace/coverage/default/43.kmac_smoke.2036746168
Short name T812
Test name
Test status
Simulation time 441998418 ps
CPU time 10.64 seconds
Started Jul 29 04:58:15 PM PDT 24
Finished Jul 29 04:58:26 PM PDT 24
Peak memory 222752 kb
Host smart-78d762a9-818e-4fe8-a62f-254cca3c0ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036746168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.2036746168 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_smoke/latest

Test location /workspace/coverage/default/43.kmac_stress_all.1572203618
Short name T634
Test name
Test status
Simulation time 268553510682 ps
CPU time 1229.36 seconds
Started Jul 29 04:58:25 PM PDT 24
Finished Jul 29 05:18:54 PM PDT 24
Peak memory 676772 kb
Host smart-108ffddf-effb-4990-af43-bd77d6a3d596
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1572203618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.1572203618 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac.1366640475
Short name T357
Test name
Test status
Simulation time 2824361822 ps
CPU time 6.17 seconds
Started Jul 29 04:58:24 PM PDT 24
Finished Jul 29 04:58:31 PM PDT 24
Peak memory 219816 kb
Host smart-2f409ccd-40db-4d60-b710-6c6022404291
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366640475 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.kmac_test_vectors_kmac.1366640475 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac_xof.3230940694
Short name T963
Test name
Test status
Simulation time 397178455 ps
CPU time 5.94 seconds
Started Jul 29 04:58:24 PM PDT 24
Finished Jul 29 04:58:30 PM PDT 24
Peak memory 219716 kb
Host smart-d706044a-c823-4599-bca9-4973ea8cf73c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230940694 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.kmac_test_vectors_kmac_xof.3230940694 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_224.1136515074
Short name T503
Test name
Test status
Simulation time 21016744706 ps
CPU time 2431.7 seconds
Started Jul 29 04:58:20 PM PDT 24
Finished Jul 29 05:38:52 PM PDT 24
Peak memory 1203588 kb
Host smart-0b5f0117-1e63-4e60-9a04-c97ee9957397
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1136515074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.1136515074 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_256.3403156046
Short name T329
Test name
Test status
Simulation time 41758160368 ps
CPU time 2055.87 seconds
Started Jul 29 04:58:20 PM PDT 24
Finished Jul 29 05:32:36 PM PDT 24
Peak memory 1171768 kb
Host smart-66eb89da-4888-4d2c-a086-b96bb7be4ec1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3403156046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.3403156046 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_384.922068220
Short name T318
Test name
Test status
Simulation time 55749146434 ps
CPU time 1606.51 seconds
Started Jul 29 04:58:19 PM PDT 24
Finished Jul 29 05:25:06 PM PDT 24
Peak memory 901356 kb
Host smart-5b7b59ea-b34c-4e6b-9c63-a6a710dfd387
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=922068220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.922068220 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_512.1812628596
Short name T874
Test name
Test status
Simulation time 70883432279 ps
CPU time 1351.95 seconds
Started Jul 29 04:58:19 PM PDT 24
Finished Jul 29 05:20:51 PM PDT 24
Peak memory 712600 kb
Host smart-31062605-2c41-469a-b2ab-d9ec617c18a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1812628596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.1812628596 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_128.828471932
Short name T236
Test name
Test status
Simulation time 109549417774 ps
CPU time 6806.5 seconds
Started Jul 29 04:58:17 PM PDT 24
Finished Jul 29 06:51:44 PM PDT 24
Peak memory 2705380 kb
Host smart-b568cc2b-e403-4986-8c4d-ba8934f77608
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=828471932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.828471932 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_256.1027071696
Short name T191
Test name
Test status
Simulation time 58139650908 ps
CPU time 5368.26 seconds
Started Jul 29 04:58:24 PM PDT 24
Finished Jul 29 06:27:53 PM PDT 24
Peak memory 2222700 kb
Host smart-ada88eba-75f6-490f-835e-265289fa3030
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1027071696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.1027071696 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/44.kmac_alert_test.1153678344
Short name T393
Test name
Test status
Simulation time 14481580 ps
CPU time 0.85 seconds
Started Jul 29 04:58:43 PM PDT 24
Finished Jul 29 04:58:44 PM PDT 24
Peak memory 218432 kb
Host smart-38baa20b-cc7f-4be4-9e76-9f0764a18a92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153678344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.1153678344 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest

Test location /workspace/coverage/default/44.kmac_app.3229940015
Short name T669
Test name
Test status
Simulation time 5966960506 ps
CPU time 303.49 seconds
Started Jul 29 04:58:34 PM PDT 24
Finished Jul 29 05:03:38 PM PDT 24
Peak memory 319376 kb
Host smart-681fda52-2c8f-4f4f-9da8-7441672e391e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229940015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.3229940015 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest

Test location /workspace/coverage/default/44.kmac_burst_write.315480379
Short name T480
Test name
Test status
Simulation time 62609755199 ps
CPU time 1336.79 seconds
Started Jul 29 04:58:31 PM PDT 24
Finished Jul 29 05:20:48 PM PDT 24
Peak memory 259772 kb
Host smart-a2a0c27c-c617-4198-b7eb-def1e4aec516
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315480379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.315480379
+enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_burst_write/latest

Test location /workspace/coverage/default/44.kmac_entropy_refresh.199984849
Short name T525
Test name
Test status
Simulation time 24313787290 ps
CPU time 153.66 seconds
Started Jul 29 04:58:37 PM PDT 24
Finished Jul 29 05:01:11 PM PDT 24
Peak memory 313460 kb
Host smart-e06be69f-0b31-4568-aa5b-544a853f213b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199984849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.19
9984849 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/44.kmac_error.295556055
Short name T19
Test name
Test status
Simulation time 5167341221 ps
CPU time 456.11 seconds
Started Jul 29 04:58:43 PM PDT 24
Finished Jul 29 05:06:19 PM PDT 24
Peak memory 382388 kb
Host smart-28c8440d-ba4f-41a7-92c1-b00da45fffba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295556055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.295556055 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest

Test location /workspace/coverage/default/44.kmac_key_error.2506022012
Short name T781
Test name
Test status
Simulation time 6454452863 ps
CPU time 4.84 seconds
Started Jul 29 04:58:36 PM PDT 24
Finished Jul 29 04:58:41 PM PDT 24
Peak memory 226736 kb
Host smart-884a6ece-1cb1-4eb9-b7d2-8710d00c49d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506022012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.2506022012 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_key_error/latest

Test location /workspace/coverage/default/44.kmac_lc_escalation.2783081007
Short name T959
Test name
Test status
Simulation time 94661972 ps
CPU time 1.38 seconds
Started Jul 29 04:58:38 PM PDT 24
Finished Jul 29 04:58:39 PM PDT 24
Peak memory 226916 kb
Host smart-f7f7f570-5e59-4c9c-8d59-407fd866dbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783081007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.2783081007 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/44.kmac_lc_escalation/latest

Test location /workspace/coverage/default/44.kmac_sideload.930795931
Short name T443
Test name
Test status
Simulation time 3991107077 ps
CPU time 137.44 seconds
Started Jul 29 04:58:30 PM PDT 24
Finished Jul 29 05:00:48 PM PDT 24
Peak memory 333912 kb
Host smart-b30ab16c-df04-43dc-a29c-d61ff77efd87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930795931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.930795931 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_sideload/latest

Test location /workspace/coverage/default/44.kmac_smoke.773857417
Short name T259
Test name
Test status
Simulation time 3189834079 ps
CPU time 36.71 seconds
Started Jul 29 04:58:29 PM PDT 24
Finished Jul 29 04:59:06 PM PDT 24
Peak memory 226992 kb
Host smart-12449d29-156c-41bc-b427-97dcba75f972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773857417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.773857417 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_smoke/latest

Test location /workspace/coverage/default/44.kmac_stress_all.1643909165
Short name T7
Test name
Test status
Simulation time 8896288906 ps
CPU time 830.26 seconds
Started Jul 29 04:58:37 PM PDT 24
Finished Jul 29 05:12:27 PM PDT 24
Peak memory 525460 kb
Host smart-f627c025-700b-40c6-836b-d9ac579c9429
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1643909165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.1643909165 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_stress_all/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac.2449429988
Short name T903
Test name
Test status
Simulation time 243021373 ps
CPU time 7.27 seconds
Started Jul 29 04:58:33 PM PDT 24
Finished Jul 29 04:58:41 PM PDT 24
Peak memory 219936 kb
Host smart-22d97c17-595a-4760-913a-e68bc3bd224d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449429988 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.kmac_test_vectors_kmac.2449429988 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac_xof.766577678
Short name T422
Test name
Test status
Simulation time 400464660 ps
CPU time 5.95 seconds
Started Jul 29 04:58:32 PM PDT 24
Finished Jul 29 04:58:38 PM PDT 24
Peak memory 218808 kb
Host smart-49700ed0-4321-415c-ae9c-58ba0b0e2fa2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766577678 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.kmac_test_vectors_kmac_xof.766577678 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_224.3342200526
Short name T952
Test name
Test status
Simulation time 137723826499 ps
CPU time 3470.02 seconds
Started Jul 29 04:58:30 PM PDT 24
Finished Jul 29 05:56:21 PM PDT 24
Peak memory 3257196 kb
Host smart-c8e90bc4-9385-40ef-9454-947ef479664e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3342200526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.3342200526 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_256.645163232
Short name T305
Test name
Test status
Simulation time 247837963560 ps
CPU time 3093.05 seconds
Started Jul 29 04:58:28 PM PDT 24
Finished Jul 29 05:50:02 PM PDT 24
Peak memory 3056752 kb
Host smart-78100811-712b-4dc5-8b5f-fe688d097d22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=645163232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.645163232 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_384.3754075728
Short name T703
Test name
Test status
Simulation time 61479972199 ps
CPU time 2418.82 seconds
Started Jul 29 04:58:27 PM PDT 24
Finished Jul 29 05:38:46 PM PDT 24
Peak memory 2372940 kb
Host smart-d6384c48-4d22-4221-b1b7-e38d7acfd997
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3754075728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.3754075728 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_512.3167622247
Short name T446
Test name
Test status
Simulation time 670382363857 ps
CPU time 1650.02 seconds
Started Jul 29 04:58:34 PM PDT 24
Finished Jul 29 05:26:04 PM PDT 24
Peak memory 1740572 kb
Host smart-04adcba8-0fd4-4ede-adf0-557d15dc5db7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3167622247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.3167622247 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/45.kmac_alert_test.3108324886
Short name T850
Test name
Test status
Simulation time 30362658 ps
CPU time 0.8 seconds
Started Jul 29 04:58:52 PM PDT 24
Finished Jul 29 04:58:53 PM PDT 24
Peak memory 218420 kb
Host smart-0a87245e-ccbf-4cc8-ac27-4d591126e2af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108324886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.3108324886 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest

Test location /workspace/coverage/default/45.kmac_app.1379440499
Short name T408
Test name
Test status
Simulation time 3869036638 ps
CPU time 303.52 seconds
Started Jul 29 04:58:46 PM PDT 24
Finished Jul 29 05:03:49 PM PDT 24
Peak memory 313848 kb
Host smart-5ee84aee-a2a3-4765-8524-2ead73a3383a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379440499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.1379440499 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/45.kmac_app/latest

Test location /workspace/coverage/default/45.kmac_burst_write.4111474905
Short name T902
Test name
Test status
Simulation time 94762388506 ps
CPU time 1165.2 seconds
Started Jul 29 04:58:48 PM PDT 24
Finished Jul 29 05:18:13 PM PDT 24
Peak memory 257096 kb
Host smart-19092831-e5c9-402f-95f9-2030578e4d16
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111474905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.411147490
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest

Test location /workspace/coverage/default/45.kmac_entropy_refresh.1486007428
Short name T223
Test name
Test status
Simulation time 4971263016 ps
CPU time 193.64 seconds
Started Jul 29 04:58:47 PM PDT 24
Finished Jul 29 05:02:01 PM PDT 24
Peak memory 284896 kb
Host smart-a07cfc1c-e799-4f76-89cb-f22bce70d648
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486007428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.1
486007428 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/45.kmac_error.820852734
Short name T808
Test name
Test status
Simulation time 22351643890 ps
CPU time 242.95 seconds
Started Jul 29 04:58:47 PM PDT 24
Finished Jul 29 05:02:50 PM PDT 24
Peak memory 406936 kb
Host smart-51a2f024-b295-416f-9ace-a58828454a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820852734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.820852734 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_error/latest

Test location /workspace/coverage/default/45.kmac_key_error.2443329269
Short name T4
Test name
Test status
Simulation time 1983541965 ps
CPU time 8.28 seconds
Started Jul 29 04:58:48 PM PDT 24
Finished Jul 29 04:58:56 PM PDT 24
Peak memory 226636 kb
Host smart-707af5bf-23ec-4b72-a3fc-06547559b7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443329269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.2443329269 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest

Test location /workspace/coverage/default/45.kmac_lc_escalation.3740315218
Short name T46
Test name
Test status
Simulation time 1063656724 ps
CPU time 8.75 seconds
Started Jul 29 04:58:48 PM PDT 24
Finished Jul 29 04:58:57 PM PDT 24
Peak memory 235156 kb
Host smart-4ddb0f76-5cf2-4b2e-b138-e9cf1d9aa617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740315218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.3740315218 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/45.kmac_lc_escalation/latest

Test location /workspace/coverage/default/45.kmac_long_msg_and_output.2051575793
Short name T245
Test name
Test status
Simulation time 1104421880 ps
CPU time 128.05 seconds
Started Jul 29 04:58:40 PM PDT 24
Finished Jul 29 05:00:48 PM PDT 24
Peak memory 282752 kb
Host smart-549f6f75-f441-4c6a-8a74-f6e8abca9947
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051575793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a
nd_output.2051575793 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/45.kmac_sideload.956598361
Short name T521
Test name
Test status
Simulation time 2476913303 ps
CPU time 194.83 seconds
Started Jul 29 04:58:43 PM PDT 24
Finished Jul 29 05:01:58 PM PDT 24
Peak memory 280580 kb
Host smart-e3aa3b7a-1021-487f-9e89-8c02c2f8c9bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956598361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.956598361 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest

Test location /workspace/coverage/default/45.kmac_smoke.3748039204
Short name T568
Test name
Test status
Simulation time 3745935696 ps
CPU time 32.22 seconds
Started Jul 29 04:58:39 PM PDT 24
Finished Jul 29 04:59:11 PM PDT 24
Peak memory 226828 kb
Host smart-659d84f1-2776-4bc6-a548-d51f871c11bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748039204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.3748039204 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest

Test location /workspace/coverage/default/45.kmac_stress_all.4221840942
Short name T33
Test name
Test status
Simulation time 2940119408 ps
CPU time 244.2 seconds
Started Jul 29 04:58:53 PM PDT 24
Finished Jul 29 05:02:58 PM PDT 24
Peak memory 328504 kb
Host smart-a2ad58b0-754d-4066-93ef-13b24b68faa4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4221840942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.4221840942 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac.2018349188
Short name T582
Test name
Test status
Simulation time 438003966 ps
CPU time 7.38 seconds
Started Jul 29 04:58:47 PM PDT 24
Finished Jul 29 04:58:55 PM PDT 24
Peak memory 220020 kb
Host smart-e0dd804d-927e-4026-87b8-ecfdd070f2ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018349188 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.kmac_test_vectors_kmac.2018349188 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac_xof.655083767
Short name T668
Test name
Test status
Simulation time 971197906 ps
CPU time 6.84 seconds
Started Jul 29 04:58:46 PM PDT 24
Finished Jul 29 04:58:53 PM PDT 24
Peak memory 219696 kb
Host smart-e1baf4aa-548d-48d3-9611-4598828eede5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655083767 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.kmac_test_vectors_kmac_xof.655083767 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_224.3701982668
Short name T501
Test name
Test status
Simulation time 43026708323 ps
CPU time 2379.14 seconds
Started Jul 29 04:58:47 PM PDT 24
Finished Jul 29 05:38:26 PM PDT 24
Peak memory 1200700 kb
Host smart-135aa136-135c-47d7-aa81-a1818f8ec333
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3701982668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.3701982668 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_256.3742391957
Short name T736
Test name
Test status
Simulation time 38018428809 ps
CPU time 2168.67 seconds
Started Jul 29 04:58:49 PM PDT 24
Finished Jul 29 05:34:58 PM PDT 24
Peak memory 1160716 kb
Host smart-53ec8d68-17ea-471e-bce6-d1f8eb1e80c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3742391957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.3742391957 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_384.292931612
Short name T926
Test name
Test status
Simulation time 72741914386 ps
CPU time 2662.45 seconds
Started Jul 29 04:58:48 PM PDT 24
Finished Jul 29 05:43:11 PM PDT 24
Peak memory 2428384 kb
Host smart-ab482b98-25f2-446d-9d4e-f404fe95efaa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=292931612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.292931612 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_512.2974309409
Short name T229
Test name
Test status
Simulation time 35038016204 ps
CPU time 1683.57 seconds
Started Jul 29 04:58:47 PM PDT 24
Finished Jul 29 05:26:51 PM PDT 24
Peak memory 1747420 kb
Host smart-17261ce7-392c-4df6-abdf-b5f9fdc57c33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2974309409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.2974309409 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/46.kmac_alert_test.484748853
Short name T361
Test name
Test status
Simulation time 58213107 ps
CPU time 0.86 seconds
Started Jul 29 04:59:06 PM PDT 24
Finished Jul 29 04:59:06 PM PDT 24
Peak memory 218396 kb
Host smart-3f3356f1-2782-433d-8610-2258d56142d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484748853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.484748853 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/46.kmac_alert_test/latest

Test location /workspace/coverage/default/46.kmac_burst_write.2054884751
Short name T287
Test name
Test status
Simulation time 25564777040 ps
CPU time 1210.9 seconds
Started Jul 29 04:58:52 PM PDT 24
Finished Jul 29 05:19:03 PM PDT 24
Peak memory 258768 kb
Host smart-884606ab-0df9-478e-bb44-2fb4b9c762b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054884751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.205488475
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest

Test location /workspace/coverage/default/46.kmac_error.3000222741
Short name T729
Test name
Test status
Simulation time 1743722177 ps
CPU time 35.69 seconds
Started Jul 29 04:59:01 PM PDT 24
Finished Jul 29 04:59:37 PM PDT 24
Peak memory 255156 kb
Host smart-07018ca7-5984-402d-9fc1-bb2cb14e49a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000222741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.3000222741 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest

Test location /workspace/coverage/default/46.kmac_key_error.2464774292
Short name T641
Test name
Test status
Simulation time 3840509357 ps
CPU time 7.21 seconds
Started Jul 29 04:59:01 PM PDT 24
Finished Jul 29 04:59:08 PM PDT 24
Peak memory 226724 kb
Host smart-bc69c7b4-f37c-4372-8a4a-2eb143a0e15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464774292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.2464774292 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest

Test location /workspace/coverage/default/46.kmac_lc_escalation.321899834
Short name T923
Test name
Test status
Simulation time 111620934 ps
CPU time 1.37 seconds
Started Jul 29 04:59:06 PM PDT 24
Finished Jul 29 04:59:07 PM PDT 24
Peak memory 226776 kb
Host smart-39a10d2e-c528-4ac7-8870-895fc5ff06af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321899834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.321899834 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/46.kmac_lc_escalation/latest

Test location /workspace/coverage/default/46.kmac_long_msg_and_output.1111290592
Short name T658
Test name
Test status
Simulation time 30938482824 ps
CPU time 1055.32 seconds
Started Jul 29 04:58:52 PM PDT 24
Finished Jul 29 05:16:27 PM PDT 24
Peak memory 1311816 kb
Host smart-cff98280-27c5-46e4-8817-c98dd4157526
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111290592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_a
nd_output.1111290592 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/46.kmac_sideload.429648396
Short name T382
Test name
Test status
Simulation time 10395569314 ps
CPU time 348.94 seconds
Started Jul 29 04:58:51 PM PDT 24
Finished Jul 29 05:04:40 PM PDT 24
Peak memory 333244 kb
Host smart-113758c6-4182-47e5-b18f-f909dc76e78d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429648396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.429648396 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest

Test location /workspace/coverage/default/46.kmac_smoke.23372878
Short name T468
Test name
Test status
Simulation time 2117390354 ps
CPU time 33.71 seconds
Started Jul 29 04:58:52 PM PDT 24
Finished Jul 29 04:59:26 PM PDT 24
Peak memory 222792 kb
Host smart-43c76774-35d6-4b65-a060-8f28aebe7f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23372878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.23372878 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_smoke/latest

Test location /workspace/coverage/default/46.kmac_stress_all.3039545867
Short name T545
Test name
Test status
Simulation time 2808301592 ps
CPU time 27.02 seconds
Started Jul 29 04:59:06 PM PDT 24
Finished Jul 29 04:59:33 PM PDT 24
Peak memory 237400 kb
Host smart-b9285c86-200a-446d-9106-cebdcc52665c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3039545867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.3039545867 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac.1111963334
Short name T753
Test name
Test status
Simulation time 204871904 ps
CPU time 5.85 seconds
Started Jul 29 04:58:53 PM PDT 24
Finished Jul 29 04:58:59 PM PDT 24
Peak memory 219700 kb
Host smart-0cfc9d8b-7867-4824-a8d2-99ae918f0d18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111963334 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.kmac_test_vectors_kmac.1111963334 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac_xof.1446526149
Short name T324
Test name
Test status
Simulation time 601978552 ps
CPU time 6.16 seconds
Started Jul 29 04:58:51 PM PDT 24
Finished Jul 29 04:58:58 PM PDT 24
Peak memory 219656 kb
Host smart-aff9b5c2-a298-49a6-a2af-6b3cdd6754ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446526149 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.kmac_test_vectors_kmac_xof.1446526149 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_384.321558567
Short name T187
Test name
Test status
Simulation time 15045678529 ps
CPU time 1567.27 seconds
Started Jul 29 04:58:52 PM PDT 24
Finished Jul 29 05:24:59 PM PDT 24
Peak memory 915328 kb
Host smart-c40fcb95-ffa4-45b8-8057-1a3e0b150173
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=321558567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.321558567 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_512.1290329798
Short name T256
Test name
Test status
Simulation time 49560823605 ps
CPU time 1789.38 seconds
Started Jul 29 04:58:54 PM PDT 24
Finished Jul 29 05:28:44 PM PDT 24
Peak memory 1690224 kb
Host smart-c6fd392b-09aa-4580-9210-46f8c27a4b32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1290329798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.1290329798 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_128.1885935491
Short name T741
Test name
Test status
Simulation time 63624141459 ps
CPU time 6847.27 seconds
Started Jul 29 04:58:52 PM PDT 24
Finished Jul 29 06:53:00 PM PDT 24
Peak memory 2705240 kb
Host smart-dd1a4a3d-9308-4c71-870c-29df5f462b26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1885935491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.1885935491 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/47.kmac_alert_test.3288956678
Short name T248
Test name
Test status
Simulation time 55694729 ps
CPU time 0.81 seconds
Started Jul 29 04:59:16 PM PDT 24
Finished Jul 29 04:59:17 PM PDT 24
Peak memory 218360 kb
Host smart-122ec489-302a-4ffb-9cef-746033c5e538
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288956678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.3288956678 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_alert_test/latest

Test location /workspace/coverage/default/47.kmac_app.2438711498
Short name T238
Test name
Test status
Simulation time 8914804564 ps
CPU time 162.63 seconds
Started Jul 29 04:59:11 PM PDT 24
Finished Jul 29 05:01:54 PM PDT 24
Peak memory 275460 kb
Host smart-da147223-f81f-4c21-aa87-cd0e78ba7c76
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438711498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.2438711498 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/47.kmac_app/latest

Test location /workspace/coverage/default/47.kmac_burst_write.3711172678
Short name T579
Test name
Test status
Simulation time 37274270529 ps
CPU time 545.55 seconds
Started Jul 29 04:59:05 PM PDT 24
Finished Jul 29 05:08:11 PM PDT 24
Peak memory 243328 kb
Host smart-62caba93-efb4-4ba6-8037-5ff658ad0565
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711172678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.371117267
8 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest

Test location /workspace/coverage/default/47.kmac_entropy_refresh.3010872899
Short name T535
Test name
Test status
Simulation time 6699385782 ps
CPU time 148.98 seconds
Started Jul 29 04:59:11 PM PDT 24
Finished Jul 29 05:01:40 PM PDT 24
Peak memory 311440 kb
Host smart-b3d5b573-5c6c-44cd-a3fc-549545db00f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010872899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.3
010872899 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/47.kmac_error.2722712801
Short name T161
Test name
Test status
Simulation time 7943208768 ps
CPU time 218.65 seconds
Started Jul 29 04:59:10 PM PDT 24
Finished Jul 29 05:02:49 PM PDT 24
Peak memory 400112 kb
Host smart-ba17e942-36af-4f5d-9e2c-acf68622a74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722712801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.2722712801 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest

Test location /workspace/coverage/default/47.kmac_key_error.1229460785
Short name T293
Test name
Test status
Simulation time 1300904889 ps
CPU time 9.33 seconds
Started Jul 29 04:59:17 PM PDT 24
Finished Jul 29 04:59:26 PM PDT 24
Peak memory 226568 kb
Host smart-e4532168-acf4-4e79-96bc-4b681ba0482d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229460785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.1229460785 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest

Test location /workspace/coverage/default/47.kmac_lc_escalation.3926321347
Short name T922
Test name
Test status
Simulation time 58114326 ps
CPU time 1.56 seconds
Started Jul 29 04:59:15 PM PDT 24
Finished Jul 29 04:59:16 PM PDT 24
Peak memory 226780 kb
Host smart-68f6cfdb-981a-4760-a28b-b514446f4533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926321347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.3926321347 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/47.kmac_lc_escalation/latest

Test location /workspace/coverage/default/47.kmac_long_msg_and_output.1685291728
Short name T529
Test name
Test status
Simulation time 46629589540 ps
CPU time 2872.55 seconds
Started Jul 29 04:59:01 PM PDT 24
Finished Jul 29 05:46:54 PM PDT 24
Peak memory 1541800 kb
Host smart-6ac39b10-bede-4566-9f64-7a195830ada0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685291728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a
nd_output.1685291728 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/47.kmac_sideload.3284522372
Short name T955
Test name
Test status
Simulation time 8225884161 ps
CPU time 528.73 seconds
Started Jul 29 04:59:05 PM PDT 24
Finished Jul 29 05:07:54 PM PDT 24
Peak memory 384476 kb
Host smart-6112fc49-4830-4cec-8942-b115e587ee3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284522372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.3284522372 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest

Test location /workspace/coverage/default/47.kmac_smoke.3045096978
Short name T879
Test name
Test status
Simulation time 1031488030 ps
CPU time 37.74 seconds
Started Jul 29 04:59:01 PM PDT 24
Finished Jul 29 04:59:39 PM PDT 24
Peak memory 226772 kb
Host smart-fac64bc5-712b-4b7a-a423-897100f525ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045096978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.3045096978 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest

Test location /workspace/coverage/default/47.kmac_stress_all.392715189
Short name T383
Test name
Test status
Simulation time 16375902949 ps
CPU time 396.3 seconds
Started Jul 29 04:59:14 PM PDT 24
Finished Jul 29 05:05:51 PM PDT 24
Peak memory 392344 kb
Host smart-c4abeb00-a715-484d-b129-7e79d3778d56
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=392715189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.392715189 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac.2045740856
Short name T459
Test name
Test status
Simulation time 4603512167 ps
CPU time 7.07 seconds
Started Jul 29 04:59:11 PM PDT 24
Finished Jul 29 04:59:18 PM PDT 24
Peak memory 218960 kb
Host smart-99fea117-64cc-4329-815f-a5d357ed720c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045740856 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.kmac_test_vectors_kmac.2045740856 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac_xof.1445925765
Short name T541
Test name
Test status
Simulation time 692895318 ps
CPU time 6.18 seconds
Started Jul 29 04:59:09 PM PDT 24
Finished Jul 29 04:59:16 PM PDT 24
Peak memory 219788 kb
Host smart-10d317f1-b76b-419a-9dbb-efcb19bb2b45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445925765 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.kmac_test_vectors_kmac_xof.1445925765 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_224.2893018025
Short name T964
Test name
Test status
Simulation time 260773331795 ps
CPU time 3408.11 seconds
Started Jul 29 04:59:04 PM PDT 24
Finished Jul 29 05:55:53 PM PDT 24
Peak memory 3212844 kb
Host smart-c19a0373-acb2-46f7-aa1d-2845a2e3fa74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2893018025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.2893018025 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_256.1799252479
Short name T817
Test name
Test status
Simulation time 198033758680 ps
CPU time 3230.66 seconds
Started Jul 29 04:59:10 PM PDT 24
Finished Jul 29 05:53:01 PM PDT 24
Peak memory 3038180 kb
Host smart-38981417-102d-4cba-a27f-0203ddbd994b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1799252479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.1799252479 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_384.3239453867
Short name T909
Test name
Test status
Simulation time 479931235479 ps
CPU time 2304.33 seconds
Started Jul 29 04:59:05 PM PDT 24
Finished Jul 29 05:37:29 PM PDT 24
Peak memory 2420456 kb
Host smart-adc72d02-6f36-41ac-ab3b-938692301383
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3239453867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.3239453867 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_512.2826779219
Short name T722
Test name
Test status
Simulation time 98058106075 ps
CPU time 1837.63 seconds
Started Jul 29 04:59:06 PM PDT 24
Finished Jul 29 05:29:44 PM PDT 24
Peak memory 1717700 kb
Host smart-d270cf90-5a74-44a5-8ace-c0e19e15ff00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2826779219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.2826779219 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/48.kmac_alert_test.2404765613
Short name T942
Test name
Test status
Simulation time 22924044 ps
CPU time 0.9 seconds
Started Jul 29 04:59:30 PM PDT 24
Finished Jul 29 04:59:31 PM PDT 24
Peak memory 218396 kb
Host smart-78927b7a-3ee2-468b-aaa6-d803ef895937
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404765613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.2404765613 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_alert_test/latest

Test location /workspace/coverage/default/48.kmac_app.1640605383
Short name T326
Test name
Test status
Simulation time 22239015358 ps
CPU time 45.65 seconds
Started Jul 29 04:59:29 PM PDT 24
Finished Jul 29 05:00:15 PM PDT 24
Peak memory 254780 kb
Host smart-75fedb6e-47e3-4021-8acf-f213c3b9c476
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640605383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.1640605383 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest

Test location /workspace/coverage/default/48.kmac_burst_write.264403012
Short name T325
Test name
Test status
Simulation time 15142454789 ps
CPU time 449.83 seconds
Started Jul 29 04:59:18 PM PDT 24
Finished Jul 29 05:06:48 PM PDT 24
Peak memory 233632 kb
Host smart-2e2b4f39-c15e-4d4e-86ef-e607f1efc7df
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264403012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.264403012
+enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_burst_write/latest

Test location /workspace/coverage/default/48.kmac_entropy_refresh.1170298526
Short name T596
Test name
Test status
Simulation time 7187730836 ps
CPU time 154.02 seconds
Started Jul 29 04:59:30 PM PDT 24
Finished Jul 29 05:02:04 PM PDT 24
Peak memory 348004 kb
Host smart-ba2926d7-f7c7-45a9-96cc-092092278561
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170298526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.1
170298526 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/48.kmac_key_error.2776615122
Short name T420
Test name
Test status
Simulation time 309988749 ps
CPU time 1.64 seconds
Started Jul 29 04:59:29 PM PDT 24
Finished Jul 29 04:59:30 PM PDT 24
Peak memory 226400 kb
Host smart-d6602e53-fa68-43e2-a431-31378faead2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776615122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.2776615122 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_key_error/latest

Test location /workspace/coverage/default/48.kmac_lc_escalation.2327870604
Short name T26
Test name
Test status
Simulation time 116806018 ps
CPU time 1.31 seconds
Started Jul 29 04:59:31 PM PDT 24
Finished Jul 29 04:59:33 PM PDT 24
Peak memory 226792 kb
Host smart-2fd8a213-0ded-4383-aef7-0b07cc39b43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327870604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.2327870604 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/48.kmac_lc_escalation/latest

Test location /workspace/coverage/default/48.kmac_long_msg_and_output.193954241
Short name T231
Test name
Test status
Simulation time 9755958123 ps
CPU time 607.85 seconds
Started Jul 29 04:59:14 PM PDT 24
Finished Jul 29 05:09:22 PM PDT 24
Peak memory 543464 kb
Host smart-3556339f-1fde-48d9-a575-6b5ec57937b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193954241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_an
d_output.193954241 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/48.kmac_sideload.3633039470
Short name T365
Test name
Test status
Simulation time 11296469892 ps
CPU time 134.69 seconds
Started Jul 29 04:59:19 PM PDT 24
Finished Jul 29 05:01:34 PM PDT 24
Peak memory 268336 kb
Host smart-ebdc4b7a-0a6b-4d2e-a45e-bb4e5469f352
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633039470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.3633039470 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest

Test location /workspace/coverage/default/48.kmac_smoke.178232652
Short name T449
Test name
Test status
Simulation time 297145332 ps
CPU time 12.19 seconds
Started Jul 29 04:59:14 PM PDT 24
Finished Jul 29 04:59:26 PM PDT 24
Peak memory 223228 kb
Host smart-c514bc28-0016-4452-a1f6-7ea4d708f682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178232652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.178232652 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest

Test location /workspace/coverage/default/48.kmac_stress_all.2144768954
Short name T48
Test name
Test status
Simulation time 28740279897 ps
CPU time 2909.39 seconds
Started Jul 29 04:59:31 PM PDT 24
Finished Jul 29 05:48:00 PM PDT 24
Peak memory 1010164 kb
Host smart-3498faed-c842-42bf-9823-6d779a795b28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2144768954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.2144768954 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac.1820447315
Short name T887
Test name
Test status
Simulation time 380635184 ps
CPU time 5.51 seconds
Started Jul 29 04:59:28 PM PDT 24
Finished Jul 29 04:59:34 PM PDT 24
Peak memory 219688 kb
Host smart-8e1db644-9aab-49a7-9efa-402a20cd67e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820447315 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.kmac_test_vectors_kmac.1820447315 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac_xof.3618002054
Short name T838
Test name
Test status
Simulation time 229839611 ps
CPU time 6.53 seconds
Started Jul 29 04:59:31 PM PDT 24
Finished Jul 29 04:59:38 PM PDT 24
Peak memory 218828 kb
Host smart-577f5efc-4e59-4dbf-bbd2-a9088fc68c25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618002054 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.kmac_test_vectors_kmac_xof.3618002054 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_224.2867174351
Short name T492
Test name
Test status
Simulation time 67795039744 ps
CPU time 2969.37 seconds
Started Jul 29 04:59:18 PM PDT 24
Finished Jul 29 05:48:47 PM PDT 24
Peak memory 3197716 kb
Host smart-4a027114-54ca-416c-9ea4-374a2a88b77e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2867174351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.2867174351 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_256.957464239
Short name T799
Test name
Test status
Simulation time 130499861355 ps
CPU time 2338.96 seconds
Started Jul 29 04:59:19 PM PDT 24
Finished Jul 29 05:38:18 PM PDT 24
Peak memory 1155192 kb
Host smart-d4f9073e-951d-45ee-9541-a618e9cfecda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=957464239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.957464239 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_384.389599233
Short name T195
Test name
Test status
Simulation time 408808227700 ps
CPU time 2607.02 seconds
Started Jul 29 04:59:24 PM PDT 24
Finished Jul 29 05:42:52 PM PDT 24
Peak memory 2456216 kb
Host smart-77a789e6-e081-4f19-a2bc-4dcc3ae1b890
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=389599233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.389599233 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_512.1620683376
Short name T967
Test name
Test status
Simulation time 37711759007 ps
CPU time 1307.28 seconds
Started Jul 29 04:59:25 PM PDT 24
Finished Jul 29 05:21:12 PM PDT 24
Peak memory 707248 kb
Host smart-08adccba-3034-442f-83b6-6c39f4a9b39f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1620683376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.1620683376 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/49.kmac_alert_test.1100077038
Short name T284
Test name
Test status
Simulation time 49433160 ps
CPU time 0.86 seconds
Started Jul 29 04:59:56 PM PDT 24
Finished Jul 29 04:59:57 PM PDT 24
Peak memory 218352 kb
Host smart-eb384edb-1056-41e5-8e6a-6f82a10e097b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100077038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.1100077038 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest

Test location /workspace/coverage/default/49.kmac_app.1339196966
Short name T871
Test name
Test status
Simulation time 12992918015 ps
CPU time 341.64 seconds
Started Jul 29 04:59:46 PM PDT 24
Finished Jul 29 05:05:28 PM PDT 24
Peak memory 472116 kb
Host smart-7584550b-6baf-42d1-b35d-b60b022d975a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339196966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.1339196966 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest

Test location /workspace/coverage/default/49.kmac_burst_write.3575904579
Short name T865
Test name
Test status
Simulation time 23532029119 ps
CPU time 264.95 seconds
Started Jul 29 04:59:33 PM PDT 24
Finished Jul 29 05:03:58 PM PDT 24
Peak memory 233064 kb
Host smart-3a6d76ba-b5ea-4be2-abe7-68bf92113d3f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575904579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.357590457
9 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest

Test location /workspace/coverage/default/49.kmac_entropy_refresh.3711541944
Short name T279
Test name
Test status
Simulation time 4569124165 ps
CPU time 186.96 seconds
Started Jul 29 04:59:48 PM PDT 24
Finished Jul 29 05:02:55 PM PDT 24
Peak memory 280856 kb
Host smart-95a79a7f-0dce-4422-804e-6cbae6265efe
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711541944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.3
711541944 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/49.kmac_error.1661180954
Short name T426
Test name
Test status
Simulation time 3694601513 ps
CPU time 64.4 seconds
Started Jul 29 04:59:45 PM PDT 24
Finished Jul 29 05:00:50 PM PDT 24
Peak memory 284176 kb
Host smart-1a0054f4-d09d-49f5-8e20-601da0336f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661180954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.1661180954 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_error/latest

Test location /workspace/coverage/default/49.kmac_key_error.2476327217
Short name T721
Test name
Test status
Simulation time 2924492563 ps
CPU time 6.35 seconds
Started Jul 29 04:59:48 PM PDT 24
Finished Jul 29 04:59:54 PM PDT 24
Peak memory 226672 kb
Host smart-a720ca90-483b-4ce4-b148-f7e32347a7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476327217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.2476327217 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_key_error/latest

Test location /workspace/coverage/default/49.kmac_lc_escalation.3194416303
Short name T973
Test name
Test status
Simulation time 462495200 ps
CPU time 16.13 seconds
Started Jul 29 04:59:51 PM PDT 24
Finished Jul 29 05:00:07 PM PDT 24
Peak memory 241364 kb
Host smart-e3f5e78b-d331-4390-bf00-e0f9ccaa4172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194416303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.3194416303 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/49.kmac_lc_escalation/latest

Test location /workspace/coverage/default/49.kmac_long_msg_and_output.108203065
Short name T624
Test name
Test status
Simulation time 228063936217 ps
CPU time 3490.48 seconds
Started Jul 29 04:59:34 PM PDT 24
Finished Jul 29 05:57:45 PM PDT 24
Peak memory 2890952 kb
Host smart-c6b2df36-f68a-4d22-b710-81b2ddb58112
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108203065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_an
d_output.108203065 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/49.kmac_sideload.1414028290
Short name T257
Test name
Test status
Simulation time 46400064477 ps
CPU time 305.75 seconds
Started Jul 29 04:59:35 PM PDT 24
Finished Jul 29 05:04:41 PM PDT 24
Peak memory 440280 kb
Host smart-cda22d39-22d0-4c69-95ce-6c37003f6ee4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414028290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.1414028290 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest

Test location /workspace/coverage/default/49.kmac_smoke.4154961146
Short name T904
Test name
Test status
Simulation time 3130998718 ps
CPU time 31.98 seconds
Started Jul 29 04:59:36 PM PDT 24
Finished Jul 29 05:00:08 PM PDT 24
Peak memory 223356 kb
Host smart-5890ed20-6aed-4c13-a164-72abf2b59de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154961146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.4154961146 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac.2363982051
Short name T586
Test name
Test status
Simulation time 373615231 ps
CPU time 6.25 seconds
Started Jul 29 04:59:45 PM PDT 24
Finished Jul 29 04:59:51 PM PDT 24
Peak memory 219632 kb
Host smart-6385226b-138d-498a-aa77-e388c6c546ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363982051 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.kmac_test_vectors_kmac.2363982051 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac_xof.3320001156
Short name T706
Test name
Test status
Simulation time 1090483940 ps
CPU time 7.01 seconds
Started Jul 29 04:59:46 PM PDT 24
Finished Jul 29 04:59:53 PM PDT 24
Peak memory 220076 kb
Host smart-c0b79f02-3fd8-4e04-b593-3e93dabb5969
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320001156 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.kmac_test_vectors_kmac_xof.3320001156 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_224.1452596787
Short name T377
Test name
Test status
Simulation time 43868718638 ps
CPU time 2252.59 seconds
Started Jul 29 04:59:33 PM PDT 24
Finished Jul 29 05:37:06 PM PDT 24
Peak memory 1188776 kb
Host smart-a86697c1-0629-4d8a-838c-c3aea3cb3d98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1452596787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.1452596787 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_256.428993034
Short name T769
Test name
Test status
Simulation time 189452523396 ps
CPU time 3471.07 seconds
Started Jul 29 04:59:39 PM PDT 24
Finished Jul 29 05:57:30 PM PDT 24
Peak memory 3032900 kb
Host smart-7bdc566e-b124-4d6d-b792-d3ba2bdafa48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=428993034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.428993034 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_384.1144268774
Short name T288
Test name
Test status
Simulation time 199031070819 ps
CPU time 2400.52 seconds
Started Jul 29 04:59:39 PM PDT 24
Finished Jul 29 05:39:40 PM PDT 24
Peak memory 2407084 kb
Host smart-d725e0d0-1d1d-490c-b760-37e59f8abc49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1144268774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.1144268774 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_512.3796407270
Short name T750
Test name
Test status
Simulation time 122914836368 ps
CPU time 1645.36 seconds
Started Jul 29 04:59:40 PM PDT 24
Finished Jul 29 05:27:05 PM PDT 24
Peak memory 1725292 kb
Host smart-2ec1aebf-398b-407d-8afa-8e022d99550a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3796407270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.3796407270 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/5.kmac_alert_test.4186865002
Short name T622
Test name
Test status
Simulation time 69193492 ps
CPU time 0.85 seconds
Started Jul 29 04:56:05 PM PDT 24
Finished Jul 29 04:56:06 PM PDT 24
Peak memory 218448 kb
Host smart-f2e9c560-7f4c-4391-b841-99fd4e6e938d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186865002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.4186865002 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_alert_test/latest

Test location /workspace/coverage/default/5.kmac_app.126843546
Short name T559
Test name
Test status
Simulation time 75052261887 ps
CPU time 251.61 seconds
Started Jul 29 04:55:56 PM PDT 24
Finished Jul 29 05:00:07 PM PDT 24
Peak memory 408172 kb
Host smart-25e22ddb-aae8-4250-8255-b8d65886835a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126843546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.126843546 +enable_masking=1
+sw_key_masked=0
Directory /workspace/5.kmac_app/latest

Test location /workspace/coverage/default/5.kmac_app_with_partial_data.122439153
Short name T436
Test name
Test status
Simulation time 17971087864 ps
CPU time 232.77 seconds
Started Jul 29 04:55:47 PM PDT 24
Finished Jul 29 04:59:39 PM PDT 24
Peak memory 289992 kb
Host smart-a3b7c4a1-7e3a-4310-aa0a-5dfe6a306f46
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122439153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_part
ial_data.122439153 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/5.kmac_burst_write.1052064924
Short name T847
Test name
Test status
Simulation time 23486498800 ps
CPU time 1258.44 seconds
Started Jul 29 04:55:49 PM PDT 24
Finished Jul 29 05:16:47 PM PDT 24
Peak memory 261332 kb
Host smart-54627627-5c31-45b6-ad6a-bab3aafaa942
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052064924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.1052064924
+enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest

Test location /workspace/coverage/default/5.kmac_edn_timeout_error.157224897
Short name T845
Test name
Test status
Simulation time 40610634 ps
CPU time 1.11 seconds
Started Jul 29 04:55:44 PM PDT 24
Finished Jul 29 04:55:45 PM PDT 24
Peak memory 218304 kb
Host smart-fc3b759d-efbd-4e79-8f72-d9d20555ca5d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=157224897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.157224897 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_mode_error.2694584012
Short name T220
Test name
Test status
Simulation time 1501844568 ps
CPU time 35.05 seconds
Started Jul 29 04:55:48 PM PDT 24
Finished Jul 29 04:56:24 PM PDT 24
Peak memory 226964 kb
Host smart-8a8bb5f8-ac37-41b9-a35d-05cf35f93c43
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2694584012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.2694584012 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_ready_error.2709511127
Short name T882
Test name
Test status
Simulation time 2607197262 ps
CPU time 40.85 seconds
Started Jul 29 04:55:50 PM PDT 24
Finished Jul 29 04:56:31 PM PDT 24
Peak memory 226916 kb
Host smart-20806609-0593-4f7b-949e-99138e40737f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709511127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.2709511127 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_refresh.4021251568
Short name T67
Test name
Test status
Simulation time 4136963358 ps
CPU time 94.62 seconds
Started Jul 29 04:55:58 PM PDT 24
Finished Jul 29 04:57:33 PM PDT 24
Peak memory 279256 kb
Host smart-ba4fcf82-54cf-4b4f-b4bf-2ebf70fa6abf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021251568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.40
21251568 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/5.kmac_error.2040180326
Short name T724
Test name
Test status
Simulation time 4829640351 ps
CPU time 167.28 seconds
Started Jul 29 04:55:49 PM PDT 24
Finished Jul 29 04:58:37 PM PDT 24
Peak memory 344820 kb
Host smart-dace59f2-66d8-4ebc-ae4c-f8ee376e92a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040180326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.2040180326 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_error/latest

Test location /workspace/coverage/default/5.kmac_key_error.1153113160
Short name T711
Test name
Test status
Simulation time 1889746152 ps
CPU time 12.52 seconds
Started Jul 29 04:56:04 PM PDT 24
Finished Jul 29 04:56:17 PM PDT 24
Peak memory 226644 kb
Host smart-36c815af-bf96-43d6-9648-8ad911326b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153113160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.1153113160 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest

Test location /workspace/coverage/default/5.kmac_lc_escalation.2911665199
Short name T789
Test name
Test status
Simulation time 769362617 ps
CPU time 38.3 seconds
Started Jul 29 04:55:44 PM PDT 24
Finished Jul 29 04:56:32 PM PDT 24
Peak memory 245548 kb
Host smart-7a550298-23c4-4271-a9b2-e2f4c11d8970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911665199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.2911665199 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/5.kmac_lc_escalation/latest

Test location /workspace/coverage/default/5.kmac_long_msg_and_output.1535480126
Short name T526
Test name
Test status
Simulation time 3926811302 ps
CPU time 142.31 seconds
Started Jul 29 04:55:43 PM PDT 24
Finished Jul 29 04:58:05 PM PDT 24
Peak memory 399720 kb
Host smart-984110d4-e69b-424c-b910-25e151e3a175
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535480126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_an
d_output.1535480126 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/5.kmac_mubi.1343259534
Short name T169
Test name
Test status
Simulation time 7037641734 ps
CPU time 229.45 seconds
Started Jul 29 04:55:45 PM PDT 24
Finished Jul 29 04:59:34 PM PDT 24
Peak memory 375280 kb
Host smart-01a35013-8d9e-47e7-80e8-0b56767aefeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343259534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.1343259534 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest

Test location /workspace/coverage/default/5.kmac_sideload.3962248219
Short name T895
Test name
Test status
Simulation time 5339154483 ps
CPU time 394.53 seconds
Started Jul 29 04:55:53 PM PDT 24
Finished Jul 29 05:02:28 PM PDT 24
Peak memory 363132 kb
Host smart-29020ced-c521-4488-bf9e-ee2daedbc6a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962248219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.3962248219 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest

Test location /workspace/coverage/default/5.kmac_smoke.3853536774
Short name T485
Test name
Test status
Simulation time 63271635805 ps
CPU time 91.13 seconds
Started Jul 29 04:55:52 PM PDT 24
Finished Jul 29 04:57:24 PM PDT 24
Peak memory 226876 kb
Host smart-9d8f3824-36c7-4959-a5bf-298218a5a93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853536774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.3853536774 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_smoke/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac.3857272852
Short name T253
Test name
Test status
Simulation time 1987598395 ps
CPU time 5.29 seconds
Started Jul 29 04:56:01 PM PDT 24
Finished Jul 29 04:56:06 PM PDT 24
Peak memory 218764 kb
Host smart-2e205a17-c9c8-4c62-a54e-33e1f5fbcc34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857272852 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.kmac_test_vectors_kmac.3857272852 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac_xof.3773854864
Short name T228
Test name
Test status
Simulation time 238437016 ps
CPU time 5.48 seconds
Started Jul 29 04:55:43 PM PDT 24
Finished Jul 29 04:55:49 PM PDT 24
Peak memory 218788 kb
Host smart-c65a7bb7-2720-4c30-8c06-7448ceade990
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773854864 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.kmac_test_vectors_kmac_xof.3773854864 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_256.610435919
Short name T906
Test name
Test status
Simulation time 509478495788 ps
CPU time 3091.41 seconds
Started Jul 29 04:56:02 PM PDT 24
Finished Jul 29 05:47:34 PM PDT 24
Peak memory 3034456 kb
Host smart-de9a932c-2220-450e-8d37-3e3f42247780
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=610435919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.610435919 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_384.3932200126
Short name T834
Test name
Test status
Simulation time 472388364490 ps
CPU time 2641.51 seconds
Started Jul 29 04:55:46 PM PDT 24
Finished Jul 29 05:39:48 PM PDT 24
Peak memory 2375176 kb
Host smart-3fa8d23c-d94b-435d-9910-3be08e447c9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3932200126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.3932200126 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_512.1551659364
Short name T694
Test name
Test status
Simulation time 112107540699 ps
CPU time 1673.86 seconds
Started Jul 29 04:56:05 PM PDT 24
Finished Jul 29 05:23:59 PM PDT 24
Peak memory 1752828 kb
Host smart-23daa061-f28d-4328-b43f-975d27ef3265
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1551659364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.1551659364 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/6.kmac_alert_test.330109852
Short name T743
Test name
Test status
Simulation time 88466278 ps
CPU time 0.85 seconds
Started Jul 29 04:55:54 PM PDT 24
Finished Jul 29 04:55:55 PM PDT 24
Peak memory 218412 kb
Host smart-7c46658c-c104-464a-b7dd-68e40cee3d0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330109852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.330109852 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/6.kmac_alert_test/latest

Test location /workspace/coverage/default/6.kmac_app.3635697303
Short name T227
Test name
Test status
Simulation time 254477372 ps
CPU time 3.23 seconds
Started Jul 29 04:55:40 PM PDT 24
Finished Jul 29 04:55:43 PM PDT 24
Peak memory 226872 kb
Host smart-0424871a-43ae-4528-bd25-ad9ff1a4632f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635697303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.3635697303 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/6.kmac_app/latest

Test location /workspace/coverage/default/6.kmac_app_with_partial_data.295449869
Short name T974
Test name
Test status
Simulation time 10225853409 ps
CPU time 126.3 seconds
Started Jul 29 04:55:52 PM PDT 24
Finished Jul 29 04:57:58 PM PDT 24
Peak memory 305652 kb
Host smart-c0814a69-4d58-4095-bf7f-f39b4b0c43b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295449869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_part
ial_data.295449869 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/6.kmac_burst_write.3295756544
Short name T410
Test name
Test status
Simulation time 9145058941 ps
CPU time 1042.97 seconds
Started Jul 29 04:56:05 PM PDT 24
Finished Jul 29 05:13:28 PM PDT 24
Peak memory 242560 kb
Host smart-c1b08f10-cef3-4d9c-976d-ce8fd81f99d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295756544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.3295756544
+enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_burst_write/latest

Test location /workspace/coverage/default/6.kmac_edn_timeout_error.2579548091
Short name T60
Test name
Test status
Simulation time 99174135 ps
CPU time 1.1 seconds
Started Jul 29 04:55:51 PM PDT 24
Finished Jul 29 04:55:52 PM PDT 24
Peak memory 218548 kb
Host smart-32c1d3e6-3a73-4490-b48e-4ca857b47198
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2579548091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.2579548091 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_mode_error.4058156448
Short name T701
Test name
Test status
Simulation time 1683884878 ps
CPU time 37.26 seconds
Started Jul 29 04:55:52 PM PDT 24
Finished Jul 29 04:56:29 PM PDT 24
Peak memory 226648 kb
Host smart-ce19c063-fd3d-41b1-9757-7fbd62d5fd22
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4058156448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.4058156448 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_ready_error.4186998414
Short name T342
Test name
Test status
Simulation time 4037155122 ps
CPU time 41.83 seconds
Started Jul 29 04:55:58 PM PDT 24
Finished Jul 29 04:56:40 PM PDT 24
Peak memory 226880 kb
Host smart-bd335329-7981-442b-a738-d788ef98b2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186998414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.4186998414 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_refresh.2605816345
Short name T65
Test name
Test status
Simulation time 10637878330 ps
CPU time 62.28 seconds
Started Jul 29 04:56:11 PM PDT 24
Finished Jul 29 04:57:14 PM PDT 24
Peak memory 268872 kb
Host smart-7dcad8c8-961e-4824-a739-acde668108a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605816345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.26
05816345 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/6.kmac_key_error.3376983096
Short name T805
Test name
Test status
Simulation time 2842503022 ps
CPU time 6.45 seconds
Started Jul 29 04:55:59 PM PDT 24
Finished Jul 29 04:56:05 PM PDT 24
Peak memory 226764 kb
Host smart-af4b1ae9-3739-4c06-be02-b64152552b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376983096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.3376983096 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_key_error/latest

Test location /workspace/coverage/default/6.kmac_lc_escalation.309498630
Short name T72
Test name
Test status
Simulation time 67981324 ps
CPU time 1.63 seconds
Started Jul 29 04:55:53 PM PDT 24
Finished Jul 29 04:55:54 PM PDT 24
Peak memory 226756 kb
Host smart-41db91f0-9890-485d-a848-4d35fd5f1631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309498630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.309498630 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_lc_escalation/latest

Test location /workspace/coverage/default/6.kmac_long_msg_and_output.2295385875
Short name T454
Test name
Test status
Simulation time 8170738884 ps
CPU time 232.47 seconds
Started Jul 29 04:55:47 PM PDT 24
Finished Jul 29 04:59:39 PM PDT 24
Peak memory 337244 kb
Host smart-44cdcdfb-0a86-48af-bc66-ff8e0f7be298
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295385875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an
d_output.2295385875 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/6.kmac_mubi.293882969
Short name T762
Test name
Test status
Simulation time 5963707867 ps
CPU time 138.56 seconds
Started Jul 29 04:55:49 PM PDT 24
Finished Jul 29 04:58:08 PM PDT 24
Peak memory 341940 kb
Host smart-400e8bf4-bba0-4c9c-b93a-a63a1bba4839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293882969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.293882969 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest

Test location /workspace/coverage/default/6.kmac_sideload.1956995816
Short name T638
Test name
Test status
Simulation time 15231091727 ps
CPU time 445.28 seconds
Started Jul 29 04:55:52 PM PDT 24
Finished Jul 29 05:03:17 PM PDT 24
Peak memory 549660 kb
Host smart-47a3924e-ac79-4c00-afa5-3faed06dda82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956995816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.1956995816 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest

Test location /workspace/coverage/default/6.kmac_smoke.3427509355
Short name T681
Test name
Test status
Simulation time 1943323898 ps
CPU time 20.99 seconds
Started Jul 29 04:56:02 PM PDT 24
Finished Jul 29 04:56:23 PM PDT 24
Peak memory 222816 kb
Host smart-ce72439d-18d8-47fd-ba54-53396298a425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427509355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.3427509355 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest

Test location /workspace/coverage/default/6.kmac_stress_all.2497402924
Short name T829
Test name
Test status
Simulation time 18836930259 ps
CPU time 723.41 seconds
Started Jul 29 04:55:51 PM PDT 24
Finished Jul 29 05:07:55 PM PDT 24
Peak memory 816316 kb
Host smart-d01bc0f4-966a-480f-99f1-4ea8959a422b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2497402924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.2497402924 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac.876322916
Short name T296
Test name
Test status
Simulation time 126540838 ps
CPU time 5.87 seconds
Started Jul 29 04:56:15 PM PDT 24
Finished Jul 29 04:56:21 PM PDT 24
Peak memory 218796 kb
Host smart-46f9ff60-3a14-404b-a074-40201255fa9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876322916 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.kmac_test_vectors_kmac.876322916 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac_xof.3294831410
Short name T362
Test name
Test status
Simulation time 1342173132 ps
CPU time 6.56 seconds
Started Jul 29 04:55:54 PM PDT 24
Finished Jul 29 04:56:00 PM PDT 24
Peak memory 218796 kb
Host smart-f2f7dcad-56a4-49e5-a788-7ec865a34b2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294831410 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.kmac_test_vectors_kmac_xof.3294831410 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_224.3875682177
Short name T244
Test name
Test status
Simulation time 24030471994 ps
CPU time 2126.17 seconds
Started Jul 29 04:55:42 PM PDT 24
Finished Jul 29 05:31:09 PM PDT 24
Peak memory 1204188 kb
Host smart-bdd7b1b0-39f2-40ef-8343-ded5c28f0ed5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3875682177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.3875682177 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_256.593857237
Short name T738
Test name
Test status
Simulation time 21290800032 ps
CPU time 2125.44 seconds
Started Jul 29 04:56:01 PM PDT 24
Finished Jul 29 05:31:27 PM PDT 24
Peak memory 1147496 kb
Host smart-fd4792d4-bd03-408c-9db0-e25a1f582902
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=593857237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.593857237 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_384.4063375323
Short name T811
Test name
Test status
Simulation time 300810320554 ps
CPU time 2684.96 seconds
Started Jul 29 04:56:10 PM PDT 24
Finished Jul 29 05:40:56 PM PDT 24
Peak memory 2450948 kb
Host smart-fcfb23a6-4b90-4b12-86bf-f5ffc35d60f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4063375323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.4063375323 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_512.2217148830
Short name T533
Test name
Test status
Simulation time 33984703921 ps
CPU time 1399.82 seconds
Started Jul 29 04:55:53 PM PDT 24
Finished Jul 29 05:19:13 PM PDT 24
Peak memory 1747768 kb
Host smart-ed64ed4c-1fd7-4d91-8dce-ba118adcc46b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2217148830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.2217148830 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_256.3812185812
Short name T807
Test name
Test status
Simulation time 189521964767 ps
CPU time 5698.21 seconds
Started Jul 29 04:55:50 PM PDT 24
Finished Jul 29 06:30:49 PM PDT 24
Peak memory 2221652 kb
Host smart-185e2cdb-021b-4cb5-89e3-2d9783e713e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3812185812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.3812185812 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/7.kmac_alert_test.1255778984
Short name T267
Test name
Test status
Simulation time 21005170 ps
CPU time 0.91 seconds
Started Jul 29 04:56:18 PM PDT 24
Finished Jul 29 04:56:19 PM PDT 24
Peak memory 218404 kb
Host smart-41a297c4-777f-444b-9f06-48976220fabb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255778984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.1255778984 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_alert_test/latest

Test location /workspace/coverage/default/7.kmac_app.3591874952
Short name T218
Test name
Test status
Simulation time 2727293857 ps
CPU time 71.63 seconds
Started Jul 29 04:55:54 PM PDT 24
Finished Jul 29 04:57:16 PM PDT 24
Peak memory 279352 kb
Host smart-fd6340f6-13c1-4942-af32-08a6951a30a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591874952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.3591874952 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/7.kmac_app/latest

Test location /workspace/coverage/default/7.kmac_app_with_partial_data.527327273
Short name T627
Test name
Test status
Simulation time 30050589039 ps
CPU time 346.33 seconds
Started Jul 29 04:56:01 PM PDT 24
Finished Jul 29 05:01:48 PM PDT 24
Peak memory 470700 kb
Host smart-9e21c10b-f4ac-43a4-a61a-08d21f560cfd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527327273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_part
ial_data.527327273 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/7.kmac_burst_write.1214649596
Short name T493
Test name
Test status
Simulation time 12662883254 ps
CPU time 1452.83 seconds
Started Jul 29 04:55:46 PM PDT 24
Finished Jul 29 05:19:59 PM PDT 24
Peak memory 246844 kb
Host smart-96f2b44f-6971-469d-b8a4-a5aeeea7087a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214649596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.1214649596
+enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest

Test location /workspace/coverage/default/7.kmac_edn_timeout_error.1495720959
Short name T740
Test name
Test status
Simulation time 32899808 ps
CPU time 0.92 seconds
Started Jul 29 04:56:20 PM PDT 24
Finished Jul 29 04:56:21 PM PDT 24
Peak memory 218368 kb
Host smart-93715822-5f55-498c-b035-9618b6eb054a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1495720959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.1495720959 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_mode_error.4247224922
Short name T929
Test name
Test status
Simulation time 1393358055 ps
CPU time 44.25 seconds
Started Jul 29 04:55:48 PM PDT 24
Finished Jul 29 04:56:33 PM PDT 24
Peak memory 226856 kb
Host smart-5852f22f-c75d-4414-a85d-4f33155b97f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4247224922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.4247224922 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_ready_error.3493807725
Short name T976
Test name
Test status
Simulation time 12329294318 ps
CPU time 58.55 seconds
Started Jul 29 04:55:52 PM PDT 24
Finished Jul 29 04:56:50 PM PDT 24
Peak memory 226916 kb
Host smart-ded379ac-06ec-4658-a80d-c0ed35f1e14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493807725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.3493807725 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_refresh.628458883
Short name T17
Test name
Test status
Simulation time 9979136966 ps
CPU time 128.05 seconds
Started Jul 29 04:56:10 PM PDT 24
Finished Jul 29 04:58:18 PM PDT 24
Peak memory 307624 kb
Host smart-e48e89d6-68c8-44b7-896c-f20ca34e4cc7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628458883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.628
458883 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/7.kmac_error.4140271907
Short name T629
Test name
Test status
Simulation time 585476420 ps
CPU time 40.24 seconds
Started Jul 29 04:56:16 PM PDT 24
Finished Jul 29 04:56:57 PM PDT 24
Peak memory 258884 kb
Host smart-65ed91e2-847f-4caf-b1e4-b7cdb05d58e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140271907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.4140271907 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest

Test location /workspace/coverage/default/7.kmac_key_error.877833787
Short name T6
Test name
Test status
Simulation time 4018080718 ps
CPU time 6.84 seconds
Started Jul 29 04:55:49 PM PDT 24
Finished Jul 29 04:55:56 PM PDT 24
Peak memory 218488 kb
Host smart-59111ba2-a2b7-4195-b65b-f508afc877d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877833787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.877833787 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest

Test location /workspace/coverage/default/7.kmac_lc_escalation.2205003953
Short name T45
Test name
Test status
Simulation time 3281173296 ps
CPU time 39.02 seconds
Started Jul 29 04:55:54 PM PDT 24
Finished Jul 29 04:56:33 PM PDT 24
Peak memory 248820 kb
Host smart-9c67594c-b4b9-400c-a4c8-318b187abf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205003953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.2205003953 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/7.kmac_lc_escalation/latest

Test location /workspace/coverage/default/7.kmac_long_msg_and_output.2721738479
Short name T732
Test name
Test status
Simulation time 115785916824 ps
CPU time 1467.61 seconds
Started Jul 29 04:55:55 PM PDT 24
Finished Jul 29 05:20:23 PM PDT 24
Peak memory 1541836 kb
Host smart-9d67ec6e-1d4e-49a0-b1b9-e967c5883d38
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721738479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an
d_output.2721738479 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/7.kmac_mubi.444858893
Short name T962
Test name
Test status
Simulation time 11588497876 ps
CPU time 373.17 seconds
Started Jul 29 04:56:10 PM PDT 24
Finished Jul 29 05:02:23 PM PDT 24
Peak memory 337636 kb
Host smart-2f73774e-5a6f-47f3-8366-ff71a08e6917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444858893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.444858893 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest

Test location /workspace/coverage/default/7.kmac_sideload.2703655825
Short name T322
Test name
Test status
Simulation time 10322051237 ps
CPU time 431.8 seconds
Started Jul 29 04:56:13 PM PDT 24
Finished Jul 29 05:03:25 PM PDT 24
Peak memory 385068 kb
Host smart-3ac4bcd5-2126-4da6-aaa6-42fe2302967e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703655825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.2703655825 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest

Test location /workspace/coverage/default/7.kmac_smoke.991716230
Short name T693
Test name
Test status
Simulation time 7098213557 ps
CPU time 63 seconds
Started Jul 29 04:55:53 PM PDT 24
Finished Jul 29 04:56:56 PM PDT 24
Peak memory 226884 kb
Host smart-8fd8f51c-0cd3-42f3-a2c3-f1cede74c3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991716230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.991716230 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_stress_all.157487343
Short name T461
Test name
Test status
Simulation time 66089196579 ps
CPU time 609.26 seconds
Started Jul 29 04:55:57 PM PDT 24
Finished Jul 29 05:06:06 PM PDT 24
Peak memory 356712 kb
Host smart-68a5c200-c651-43d6-8031-74a037309386
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=157487343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.157487343 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac.917755051
Short name T201
Test name
Test status
Simulation time 244668550 ps
CPU time 6.37 seconds
Started Jul 29 04:56:16 PM PDT 24
Finished Jul 29 04:56:22 PM PDT 24
Peak memory 218880 kb
Host smart-b9389aa5-d0a8-4af7-a262-cfa1dbd752f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917755051 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.kmac_test_vectors_kmac.917755051 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac_xof.1965722883
Short name T194
Test name
Test status
Simulation time 122872838 ps
CPU time 5.97 seconds
Started Jul 29 04:55:51 PM PDT 24
Finished Jul 29 04:55:57 PM PDT 24
Peak memory 218740 kb
Host smart-9bce59f4-bc5e-4128-856a-32d3d35dd977
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965722883 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.kmac_test_vectors_kmac_xof.1965722883 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_224.2729149206
Short name T835
Test name
Test status
Simulation time 144395471558 ps
CPU time 3436.16 seconds
Started Jul 29 04:55:57 PM PDT 24
Finished Jul 29 05:53:14 PM PDT 24
Peak memory 3210484 kb
Host smart-73caf7ac-4485-4919-a33d-7aecd5d01546
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2729149206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.2729149206 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_256.1479712290
Short name T877
Test name
Test status
Simulation time 83340615670 ps
CPU time 3314.76 seconds
Started Jul 29 04:56:13 PM PDT 24
Finished Jul 29 05:51:28 PM PDT 24
Peak memory 3020360 kb
Host smart-c65ef3d0-9ff3-41a7-ab30-896a4b955b0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1479712290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.1479712290 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_384.3142357675
Short name T289
Test name
Test status
Simulation time 112337169767 ps
CPU time 2419.72 seconds
Started Jul 29 04:55:50 PM PDT 24
Finished Jul 29 05:36:10 PM PDT 24
Peak memory 2374580 kb
Host smart-5ead7bcb-6683-4d65-be10-7ba49df3fdb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3142357675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.3142357675 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_512.2291089707
Short name T576
Test name
Test status
Simulation time 294599208676 ps
CPU time 2062.15 seconds
Started Jul 29 04:55:56 PM PDT 24
Finished Jul 29 05:30:19 PM PDT 24
Peak memory 1762472 kb
Host smart-1cf34ccc-686a-4b16-8fe1-1e2623d3232b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2291089707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.2291089707 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_256.1461302530
Short name T332
Test name
Test status
Simulation time 61170451887 ps
CPU time 5555.79 seconds
Started Jul 29 04:56:02 PM PDT 24
Finished Jul 29 06:28:38 PM PDT 24
Peak memory 2207196 kb
Host smart-70684283-368c-48bd-93a3-5f1e77189234
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1461302530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.1461302530 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/8.kmac_alert_test.3316078739
Short name T255
Test name
Test status
Simulation time 69941553 ps
CPU time 0.86 seconds
Started Jul 29 04:55:55 PM PDT 24
Finished Jul 29 04:55:56 PM PDT 24
Peak memory 218440 kb
Host smart-26af1499-69d7-48c0-bdd4-fd2d9dd89943
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316078739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.3316078739 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_alert_test/latest

Test location /workspace/coverage/default/8.kmac_app.1542554256
Short name T111
Test name
Test status
Simulation time 8145187660 ps
CPU time 248.86 seconds
Started Jul 29 04:55:38 PM PDT 24
Finished Jul 29 04:59:47 PM PDT 24
Peak memory 407672 kb
Host smart-76cce8db-acff-412e-9818-916c39251a32
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542554256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.1542554256 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/8.kmac_app/latest

Test location /workspace/coverage/default/8.kmac_app_with_partial_data.1376212670
Short name T705
Test name
Test status
Simulation time 45357206043 ps
CPU time 325.06 seconds
Started Jul 29 04:56:15 PM PDT 24
Finished Jul 29 05:01:41 PM PDT 24
Peak memory 457072 kb
Host smart-1a065c33-d888-40f4-bbbf-6257d3bd9d8e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376212670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_par
tial_data.1376212670 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/8.kmac_burst_write.1906078974
Short name T417
Test name
Test status
Simulation time 38734770810 ps
CPU time 1829.11 seconds
Started Jul 29 04:55:57 PM PDT 24
Finished Jul 29 05:26:26 PM PDT 24
Peak memory 271124 kb
Host smart-f1895e26-323d-4cd0-ba18-04b477fd57ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906078974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.1906078974
+enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest

Test location /workspace/coverage/default/8.kmac_edn_timeout_error.2513615028
Short name T756
Test name
Test status
Simulation time 106848677 ps
CPU time 1.07 seconds
Started Jul 29 04:55:52 PM PDT 24
Finished Jul 29 04:55:53 PM PDT 24
Peak memory 218544 kb
Host smart-657a63c4-c329-4f03-b9cd-0dddaf2f0f69
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2513615028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.2513615028 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_mode_error.2757548584
Short name T437
Test name
Test status
Simulation time 56535872 ps
CPU time 0.94 seconds
Started Jul 29 04:55:50 PM PDT 24
Finished Jul 29 04:55:51 PM PDT 24
Peak memory 221748 kb
Host smart-bcb75d5f-9046-4d08-adde-7c86913e5681
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2757548584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.2757548584 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_ready_error.1493898966
Short name T8
Test name
Test status
Simulation time 11297656585 ps
CPU time 47.56 seconds
Started Jul 29 04:56:19 PM PDT 24
Finished Jul 29 04:57:07 PM PDT 24
Peak memory 224208 kb
Host smart-1cbce106-2df5-4a00-96dd-ac2633ddbd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493898966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.1493898966 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_refresh.2663126666
Short name T605
Test name
Test status
Simulation time 44002001221 ps
CPU time 372.63 seconds
Started Jul 29 04:55:59 PM PDT 24
Finished Jul 29 05:02:11 PM PDT 24
Peak memory 447660 kb
Host smart-9febd6b3-0ed4-4cd9-87a4-a4497a6bfaca
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663126666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.26
63126666 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/8.kmac_error.188107141
Short name T663
Test name
Test status
Simulation time 26419900477 ps
CPU time 318.92 seconds
Started Jul 29 04:55:59 PM PDT 24
Finished Jul 29 05:01:18 PM PDT 24
Peak memory 474176 kb
Host smart-15b03e88-228d-461d-ac2d-d443d0341905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188107141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.188107141 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest

Test location /workspace/coverage/default/8.kmac_key_error.1519578222
Short name T659
Test name
Test status
Simulation time 2259465785 ps
CPU time 3.21 seconds
Started Jul 29 04:56:17 PM PDT 24
Finished Jul 29 04:56:21 PM PDT 24
Peak memory 226580 kb
Host smart-5aa63461-754e-47dc-a649-eceee10a968d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519578222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.1519578222 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest

Test location /workspace/coverage/default/8.kmac_lc_escalation.1885138738
Short name T41
Test name
Test status
Simulation time 168890365 ps
CPU time 1.4 seconds
Started Jul 29 04:55:52 PM PDT 24
Finished Jul 29 04:55:53 PM PDT 24
Peak memory 226700 kb
Host smart-2e526c95-176f-4647-8683-c25611b28c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885138738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.1885138738 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/8.kmac_lc_escalation/latest

Test location /workspace/coverage/default/8.kmac_long_msg_and_output.2384664223
Short name T389
Test name
Test status
Simulation time 9458059922 ps
CPU time 1038.22 seconds
Started Jul 29 04:56:23 PM PDT 24
Finished Jul 29 05:13:42 PM PDT 24
Peak memory 732640 kb
Host smart-e6da822f-0c4f-49f9-89bc-a26953769ab7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384664223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an
d_output.2384664223 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/8.kmac_mubi.914129728
Short name T897
Test name
Test status
Simulation time 12937865301 ps
CPU time 169.07 seconds
Started Jul 29 04:56:05 PM PDT 24
Finished Jul 29 04:58:55 PM PDT 24
Peak memory 354572 kb
Host smart-5ae50ed7-2ee9-415e-803e-df2e038eaf89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914129728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.914129728 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_mubi/latest

Test location /workspace/coverage/default/8.kmac_sideload.3774360491
Short name T689
Test name
Test status
Simulation time 15155456413 ps
CPU time 434.32 seconds
Started Jul 29 04:55:48 PM PDT 24
Finished Jul 29 05:03:03 PM PDT 24
Peak memory 362608 kb
Host smart-faaede1d-bfc5-4b4c-871f-549c82636ee5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774360491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.3774360491 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_sideload/latest

Test location /workspace/coverage/default/8.kmac_smoke.3879575910
Short name T954
Test name
Test status
Simulation time 335526404 ps
CPU time 8.62 seconds
Started Jul 29 04:55:51 PM PDT 24
Finished Jul 29 04:56:00 PM PDT 24
Peak memory 223208 kb
Host smart-82f2430f-3383-4cee-b27f-0e42b94c3179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879575910 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.3879575910 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest

Test location /workspace/coverage/default/8.kmac_stress_all.1097120066
Short name T268
Test name
Test status
Simulation time 1196548395 ps
CPU time 24.27 seconds
Started Jul 29 04:56:05 PM PDT 24
Finished Jul 29 04:56:29 PM PDT 24
Peak memory 233952 kb
Host smart-856744a6-aa3d-4afc-af85-bdf6acfdc71a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1097120066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.1097120066 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac.4282132252
Short name T746
Test name
Test status
Simulation time 996149230 ps
CPU time 5.87 seconds
Started Jul 29 04:56:00 PM PDT 24
Finished Jul 29 04:56:06 PM PDT 24
Peak memory 218756 kb
Host smart-8003776b-6339-4262-90e0-64ff1f1d0534
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282132252 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.kmac_test_vectors_kmac.4282132252 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac_xof.2837577153
Short name T200
Test name
Test status
Simulation time 184404524 ps
CPU time 5.67 seconds
Started Jul 29 04:55:59 PM PDT 24
Finished Jul 29 04:56:04 PM PDT 24
Peak memory 218804 kb
Host smart-89d21b39-d6aa-41ed-9c1a-e986bcd565d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837577153 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.kmac_test_vectors_kmac_xof.2837577153 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_224.685252473
Short name T612
Test name
Test status
Simulation time 45965014899 ps
CPU time 2183.05 seconds
Started Jul 29 04:55:58 PM PDT 24
Finished Jul 29 05:32:22 PM PDT 24
Peak memory 1183576 kb
Host smart-083f486e-6227-4d06-bfa8-a00798d3bd14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=685252473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.685252473 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_256.2826799731
Short name T520
Test name
Test status
Simulation time 82436342712 ps
CPU time 2275.78 seconds
Started Jul 29 04:55:52 PM PDT 24
Finished Jul 29 05:33:48 PM PDT 24
Peak memory 1154984 kb
Host smart-c839915a-0e64-4a00-a0c6-f1056bdac25f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2826799731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.2826799731 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_384.666895724
Short name T710
Test name
Test status
Simulation time 15525920954 ps
CPU time 1729.68 seconds
Started Jul 29 04:55:55 PM PDT 24
Finished Jul 29 05:24:45 PM PDT 24
Peak memory 913236 kb
Host smart-51a3bc98-4f58-4680-89fa-6e4b3c759800
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=666895724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.666895724 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_512.1804880958
Short name T35
Test name
Test status
Simulation time 123122504774 ps
CPU time 1928.35 seconds
Started Jul 29 04:55:47 PM PDT 24
Finished Jul 29 05:27:57 PM PDT 24
Peak memory 1731220 kb
Host smart-dccc23d0-f8ec-4d2c-b8dc-76714618538c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1804880958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.1804880958 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_256.3510100883
Short name T192
Test name
Test status
Simulation time 52593036851 ps
CPU time 5616.62 seconds
Started Jul 29 04:56:00 PM PDT 24
Finished Jul 29 06:29:37 PM PDT 24
Peak memory 2243476 kb
Host smart-c86cca67-96f8-4719-ba67-8bb5f0519a44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3510100883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.3510100883 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/9.kmac_alert_test.358230456
Short name T896
Test name
Test status
Simulation time 13149030 ps
CPU time 0.81 seconds
Started Jul 29 04:55:58 PM PDT 24
Finished Jul 29 04:55:59 PM PDT 24
Peak memory 218464 kb
Host smart-3901fcf4-d8d0-45d2-bcd5-4aa13eddd3cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358230456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.358230456 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/9.kmac_alert_test/latest

Test location /workspace/coverage/default/9.kmac_app.2927992272
Short name T274
Test name
Test status
Simulation time 16932860369 ps
CPU time 449.64 seconds
Started Jul 29 04:56:00 PM PDT 24
Finished Jul 29 05:03:29 PM PDT 24
Peak memory 519436 kb
Host smart-a2e95044-3912-41d4-85da-699db40b30e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927992272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.2927992272 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/9.kmac_app/latest

Test location /workspace/coverage/default/9.kmac_app_with_partial_data.161277829
Short name T487
Test name
Test status
Simulation time 19979007188 ps
CPU time 319.7 seconds
Started Jul 29 04:55:47 PM PDT 24
Finished Jul 29 05:01:07 PM PDT 24
Peak memory 308244 kb
Host smart-4db2793d-b53d-4cc1-8fc1-e50e30e4a478
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161277829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_part
ial_data.161277829 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/9.kmac_burst_write.111733745
Short name T908
Test name
Test status
Simulation time 141290740529 ps
CPU time 381.27 seconds
Started Jul 29 04:55:45 PM PDT 24
Finished Jul 29 05:02:10 PM PDT 24
Peak memory 243288 kb
Host smart-f5e7f4a2-01de-45ae-8538-44bb237586d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111733745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.111733745 +
enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_burst_write/latest

Test location /workspace/coverage/default/9.kmac_edn_timeout_error.2531756420
Short name T837
Test name
Test status
Simulation time 43957246 ps
CPU time 1.02 seconds
Started Jul 29 04:55:55 PM PDT 24
Finished Jul 29 04:55:57 PM PDT 24
Peak memory 218436 kb
Host smart-1082bb5b-834f-4937-8e21-f8886c8fc1a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2531756420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.2531756420 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_mode_error.1192577621
Short name T726
Test name
Test status
Simulation time 429905558 ps
CPU time 1.37 seconds
Started Jul 29 04:56:04 PM PDT 24
Finished Jul 29 04:56:06 PM PDT 24
Peak memory 222272 kb
Host smart-859737a4-69cc-4376-b8a5-c1511ae15e30
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1192577621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.1192577621 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_ready_error.1043889005
Short name T10
Test name
Test status
Simulation time 6825099010 ps
CPU time 54.77 seconds
Started Jul 29 04:56:13 PM PDT 24
Finished Jul 29 04:57:08 PM PDT 24
Peak memory 223828 kb
Host smart-a510aa48-db21-4a03-9755-c30d4ad5316b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043889005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.1043889005 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_refresh.790651302
Short name T604
Test name
Test status
Simulation time 56432867131 ps
CPU time 283.87 seconds
Started Jul 29 04:55:49 PM PDT 24
Finished Jul 29 05:00:34 PM PDT 24
Peak memory 308492 kb
Host smart-b0b6ad59-d499-4e5e-ac72-eedf318803b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790651302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.790
651302 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/9.kmac_error.3389418266
Short name T398
Test name
Test status
Simulation time 10491187356 ps
CPU time 407.28 seconds
Started Jul 29 04:55:57 PM PDT 24
Finished Jul 29 05:02:44 PM PDT 24
Peak memory 514204 kb
Host smart-cd729692-d4ae-41c6-8d24-3a12d155f622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389418266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.3389418266 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest

Test location /workspace/coverage/default/9.kmac_key_error.1680398529
Short name T863
Test name
Test status
Simulation time 1227923685 ps
CPU time 3.11 seconds
Started Jul 29 04:55:52 PM PDT 24
Finished Jul 29 04:55:56 PM PDT 24
Peak memory 226380 kb
Host smart-25632121-465b-4898-9048-e4f1d635681c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680398529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.1680398529 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest

Test location /workspace/coverage/default/9.kmac_lc_escalation.4004120452
Short name T977
Test name
Test status
Simulation time 60155855 ps
CPU time 1.34 seconds
Started Jul 29 04:56:18 PM PDT 24
Finished Jul 29 04:56:20 PM PDT 24
Peak memory 226928 kb
Host smart-a55a01f3-340c-4209-8449-88b1f6582fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004120452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.4004120452 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/9.kmac_lc_escalation/latest

Test location /workspace/coverage/default/9.kmac_long_msg_and_output.570538328
Short name T562
Test name
Test status
Simulation time 4623269651 ps
CPU time 487.7 seconds
Started Jul 29 04:56:22 PM PDT 24
Finished Jul 29 05:04:30 PM PDT 24
Peak memory 492100 kb
Host smart-b354c386-3c88-44ef-9f01-69283024c6f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570538328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and
_output.570538328 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/9.kmac_mubi.3943743955
Short name T625
Test name
Test status
Simulation time 58627411770 ps
CPU time 224.78 seconds
Started Jul 29 04:56:15 PM PDT 24
Finished Jul 29 05:00:00 PM PDT 24
Peak memory 385404 kb
Host smart-a1572bff-9dcf-4c19-a6ed-bde58a7b6101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943743955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.3943743955 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest

Test location /workspace/coverage/default/9.kmac_sideload.606616653
Short name T263
Test name
Test status
Simulation time 14054553736 ps
CPU time 106.84 seconds
Started Jul 29 04:55:56 PM PDT 24
Finished Jul 29 04:57:43 PM PDT 24
Peak memory 263652 kb
Host smart-b7629c70-be37-4b4a-896c-340b20e9c8af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606616653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.606616653 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest

Test location /workspace/coverage/default/9.kmac_smoke.1567996915
Short name T416
Test name
Test status
Simulation time 2975869568 ps
CPU time 30.71 seconds
Started Jul 29 04:56:17 PM PDT 24
Finished Jul 29 04:56:47 PM PDT 24
Peak memory 222364 kb
Host smart-21ff8842-79fa-4d4d-8847-6a0ab55ed501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567996915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.1567996915 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_smoke/latest

Test location /workspace/coverage/default/9.kmac_stress_all.2398338707
Short name T572
Test name
Test status
Simulation time 25020670537 ps
CPU time 1857.53 seconds
Started Jul 29 04:55:58 PM PDT 24
Finished Jul 29 05:26:56 PM PDT 24
Peak memory 760448 kb
Host smart-10ecf2a1-f091-45c5-ad1e-0221200eb2cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2398338707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.2398338707 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac.1264157770
Short name T331
Test name
Test status
Simulation time 852706310 ps
CPU time 6.48 seconds
Started Jul 29 04:55:48 PM PDT 24
Finished Jul 29 04:55:55 PM PDT 24
Peak memory 219644 kb
Host smart-ccb49aa0-9544-49b4-98f8-d3272c16d3ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264157770 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.kmac_test_vectors_kmac.1264157770 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac_xof.1861350261
Short name T609
Test name
Test status
Simulation time 730998437 ps
CPU time 5.83 seconds
Started Jul 29 04:55:55 PM PDT 24
Finished Jul 29 04:56:01 PM PDT 24
Peak memory 219792 kb
Host smart-97940209-7305-4265-9f89-e1904a173852
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861350261 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.kmac_test_vectors_kmac_xof.1861350261 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_224.1586334439
Short name T603
Test name
Test status
Simulation time 88165906840 ps
CPU time 3313.93 seconds
Started Jul 29 04:55:58 PM PDT 24
Finished Jul 29 05:51:12 PM PDT 24
Peak memory 3210248 kb
Host smart-b7dfbbcf-a047-421f-ac8d-ecbcecddaa8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1586334439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.1586334439 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_384.381879278
Short name T547
Test name
Test status
Simulation time 15023694552 ps
CPU time 1660.44 seconds
Started Jul 29 04:55:50 PM PDT 24
Finished Jul 29 05:23:31 PM PDT 24
Peak memory 902960 kb
Host smart-babd54d2-8950-42ad-b497-f5c3a43aea9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=381879278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.381879278 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_512.1531899026
Short name T226
Test name
Test status
Simulation time 73238162569 ps
CPU time 1268.26 seconds
Started Jul 29 04:56:18 PM PDT 24
Finished Jul 29 05:17:27 PM PDT 24
Peak memory 690648 kb
Host smart-e611292d-99ad-4c6f-8d44-db0f16b2c65c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1531899026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.1531899026 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_128.2760427363
Short name T598
Test name
Test status
Simulation time 277096493951 ps
CPU time 6207.36 seconds
Started Jul 29 04:56:02 PM PDT 24
Finished Jul 29 06:39:31 PM PDT 24
Peak memory 2618116 kb
Host smart-6c876695-fed4-4135-82f8-e3da6d2dfab6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2760427363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.2760427363 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_256.3638472755
Short name T510
Test name
Test status
Simulation time 344588732705 ps
CPU time 5029.72 seconds
Started Jul 29 04:56:15 PM PDT 24
Finished Jul 29 06:20:05 PM PDT 24
Peak memory 2243484 kb
Host smart-372da17f-c992-4c10-b1b8-9d32b0a49436
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3638472755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.3638472755 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_256/latest
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