Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	62100504	1			T2	138		T3	5741		T17	215234
all_values[1]	62100504	1			T2	138		T3	5741		T17	215234
all_values[2]	62100504	1			T2	138		T3	5741		T17	215234

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

423204

1

T2

276

T3

146

T17

37

auto[1]

185878308

1

T2

138

T3

17077

T17

645665

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

185414871

1

T2

408

T3

17049

T17

644025

auto[1]

886641

1

T2

6

T3

174

T17

1677

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	138458	1			T2	136		T17	13		T7	410
all_values[0]	auto[0]	auto[1]	1841	1			T2	2		T17	12		T7	4
all_values[0]	auto[1]	auto[0]	61666499	1			T3	5683		T17	214662		T7	1638
all_values[0]	auto[1]	auto[1]	293706	1			T3	58		T17	547		T7	12
all_values[1]	auto[0]	auto[0]	158263	1			T2	136		T17	6		T33	3
all_values[1]	auto[0]	auto[1]	1460	1			T2	2		T17	6		T33	4
all_values[1]	auto[1]	auto[0]	61646694	1			T3	5683		T17	214669		T7	2048
all_values[1]	auto[1]	auto[1]	294087	1			T3	58		T17	553		T7	16
all_values[2]	auto[0]	auto[0]	121879	1			T3	145		T7	619		T14	4441
all_values[2]	auto[0]	auto[1]	1303	1			T3	1		T7	5		T14	14
all_values[2]	auto[1]	auto[0]	61683078	1			T2	136		T3	5538		T17	214675
all_values[2]	auto[1]	auto[1]	294244	1			T2	2		T3	57		T17	559