| | | | | | | |
tlul_err_resp |
57.14 |
71.43 |
50.00 |
|
|
50.00 |
|
kmac_app |
83.27 |
94.57 |
86.30 |
|
44.44 |
91.01 |
100.00 |
kmac_staterd |
90.00 |
100.00 |
70.00 |
|
|
100.00 |
|
prim_intr_hw |
90.35 |
95.00 |
76.39 |
|
|
90.00 |
100.00 |
prim_intr_hw |
100.00 |
|
|
|
|
|
100.00 |
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" ) |
91.67 |
100.00 |
75.00 |
|
|
100.00 |
|
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" ) |
82.59 |
90.00 |
77.78 |
|
|
80.00 |
|
prim_fifo_sync_cnt |
90.79 |
96.00 |
90.00 |
|
|
86.36 |
|
prim_fifo_sync_cnt ( parameter Depth=1,Secure=0,PtrW=1,DepthW=1,WrapPtrW=2 ) |
81.58 |
92.00 |
80.00 |
|
|
72.73 |
|
prim_fifo_sync_cnt ( parameter Depth=10,Secure=1,PtrW=4,DepthW=4,WrapPtrW=5 ) |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
keccak_round |
91.81 |
94.55 |
100.00 |
|
73.33 |
91.18 |
100.00 |
prim_fifo_sync |
93.36 |
100.00 |
73.44 |
|
|
100.00 |
100.00 |
prim_fifo_sync |
100.00 |
|
|
|
|
|
100.00 |
prim_fifo_sync ( parameter Width=109,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 ) |
84.38 |
100.00 |
68.75 |
|
|
|
|
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 ) |
100.00 |
|
|
|
|
100.00 |
|
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 ) |
87.50 |
100.00 |
75.00 |
|
|
|
|
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=72,Pass=1,Depth=10,OutputZeroIfEmpty=1,Secure=1,DepthW=4,gen_normal_fifo.PtrW=4 ) |
100.00 |
|
|
|
|
100.00 |
|
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 ) |
81.25 |
100.00 |
62.50 |
|
|
|
|
prim_fifo_sync ( parameter Width=72,Pass=1,Depth=10,OutputZeroIfEmpty=1,Secure=1,DepthW=4,gen_normal_fifo.PtrW=4 ) |
93.75 |
100.00 |
87.50 |
|
|
|
|
kmac_entropy |
93.57 |
100.00 |
87.83 |
|
80.00 |
100.00 |
100.00 |
tlul_adapter_sram |
93.71 |
98.58 |
80.12 |
|
|
96.15 |
100.00 |
tlul_adapter_sram |
98.08 |
|
|
|
|
96.15 |
100.00 |
tlul_adapter_sram ( parameter SramAw=7,SramDw=32,Outstanding=1,SramBusBankAW=12,ByteAccess=1,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0,SecFifoPtr=0,EnableReadback=0,DataXorAddr=0,WidthMult=1,DataOutW=32,DataBitWidth=2,WoffsetWidth=1,DataWidth=32 ) |
90.53 |
98.61 |
82.46 |
|
|
|
|
tlul_adapter_sram ( parameter SramAw=9,SramDw=32,Outstanding=1,SramBusBankAW=12,ByteAccess=1,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0,SecFifoPtr=0,EnableReadback=0,DataXorAddr=0,WidthMult=1,DataOutW=32,DataBitWidth=2,WoffsetWidth=1,DataWidth=32 ) |
88.16 |
98.55 |
77.78 |
|
|
|
|
kmac_errchk |
93.84 |
94.59 |
94.59 |
|
86.67 |
93.33 |
100.00 |
sha3pad |
93.84 |
99.41 |
88.37 |
|
85.71 |
95.70 |
100.00 |
sha3 |
94.14 |
97.56 |
88.89 |
|
90.91 |
93.33 |
100.00 |
kmac_core |
94.30 |
98.68 |
92.86 |
|
100.00 |
91.07 |
88.89 |
prim_arbiter_fixed |
95.05 |
87.50 |
92.68 |
|
|
100.00 |
100.00 |
prim_trivium |
95.62 |
100.00 |
88.37 |
|
|
94.12 |
100.00 |
tlul_rsp_intg_gen |
95.83 |
91.67 |
|
|
|
|
100.00 |
tlul_rsp_intg_gen |
100.00 |
|
|
|
|
|
100.00 |
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 ) |
83.33 |
83.33 |
|
|
|
|
|
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_sync_reqack |
95.83 |
100.00 |
83.33 |
|
|
100.00 |
100.00 |
prim_count |
96.58 |
|
|
96.58 |
|
|
|
prim_count ( parameter Width=10,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 ) |
100.00 |
|
|
100.00 |
|
|
|
prim_count ( parameter Width=5,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 ) |
100.00 |
|
|
100.00 |
|
|
|
prim_count ( parameter Width=8,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 ) |
89.74 |
|
|
89.74 |
|
|
|
prim_subreg_shadow |
97.12 |
100.00 |
88.46 |
|
|
100.00 |
100.00 |
tlul_socket_1n |
97.25 |
100.00 |
93.33 |
|
|
95.65 |
100.00 |
prim_packer |
98.08 |
100.00 |
100.00 |
|
|
92.31 |
100.00 |
kmac_msgfifo |
98.21 |
100.00 |
|
|
100.00 |
92.86 |
100.00 |
kmac |
98.76 |
98.75 |
96.74 |
100.00 |
100.00 |
97.06 |
100.00 |
tlul_adapter_reg |
98.98 |
100.00 |
95.92 |
|
|
100.00 |
100.00 |
keccak_2share |
99.37 |
100.00 |
98.75 |
|
|
98.73 |
100.00 |
kmac_reg_top |
99.97 |
100.00 |
99.87 |
|
|
100.00 |
100.00 |
prim_lc_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
tlul_data_integ_dec |
100.00 |
100.00 |
|
|
|
|
|
prim_sparse_fsm_flop |
100.00 |
100.00 |
|
|
|
|
100.00 |
tlul_cmd_intg_chk |
100.00 |
100.00 |
|
|
|
|
100.00 |
prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
sha3pad_assert_if |
100.00 |
|
|
|
|
|
100.00 |
prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
tlul_fifo_sync |
100.00 |
|
100.00 |
|
|
100.00 |
|
prim_generic_xor2 |
100.00 |
100.00 |
|
|
|
|
|
tlul_assert |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
prim_onehot_check |
100.00 |
|
|
100.00 |
|
|
|
prim_subreg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
prim_subreg |
100.00 |
100.00 |
|
|
|
100.00 |
|
prim_subreg ( parameter DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=1,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=10,SwAccess=0,RESVAL,Mubi=0 + DW=10,SwAccess=1,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=16,SwAccess=0,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=2,SwAccess=0,RESVAL,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=3,SwAccess=0,RESVAL,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=32,SwAccess=0,RESVAL=0,Mubi=0 + DW=32,SwAccess=1,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_secded_inv_39_32_dec |
100.00 |
|
|
100.00 |
|
|
|
prim_generic_buf |
100.00 |
100.00 |
|
|
|
|
|
prim_slicer |
100.00 |
100.00 |
|
|
|
|
100.00 |
prim_subreg_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
prim_subreg_arb |
100.00 |
|
|
|
|
100.00 |
|
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=3,SwAccess=0,Mubi=0 + DW=2,SwAccess=0,Mubi=0 + DW=10,SwAccess=0,Mubi=0 + DW=16,SwAccess=0,Mubi=0 + DW=32,SwAccess=0,Mubi=0 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 + DW=10,SwAccess=1,Mubi=0 + DW=32,SwAccess=1,Mubi=0 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 ) |
100.00 |
100.00 |
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=10,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=16,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=2,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=3,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
kmac_csr_assert_fpv |
100.00 |
|
|
|
|
|
100.00 |
prim_subreg_ext |
100.00 |
100.00 |
|
|
|
|
|
prim_generic_flop_en |
100.00 |
100.00 |
|
|
|
100.00 |
|
prim_secded_inv_39_32_enc |
100.00 |
100.00 |
|
|
|
|
|
tlul_sram_byte |
100.00 |
100.00 |
|
|
|
|
100.00 |
tlul_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
prim_secded_inv_64_57_enc |
100.00 |
100.00 |
|
|
|
|
|
prim_secded_inv_64_57_dec |
100.00 |
|
|
100.00 |
|
|
|
prim_dom_and_2share |
100.00 |
100.00 |
|
|
|
|
100.00 |
prim_sync_reqack_data |
100.00 |
100.00 |
|
|
|
|
100.00 |
prim_generic_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
tlul_data_integ_enc |
|
|
|
|
|
|
|
prim_reg_we_check |
|
|
|
|
|
|
|
prim_flop_en |
|
|
|
|
|
|
|
prim_buf |
|
|
|
|
|
|
|
prim_generic_flop_2sync |
|
|
|
|
|
|
|
prim_xor2 |
|
|
|
|
|
|
|
prim_flop |
|
|
|
|
|
|
|
prim_flop_2sync |
|
|
|
|
|
|
|
tb |
|
|
|
|
|
|
|
prim_sec_anchor_buf |
|
|
|
|
|
|
|