Summary for Variable entropy_edn_mode_enabled
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
196764 | 
1 | 
 | 
 | 
T2 | 
2 | 
 | 
T3 | 
2 | 
 | 
T17 | 
2 | 
| auto[1] | 
210952 | 
1 | 
 | 
 | 
T2 | 
2 | 
 | 
T3 | 
70 | 
 | 
T17 | 
746 | 
Summary for Variable prescaler_val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for prescaler_val
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 
101806 | 
1 | 
 | 
 | 
T3 | 
18 | 
 | 
T17 | 
208 | 
 | 
T7 | 
4 | 
| lower_val | 
100968 | 
1 | 
 | 
 | 
T3 | 
17 | 
 | 
T17 | 
216 | 
 | 
T7 | 
4 | 
| zero_val | 
1451 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 | 
T17 | 
3 | 
Summary for Variable wait_timer_val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for wait_timer_val
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 
150812 | 
1 | 
 | 
 | 
T2 | 
2 | 
 | 
T3 | 
12 | 
 | 
T17 | 
182 | 
| lower_val | 
151632 | 
1 | 
 | 
 | 
T2 | 
2 | 
 | 
T3 | 
22 | 
 | 
T17 | 
146 | 
| zero_val | 
105272 | 
1 | 
 | 
 | 
T3 | 
38 | 
 | 
T17 | 
420 | 
 | 
T33 | 
348 | 
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
18 | 
0 | 
18 | 
100.00 | 
 | 
Automatically Generated Cross Bins for entropy_timer_cross
Bins
| prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 
higher_val | 
auto[0] | 
24413 | 
1 | 
 | 
 | 
T7 | 
3 | 
 | 
T8 | 
35 | 
 | 
T14 | 
78 | 
| higher_val | 
higher_val | 
auto[1] | 
13218 | 
1 | 
 | 
 | 
T3 | 
4 | 
 | 
T17 | 
56 | 
 | 
T33 | 
57 | 
| higher_val | 
lower_val | 
auto[0] | 
24313 | 
1 | 
 | 
 | 
T7 | 
1 | 
 | 
T8 | 
31 | 
 | 
T14 | 
81 | 
| higher_val | 
lower_val | 
auto[1] | 
13359 | 
1 | 
 | 
 | 
T3 | 
7 | 
 | 
T17 | 
40 | 
 | 
T33 | 
43 | 
| higher_val | 
zero_val | 
auto[0] | 
78 | 
1 | 
 | 
 | 
T17 | 
1 | 
 | 
T14 | 
1 | 
 | 
T56 | 
1 | 
| higher_val | 
zero_val | 
auto[1] | 
26425 | 
1 | 
 | 
 | 
T3 | 
7 | 
 | 
T17 | 
111 | 
 | 
T33 | 
91 | 
| lower_val | 
higher_val | 
auto[0] | 
24518 | 
1 | 
 | 
 | 
T7 | 
2 | 
 | 
T12 | 
1 | 
 | 
T8 | 
20 | 
| lower_val | 
higher_val | 
auto[1] | 
13058 | 
1 | 
 | 
 | 
T17 | 
52 | 
 | 
T33 | 
51 | 
 | 
T14 | 
24 | 
| lower_val | 
lower_val | 
auto[0] | 
24344 | 
1 | 
 | 
 | 
T7 | 
2 | 
 | 
T8 | 
32 | 
 | 
T14 | 
72 | 
| lower_val | 
lower_val | 
auto[1] | 
13171 | 
1 | 
 | 
 | 
T3 | 
5 | 
 | 
T17 | 
46 | 
 | 
T33 | 
49 | 
| lower_val | 
zero_val | 
auto[0] | 
78 | 
1 | 
 | 
 | 
T14 | 
1 | 
 | 
T178 | 
1 | 
 | 
T112 | 
1 | 
| lower_val | 
zero_val | 
auto[1] | 
25799 | 
1 | 
 | 
 | 
T3 | 
12 | 
 | 
T17 | 
118 | 
 | 
T33 | 
88 | 
| zero_val | 
higher_val | 
auto[0] | 
474 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T7 | 
1 | 
 | 
T12 | 
1 | 
| zero_val | 
higher_val | 
auto[1] | 
110 | 
1 | 
 | 
 | 
T14 | 
1 | 
 | 
T35 | 
1 | 
 | 
T18 | 
1 | 
| zero_val | 
lower_val | 
auto[0] | 
401 | 
1 | 
 | 
 | 
T14 | 
1 | 
 | 
T13 | 
1 | 
 | 
T35 | 
1 | 
| zero_val | 
lower_val | 
auto[1] | 
106 | 
1 | 
 | 
 | 
T17 | 
1 | 
 | 
T14 | 
3 | 
 | 
T192 | 
1 | 
| zero_val | 
zero_val | 
auto[0] | 
221 | 
1 | 
 | 
 | 
T3 | 
1 | 
 | 
T17 | 
1 | 
 | 
T14 | 
1 | 
| zero_val | 
zero_val | 
auto[1] | 
139 | 
1 | 
 | 
 | 
T17 | 
1 | 
 | 
T14 | 
1 | 
 | 
T35 | 
3 |