Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	62100504	1			T2	138		T3	5741		T17	215234
all_pins[1]	62100504	1			T2	138		T3	5741		T17	215234
all_pins[2]	62100504	1			T2	138		T3	5741		T17	215234

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	185731166	1			T2	414		T3	17165		T17	645155
values[0x1]	570346	1			T3	58		T17	547		T7	15
transitions[0x0=>0x1]	568487	1			T3	58		T17	547		T7	15
transitions[0x1=>0x0]	568510	1			T3	58		T17	547		T7	15

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	61806798	1			T2	138		T3	5683		T17	214687
all_pins[0]	values[0x1]	293706	1			T3	58		T17	547		T7	12
all_pins[0]	transitions[0x0=>0x1]	293700	1			T3	58		T17	547		T7	12
all_pins[0]	transitions[0x1=>0x0]	5399	1			T7	3		T8	25		T14	164
all_pins[1]	values[0x0]	62095099	1			T2	138		T3	5741		T17	215234
all_pins[1]	values[0x1]	5405	1			T7	3		T8	25		T14	164
all_pins[1]	transitions[0x0=>0x1]	5161	1			T7	3		T8	25		T14	162
all_pins[1]	transitions[0x1=>0x0]	270991	1			T14	1714		T36	520		T22	602
all_pins[2]	values[0x0]	61829269	1			T2	138		T3	5741		T17	215234
all_pins[2]	values[0x1]	271235	1			T14	1716		T36	520		T22	602
all_pins[2]	transitions[0x0=>0x1]	269626	1			T14	1704		T36	520		T22	602
all_pins[2]	transitions[0x1=>0x0]	292120	1			T3	58		T17	547		T7	12