Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8084369 |
1 |
|
|
T2 |
216 |
|
T3 |
6002 |
|
T17 |
2992 |
auto[1] |
8084330 |
1 |
|
|
T2 |
216 |
|
T3 |
6002 |
|
T17 |
2992 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
16036885 |
1 |
|
|
T2 |
432 |
|
T3 |
11948 |
|
T17 |
5984 |
triple_byte_access |
43826 |
1 |
|
|
T3 |
16 |
|
T7 |
8 |
|
T8 |
48 |
halfword_access |
43964 |
1 |
|
|
T3 |
22 |
|
T7 |
4 |
|
T8 |
34 |
byte_access |
44024 |
1 |
|
|
T3 |
18 |
|
T7 |
2 |
|
T8 |
36 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
8018462 |
1 |
|
|
T2 |
216 |
|
T3 |
5974 |
|
T17 |
2992 |
auto[0] |
triple_byte_access |
21913 |
1 |
|
|
T3 |
8 |
|
T7 |
4 |
|
T8 |
24 |
auto[0] |
halfword_access |
21982 |
1 |
|
|
T3 |
11 |
|
T7 |
2 |
|
T8 |
17 |
auto[0] |
byte_access |
22012 |
1 |
|
|
T3 |
9 |
|
T7 |
1 |
|
T8 |
18 |
auto[1] |
word_access |
8018423 |
1 |
|
|
T2 |
216 |
|
T3 |
5974 |
|
T17 |
2992 |
auto[1] |
triple_byte_access |
21913 |
1 |
|
|
T3 |
8 |
|
T7 |
4 |
|
T8 |
24 |
auto[1] |
halfword_access |
21982 |
1 |
|
|
T3 |
11 |
|
T7 |
2 |
|
T8 |
17 |
auto[1] |
byte_access |
22012 |
1 |
|
|
T3 |
9 |
|
T7 |
1 |
|
T8 |
18 |