Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170503 |
1 |
|
|
T4 |
2030 |
|
T15 |
101 |
|
T5 |
228 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
92429 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
55976 |
1 |
|
|
T4 |
148 |
|
T15 |
1 |
|
T5 |
224 |
seven_bytes |
3131 |
1 |
|
|
T4 |
48 |
|
T10 |
21 |
|
T11 |
30 |
six_bytes |
3148 |
1 |
|
|
T4 |
40 |
|
T15 |
1 |
|
T10 |
18 |
five_bytes |
3188 |
1 |
|
|
T4 |
51 |
|
T15 |
3 |
|
T10 |
19 |
four_bytes |
3136 |
1 |
|
|
T4 |
52 |
|
T15 |
3 |
|
T10 |
17 |
three_bytes |
3197 |
1 |
|
|
T4 |
58 |
|
T15 |
4 |
|
T10 |
15 |
two_bytes |
3149 |
1 |
|
|
T4 |
42 |
|
T10 |
13 |
|
T11 |
27 |
one_byte |
3149 |
1 |
|
|
T4 |
50 |
|
T15 |
2 |
|
T10 |
9 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
167309 |
1 |
|
|
T4 |
2004 |
|
T15 |
99 |
|
T5 |
220 |
auto[1] |
3194 |
1 |
|
|
T4 |
26 |
|
T15 |
2 |
|
T5 |
8 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170503 |
1 |
|
|
T4 |
2030 |
|
T15 |
101 |
|
T5 |
228 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170493 |
1 |
|
|
T4 |
2030 |
|
T15 |
101 |
|
T5 |
228 |
auto[1] |
10 |
1 |
|
|
T44 |
1 |
|
T24 |
1 |
|
T181 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1069 |
1 |
|
|
T4 |
7 |
|
T5 |
4 |
|
T17 |
3 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3194 |
1 |
|
|
T4 |
26 |
|
T15 |
2 |
|
T5 |
8 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
173015 |
1 |
|
|
T4 |
1304 |
|
T15 |
963 |
|
T5 |
337 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
93254 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
57579 |
1 |
|
|
T4 |
223 |
|
T15 |
18 |
|
T5 |
333 |
seven_bytes |
3218 |
1 |
|
|
T4 |
35 |
|
T15 |
25 |
|
T10 |
47 |
six_bytes |
3170 |
1 |
|
|
T4 |
25 |
|
T15 |
30 |
|
T10 |
50 |
five_bytes |
3234 |
1 |
|
|
T4 |
29 |
|
T15 |
29 |
|
T10 |
49 |
four_bytes |
3123 |
1 |
|
|
T4 |
34 |
|
T15 |
25 |
|
T10 |
46 |
three_bytes |
3202 |
1 |
|
|
T4 |
29 |
|
T15 |
38 |
|
T10 |
41 |
two_bytes |
3086 |
1 |
|
|
T4 |
28 |
|
T15 |
23 |
|
T10 |
41 |
one_byte |
3149 |
1 |
|
|
T4 |
30 |
|
T15 |
22 |
|
T10 |
43 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
169823 |
1 |
|
|
T4 |
1280 |
|
T15 |
949 |
|
T5 |
329 |
auto[1] |
3192 |
1 |
|
|
T4 |
24 |
|
T15 |
14 |
|
T5 |
8 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
173015 |
1 |
|
|
T4 |
1304 |
|
T15 |
963 |
|
T5 |
337 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
173002 |
1 |
|
|
T4 |
1304 |
|
T15 |
963 |
|
T5 |
337 |
auto[1] |
13 |
1 |
|
|
T59 |
1 |
|
T60 |
1 |
|
T182 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1078 |
1 |
|
|
T4 |
8 |
|
T15 |
4 |
|
T5 |
4 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3192 |
1 |
|
|
T4 |
24 |
|
T15 |
14 |
|
T5 |
8 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
344827 |
1 |
|
|
T4 |
3363 |
|
T15 |
940 |
|
T5 |
372 |
auto[1] |
609 |
1 |
|
|
T17 |
16 |
|
T18 |
65 |
|
T19 |
100 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
183585 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
118231 |
1 |
|
|
T4 |
365 |
|
T15 |
26 |
|
T5 |
367 |
seven_bytes |
6223 |
1 |
|
|
T4 |
82 |
|
T15 |
21 |
|
T10 |
76 |
six_bytes |
6325 |
1 |
|
|
T4 |
105 |
|
T15 |
18 |
|
T10 |
76 |
five_bytes |
6287 |
1 |
|
|
T4 |
78 |
|
T15 |
26 |
|
T10 |
75 |
four_bytes |
6155 |
1 |
|
|
T4 |
86 |
|
T15 |
22 |
|
T10 |
63 |
three_bytes |
6308 |
1 |
|
|
T4 |
92 |
|
T15 |
34 |
|
T10 |
66 |
two_bytes |
6192 |
1 |
|
|
T4 |
86 |
|
T15 |
30 |
|
T10 |
69 |
one_byte |
6130 |
1 |
|
|
T4 |
81 |
|
T15 |
25 |
|
T10 |
68 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
338804 |
1 |
|
|
T4 |
3309 |
|
T15 |
924 |
|
T5 |
362 |
auto[1] |
6632 |
1 |
|
|
T4 |
54 |
|
T15 |
16 |
|
T5 |
10 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
345436 |
1 |
|
|
T4 |
3363 |
|
T15 |
940 |
|
T5 |
372 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
345409 |
1 |
|
|
T4 |
3363 |
|
T15 |
940 |
|
T5 |
372 |
auto[1] |
27 |
1 |
|
|
T18 |
1 |
|
T61 |
1 |
|
T183 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2254 |
1 |
|
|
T4 |
11 |
|
T15 |
4 |
|
T5 |
5 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6632 |
1 |
|
|
T4 |
54 |
|
T15 |
16 |
|
T5 |
10 |