Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	170418157	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

125556938

1

T1

249525

T2

71148

T3

166

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	153444095	1			T1	329087		T2	95977		T3	78
values[0x0]	68572102	1			T1	154904		T2	40229		T3	46
values[0x1]	73958898	1			T1	169442		T2	44220		T3	57

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	132350804	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

163624291

1

T1

338381

T2

95845

T3

172

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	932515	1			T2	810		T6	448		T12	807
valid_sources[0x01]	3313467	1			T2	675		T6	463		T12	814
valid_sources[0x02]	1963918	1			T2	745		T6	514		T12	821
valid_sources[0x03]	907347	1			T2	629		T3	2		T6	452
valid_sources[0x04]	903249	1			T2	676		T6	465		T12	821
valid_sources[0x05]	1741972	1			T2	726		T6	474		T12	821
valid_sources[0x06]	897991	1			T2	660		T6	507		T12	829
valid_sources[0x07]	3262013	1			T2	705		T6	515		T12	803
valid_sources[0x08]	897642	1			T2	731		T6	447		T12	839
valid_sources[0x09]	1020314	1			T2	652		T6	411		T12	794
valid_sources[0x0a]	904193	1			T2	722		T6	412		T12	795
valid_sources[0x0b]	893286	1			T2	706		T3	5		T6	445
valid_sources[0x0c]	1454910	1			T2	669		T6	427		T12	835
valid_sources[0x0d]	1057079	1			T2	737		T6	447		T12	827
valid_sources[0x0e]	906790	1			T2	710		T6	487		T12	869
valid_sources[0x0f]	899093	1			T2	693		T6	476		T12	826
valid_sources[0x10]	917057	1			T2	727		T3	1		T6	482
valid_sources[0x11]	897770	1			T2	734		T3	2		T6	475
valid_sources[0x12]	907166	1			T2	659		T6	440		T12	906
valid_sources[0x13]	957107	1			T2	674		T6	453		T12	851
valid_sources[0x14]	934867	1			T2	687		T3	6		T6	453
valid_sources[0x15]	925638	1			T2	664		T6	440		T12	760
valid_sources[0x16]	902252	1			T2	751		T6	474		T12	873
valid_sources[0x17]	907219	1			T2	665		T3	6		T6	435
valid_sources[0x18]	931191	1			T2	705		T6	484		T12	874
valid_sources[0x19]	904402	1			T2	647		T6	467		T12	799
valid_sources[0x1a]	1562055	1			T2	689		T6	443		T12	799
valid_sources[0x1b]	903765	1			T2	677		T6	496		T12	781
valid_sources[0x1c]	988265	1			T2	732		T6	416		T12	811
valid_sources[0x1d]	902120	1			T2	718		T6	461		T12	800
valid_sources[0x1e]	1025956	1			T2	688		T6	412		T12	809
valid_sources[0x1f]	3405842	1			T2	694		T6	452		T12	839
valid_sources[0x20]	1783542	1			T2	717		T6	475		T12	802
valid_sources[0x21]	979273	1			T2	769		T6	428		T12	791
valid_sources[0x22]	905835	1			T2	700		T6	447		T12	827
valid_sources[0x23]	2403428	1			T2	722		T6	447		T12	819
valid_sources[0x24]	3211085	1			T2	716		T6	464		T12	828
valid_sources[0x25]	897654	1			T2	684		T6	447		T12	857
valid_sources[0x26]	899784	1			T2	745		T6	445		T12	827
valid_sources[0x27]	891942	1			T2	718		T6	448		T12	830
valid_sources[0x28]	1016794	1			T2	698		T6	452		T12	819
valid_sources[0x29]	901871	1			T2	660		T6	439		T12	798
valid_sources[0x2a]	998691	1			T2	642		T6	511		T12	832
valid_sources[0x2b]	901371	1			T2	705		T6	503		T12	801
valid_sources[0x2c]	898145	1			T2	722		T6	457		T12	833
valid_sources[0x2d]	900058	1			T2	719		T6	435		T12	857
valid_sources[0x2e]	943783	1			T2	650		T6	466		T12	866
valid_sources[0x2f]	901584	1			T2	701		T6	491		T12	823
valid_sources[0x30]	899967	1			T2	700		T6	453		T12	789
valid_sources[0x31]	905908	1			T2	729		T3	9		T6	482
valid_sources[0x32]	899284	1			T2	716		T6	498		T12	784
valid_sources[0x33]	901008	1			T2	633		T6	441		T12	832
valid_sources[0x34]	946146	1			T2	689		T6	472		T12	803
valid_sources[0x35]	900633	1			T2	724		T6	443		T12	824
valid_sources[0x36]	904581	1			T2	707		T6	506		T12	815
valid_sources[0x37]	903735	1			T2	723		T6	497		T12	813
valid_sources[0x38]	1160601	1			T2	724		T3	1		T6	470
valid_sources[0x39]	899098	1			T2	666		T6	469		T12	851
valid_sources[0x3a]	935567	1			T2	715		T3	1		T6	515
valid_sources[0x3b]	1828192	1			T2	715		T6	493		T12	869
valid_sources[0x3c]	899687	1			T2	685		T6	461		T12	838
valid_sources[0x3d]	936243	1			T2	683		T6	434		T12	823
valid_sources[0x3e]	894441	1			T2	717		T3	11		T6	450
valid_sources[0x3f]	1060982	1			T2	742		T6	470		T12	810
valid_sources[0x40]	898263	1			T2	715		T6	451		T12	842
valid_sources[0x41]	1099263	1			T2	741		T6	446		T12	813
valid_sources[0x42]	916899	1			T2	718		T6	518		T12	849
valid_sources[0x43]	1002432	1			T2	663		T6	498		T12	806
valid_sources[0x44]	1555963	1			T2	654		T6	492		T12	788
valid_sources[0x45]	901550	1			T2	680		T6	433		T12	843
valid_sources[0x46]	1550252	1			T1	653433		T2	734		T3	1
valid_sources[0x47]	921830	1			T2	719		T6	451		T12	829
valid_sources[0x48]	915873	1			T2	734		T6	428		T12	826
valid_sources[0x49]	1749060	1			T2	717		T6	455		T12	813
valid_sources[0x4a]	903432	1			T2	753		T6	451		T12	861
valid_sources[0x4b]	1112571	1			T2	660		T6	511		T12	824
valid_sources[0x4c]	895616	1			T2	707		T6	441		T12	825
valid_sources[0x4d]	898765	1			T2	704		T6	392		T12	838
valid_sources[0x4e]	902276	1			T2	725		T3	1		T6	497
valid_sources[0x4f]	900644	1			T2	701		T6	472		T12	861
valid_sources[0x50]	904435	1			T2	678		T6	533		T12	826
valid_sources[0x51]	1837636	1			T2	685		T6	437		T12	843
valid_sources[0x52]	904313	1			T2	728		T3	1		T6	467
valid_sources[0x53]	897210	1			T2	734		T6	476		T12	819
valid_sources[0x54]	907647	1			T2	652		T6	454		T12	809
valid_sources[0x55]	1463496	1			T2	679		T6	453		T12	823
valid_sources[0x56]	997266	1			T2	660		T6	469		T12	837
valid_sources[0x57]	897593	1			T2	715		T3	2		T6	489
valid_sources[0x58]	1740043	1			T2	702		T6	524		T12	807
valid_sources[0x59]	1791534	1			T2	638		T6	446		T12	854
valid_sources[0x5a]	905795	1			T2	718		T6	486		T12	815
valid_sources[0x5b]	898081	1			T2	711		T6	439		T12	854
valid_sources[0x5c]	1014399	1			T2	732		T6	452		T12	831
valid_sources[0x5d]	1782499	1			T2	736		T6	496		T12	832
valid_sources[0x5e]	899327	1			T2	700		T6	500		T12	785
valid_sources[0x5f]	908682	1			T2	686		T6	462		T12	817
valid_sources[0x60]	897555	1			T2	751		T6	442		T12	809
valid_sources[0x61]	901673	1			T2	717		T6	550		T12	834
valid_sources[0x62]	1344198	1			T2	692		T6	385		T12	767
valid_sources[0x63]	900508	1			T2	676		T6	470		T12	829
valid_sources[0x64]	1761579	1			T2	691		T6	472		T12	784
valid_sources[0x65]	903228	1			T2	724		T6	475		T12	822
valid_sources[0x66]	898538	1			T2	730		T6	455		T12	850
valid_sources[0x67]	898072	1			T2	673		T6	474		T12	828
valid_sources[0x68]	901192	1			T2	707		T6	472		T12	843
valid_sources[0x69]	974927	1			T2	672		T6	455		T12	877
valid_sources[0x6a]	900151	1			T2	701		T6	422		T12	839
valid_sources[0x6b]	937750	1			T2	722		T6	447		T12	820
valid_sources[0x6c]	1064080	1			T2	695		T6	518		T12	838
valid_sources[0x6d]	1902180	1			T2	736		T6	424		T12	833
valid_sources[0x6e]	897067	1			T2	689		T6	410		T12	866
valid_sources[0x6f]	899211	1			T2	710		T6	445		T12	890
valid_sources[0x70]	899574	1			T2	669		T6	488		T12	831
valid_sources[0x71]	933833	1			T2	679		T6	496		T12	840
valid_sources[0x72]	1541797	1			T2	714		T6	478		T12	808
valid_sources[0x73]	898939	1			T2	721		T3	3		T6	496
valid_sources[0x74]	1820394	1			T2	805		T6	445		T12	848
valid_sources[0x75]	2716015	1			T2	712		T6	406		T12	814
valid_sources[0x76]	904321	1			T2	728		T6	420		T12	825
valid_sources[0x77]	903471	1			T2	747		T6	399		T12	800
valid_sources[0x78]	1789642	1			T2	754		T6	438		T12	806
valid_sources[0x79]	912548	1			T2	733		T6	413		T12	845
valid_sources[0x7a]	987940	1			T2	728		T6	459		T12	814
valid_sources[0x7b]	916327	1			T2	710		T6	412		T12	859
valid_sources[0x7c]	896620	1			T2	689		T6	489		T12	897
valid_sources[0x7d]	915480	1			T2	740		T3	7		T6	433
valid_sources[0x7e]	902261	1			T2	702		T6	494		T12	834
valid_sources[0x7f]	903227	1			T2	732		T3	5		T6	419
valid_sources[0x80]	894512	1			T2	777		T3	6		T6	468

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48385138

1

T1

87575

T2

29012

T3

70

values[0x0]

all_enables

biggest_size

41320399

1

T1

87675

T2

22842

T3

43

values[0x1]

all_enables

biggest_size

35851401

1

T1

74275

T2

19294

T3

53