Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

171044606

1

T1

403908

T2

109278

T3

15

full_word

125595211

1

T1

249525

T2

71148

T3

166

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	296639527	1			T1	653433		T2	180426		T3	181
auto[TlIntgErrCmd]	91	1			T135	8		T136	8		T137	3
auto[TlIntgErrData]	99	1			T135	6		T136	8		T137	2
auto[TlIntgErrBoth]	100	1			T135	6		T136	4		T137	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

153587498

1

T1

329087

T2

95977

T3

78

auto[1]

143052319

1

T1

324346

T2

84449

T3

103

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	105191619	1			T1	241512		T2	66965		T3	8
auto[TlIntgErrNone]	partial	auto[1]	65852720	1			T1	162396		T2	42313		T3	7
auto[TlIntgErrNone]	full_word	auto[0]	48395744	1			T1	87575		T2	29012		T3	70
auto[TlIntgErrNone]	full_word	auto[1]	77199444	1			T1	161950		T2	42136		T3	96
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T135	2		T136	3		T188	1
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T135	5		T136	5		T137	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T187	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T135	1		T189	1		T190	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T135	2		T136	5		T137	2
auto[TlIntgErrData]	partial	auto[1]	42	1			T135	4		T136	1		T188	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T136	1		T191	1		T192	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T136	1		T191	2		T193	2
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T135	3		T136	2		T137	2
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T135	3		T136	2		T137	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T187	1		T189	1		T194	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T184	1		T187	1		T195	1