Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.05	87.50	92.68			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_app_intf.u_appid_arb	95.05	87.50	92.68			100.00	100.00

---

Module Instance : tb.dut.u_app_intf.u_appid_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.05	87.50	92.68			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.05	87.50	92.68			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.27	94.57	86.30		44.44	91.01	100.00	u_app_intf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		32	28	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	97	1	1	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	0	0.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	3	3
87	0	3
89	3	3
97	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	0	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	41	38	92.68
Logical	41	38	92.68
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T16,T4
0	1	Covered	T3,T4,T15
1	0	Covered	T16,T4,T15

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T16,T4
0	1	Covered	T3,T4,T15
1	0	Covered	T16,T4,T15

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T15
0	1	Unreachable
1	0	Covered	T3,T4,T15

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T16,T4
1	Covered	T3,T16,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T16,T4
1	Covered	T3,T16,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T3,T4,T15
1	Covered	T3,T4,T15

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T16,T4
1	Covered	T3,T16,T4

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T16,T4
1	Covered	T3,T16,T4

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T3,T4,T15
1	Covered	T3,T4,T15

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T16,T4
1	0	Covered	T4,T15,T5
1	1	Covered	T16,T4,T15

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T16,T4
1	0	Covered	T4,T15,T5
1	1	Covered	T16,T4,T15

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T15
1	0	Not Covered
1	1	Covered	T4,T15,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T16,T4
1	0	Covered	T16,T4,T15
1	1	Covered	T4,T15,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T16,T4
1	0	Covered	T16,T4,T15
1	1	Covered	T4,T15,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T15
1	0	Covered	T4,T15,T5
1	1	Not Covered

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T16,T4
1	1	Covered	T16,T4,T15

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T16,T4
0	Covered	T3,T16,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T16,T4
0	Covered	T3,T16,T4

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T16,T4
0	Covered	T3,T16,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T16,T4
0	Covered	T3,T16,T4

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T15
0	Covered	T3,T4,T15

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T15
0	Covered	T3,T4,T15

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1514977704	1514786187	0	0
CheckNGreaterZero_A	942	942	0	0
GntImpliesReady_A	1514977704	7037	0	0
GntImpliesValid_A	1514977704	7037	0	0
GrantKnown_A	1514977704	1514786187	0	0
IdxKnown_A	1514977704	1514786187	0	0
IndexIsCorrect_A	1514977704	7037	0	0
NoReadyValidNoGrant_A	1514977704	1511287603	0	0
Priority_A	1514977704	3498584	0	0
ReadyAndValidImplyGrant_A	1514977704	7037	0	0
ReqAndReadyImplyGrant_A	1514977704	7037	0	0
ReqImpliesValid_A	1514977704	3498584	0	0
ValidKnown_A	1514977704	1514786187	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	1514786187	0	0
T1	476048	476038	0	0
T2	400886	400824	0	0
T3	3181	3021	0	0
T4	352477	352376	0	0
T6	101372	101362	0	0
T12	226917	226911	0	0
T16	4958	4907	0	0
T38	19134	19072	0	0
T39	19055	18975	0	0
T40	147488	147481	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	7037	0	0
T4	352477	52	0	0
T5	128982	13	0	0
T10	0	31	0	0
T11	0	46	0	0
T15	199064	16	0	0
T16	4958	1	0	0
T17	0	29	0	0
T26	0	2	0	0
T27	235619	0	0	0
T38	19134	0	0	0
T39	19055	0	0	0
T40	147488	0	0	0
T41	851363	0	0	0
T42	102644	0	0	0
T44	0	34	0	0
T92	0	1	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	7037	0	0
T4	352477	52	0	0
T5	128982	13	0	0
T10	0	31	0	0
T11	0	46	0	0
T15	199064	16	0	0
T16	4958	1	0	0
T17	0	29	0	0
T26	0	2	0	0
T27	235619	0	0	0
T38	19134	0	0	0
T39	19055	0	0	0
T40	147488	0	0	0
T41	851363	0	0	0
T42	102644	0	0	0
T44	0	34	0	0
T92	0	1	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	1514786187	0	0
T1	476048	476038	0	0
T2	400886	400824	0	0
T3	3181	3021	0	0
T4	352477	352376	0	0
T6	101372	101362	0	0
T12	226917	226911	0	0
T16	4958	4907	0	0
T38	19134	19072	0	0
T39	19055	18975	0	0
T40	147488	147481	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	1514786187	0	0
T1	476048	476038	0	0
T2	400886	400824	0	0
T3	3181	3021	0	0
T4	352477	352376	0	0
T6	101372	101362	0	0
T12	226917	226911	0	0
T16	4958	4907	0	0
T38	19134	19072	0	0
T39	19055	18975	0	0
T40	147488	147481	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	7037	0	0
T4	352477	52	0	0
T5	128982	13	0	0
T10	0	31	0	0
T11	0	46	0	0
T15	199064	16	0	0
T16	4958	1	0	0
T17	0	29	0	0
T26	0	2	0	0
T27	235619	0	0	0
T38	19134	0	0	0
T39	19055	0	0	0
T40	147488	0	0	0
T41	851363	0	0	0
T42	102644	0	0	0
T44	0	34	0	0
T92	0	1	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	1511287603	0	0
T1	476048	476038	0	0
T2	400886	400824	0	0
T3	3181	1552	0	0
T4	352477	351701	0	0
T6	101372	101362	0	0
T12	226917	226911	0	0
T16	4958	4829	0	0
T38	19134	19072	0	0
T39	19055	18975	0	0
T40	147488	147481	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	3498584	0	0
T3	3181	1469	0	0
T4	352477	6749	0	0
T5	0	5410	0	0
T6	101372	0	0	0
T10	0	11770	0	0
T11	0	7059	0	0
T12	226917	0	0	0
T15	0	2020	0	0
T16	4958	78	0	0
T17	0	6013	0	0
T26	0	835	0	0
T27	235619	0	0	0
T38	19134	0	0	0
T39	19055	0	0	0
T40	147488	0	0	0
T41	851363	0	0	0
T44	0	2283	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	7037	0	0
T4	352477	52	0	0
T5	128982	13	0	0
T10	0	31	0	0
T11	0	46	0	0
T15	199064	16	0	0
T16	4958	1	0	0
T17	0	29	0	0
T26	0	2	0	0
T27	235619	0	0	0
T38	19134	0	0	0
T39	19055	0	0	0
T40	147488	0	0	0
T41	851363	0	0	0
T42	102644	0	0	0
T44	0	34	0	0
T92	0	1	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	7037	0	0
T4	352477	52	0	0
T5	128982	13	0	0
T10	0	31	0	0
T11	0	46	0	0
T15	199064	16	0	0
T16	4958	1	0	0
T17	0	29	0	0
T26	0	2	0	0
T27	235619	0	0	0
T38	19134	0	0	0
T39	19055	0	0	0
T40	147488	0	0	0
T41	851363	0	0	0
T42	102644	0	0	0
T44	0	34	0	0
T92	0	1	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	3498584	0	0
T3	3181	1469	0	0
T4	352477	6749	0	0
T5	0	5410	0	0
T6	101372	0	0	0
T10	0	11770	0	0
T11	0	7059	0	0
T12	226917	0	0	0
T15	0	2020	0	0
T16	4958	78	0	0
T17	0	6013	0	0
T26	0	835	0	0
T27	235619	0	0	0
T38	19134	0	0	0
T39	19055	0	0	0
T40	147488	0	0	0
T41	851363	0	0	0
T44	0	2283	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	1514786187	0	0
T1	476048	476038	0	0
T2	400886	400824	0	0
T3	3181	3021	0	0
T4	352477	352376	0	0
T6	101372	101362	0	0
T12	226917	226911	0	0
T16	4958	4907	0	0
T38	19134	19072	0	0
T39	19055	18975	0	0
T40	147488	147481	0	0